Market Size (2025)
$1.28B
Vertical: SEMIBase Year: 2025
Market Size (2025)
$1.28B
Projected (2032)
$2.06B
CAGR (2022–2032)
6.2%
Key Players
10+
Market Overview
The global CMP pads market was valued at USD 1.276 billion in 2025 and is projected to reach USD 2.057 billion by 2032, expanding at a compound annual growth rate (CAGR) of 7.0% over 2026–2032. In absolute terms, the market is expected to add USD 0.781 billion between 2025 and 2032. Chemical mechanical planarization (CMP) pads are engineered polymer consumables, most commonly porous cast polyurethane or polyurethane-impregnated non-woven felts, that are mounted on the rotating platen of a CMP tool and work together with abrasive slurry to remove material and flatten the wafer surface between successive deposition and patterning steps. Because a pad wears out after a defined number of wafers and must be replaced, demand tracks wafer starts, the number of CMP steps per wafer and the pad life achieved on each step, rather than capital spending cycles alone.
The historical series shows that the market is sensitive to memory pricing and fab utilisation. Revenue fell from USD 1.124 billion in 2022 to USD 1.048 billion in 2023, when the memory downturn led DRAM and NAND producers to cut wafer starts and run lines at reduced loading. The market recovered to USD 1.161 billion in 2024 as utilisation improved at leading-edge logic foundries and high-bandwidth memory (HBM) production expanded, and it reached USD 1.276 billion in 2025. The forecast period is shaped by three structural factors: a higher count of planarization steps in gate-all-around (GAA) logic, backside power delivery and 3D NAND with more word-line layers; the spread of CMP into advanced packaging steps such as through-silicon via (TSV) reveal and hybrid bonding; and the construction of new 300 mm capacity in the United States, Japan, Europe, India and China under national semiconductor programmes. SEMI reported in October 2026 that global 300 mm fab equipment spending is projected to rise 31% to USD 149 billion in 2026 and to reach USD 227 billion by 2029, which indicates the scale of the installed base that will consume pads over the forecast years.
The trajectory is steady rather than abrupt. The market rises in every forecast year, from USD 1.372 billion in 2026 to USD 1.804 billion in 2030 and USD 2.057 billion in 2032, which reflects compounding on a larger base and a gradual shift of the mix towards higher-value pad formats for advanced nodes and packaging. Pricing is expected to remain broadly stable for mature-node pads, while premium pads with tighter defectivity specifications, integrated endpoint windows and customised groove patterns are expected to carry higher average selling prices.
Key Findings
By pad type, hard pads were the largest segment in 2025 with a value of USD 0.702 billion and a 55.0% share, because rigid, closed-cell polyurethane pads are the process-of-record for oxide, shallow trench isolation (STI), tungsten and bulk copper steps that require high planarization efficiency. Composite / stacked pads are the fastest-growing pad type with a CAGR of 10.1% over 2026–2032, rising from USD 0.190 billion in 2025 to USD 0.376 billion in 2032, as fabs adopt engineered multilayer constructions that combine a stiff top layer with a compliant sub-pad to balance local planarity and global uniformity.
By application, oxide / ILD & STI CMP was the largest segment, accounting for USD 0.420 billion and a 32.9% share in 2025. Advanced packaging (TSV / hybrid bonding) is the fastest-growing application at a CAGR of 13.6%, increasing from USD 0.123 billion in 2025 to USD 0.308 billion in 2032, as hybrid bonding for HBM stacks, chip-on-wafer integration and wafer-to-wafer bonding requires very flat dielectric and copper surfaces.
By wafer size, the 300 mm segment was both the largest and the fastest-growing category. It was valued at USD 0.891 billion in 2025, a 69.8% share, and is projected to reach USD 1.533 billion by 2032 at a CAGR of 8.0%. The 200 mm segment, at USD 0.302 billion in 2025, remains important for power, analog, MEMS and silicon carbide (SiC) devices.
By end user, foundries were the largest segment with USD 0.471 billion and a 36.9% share in 2025, reflecting the concentration of leading-edge logic production at pure-play foundries. OSATs & advanced packaging houses are the fastest-growing end user, with a CAGR of 10.7% that takes the segment from USD 0.081 billion in 2025 to USD 0.165 billion in 2032.
By region, Asia Pacific led the market in 2025 with USD 0.968 billion and a 75.8% share, while North America is the fastest-growing region at a CAGR of 9.7%. Among individually reported countries, China was the largest market at USD 0.363 billion in 2025, equal to 28.4% of the global total; the Rest of Asia Pacific grouping, which includes Taiwan, South Korea, Singapore and Malaysia, was larger in aggregate at USD 0.423 billion. Saudi Arabia is the fastest-growing country at a CAGR of 12.3%, although from a very small base of USD 0.003 billion in 2025.
Segmentation Summary
The market is assessed across four product and demand segmentations, namely pad type, application, wafer size and end user, together with five regions and twenty country-level markets. The pattern across the segmentations is consistent: the established categories that support high-volume front-end processing (hard pads, oxide / ILD & STI CMP, 300 mm wafers and foundries) hold the largest shares, while the categories linked to heterogeneous integration and more complex device stacks (composite / stacked pads, advanced packaging and OSATs) post the highest growth rates. Table 1.1 summarises the largest and fastest-growing segment in each segmentation.
Two points stand out from the summary. First, growth leadership in three of the four product segmentations sits with segments that currently account for less than 15% of value, which means that the competitive position of suppliers in these smaller categories will matter more by 2032 than their present size suggests. Second, the 300 mm wafer segment is the only case in which the largest segment also grows fastest, because almost all new fab capacity added during the forecast period uses 300 mm wafers, including power and analog lines that historically ran on 200 mm.
Regional and Country Highlights
Asia Pacific is the centre of demand because it hosts the largest foundry, memory and wafer-manufacturing bases. Within the region, the Rest of Asia Pacific grouping held 43.7% of regional value in 2025 and China held 37.5%, while India is the fastest-growing market at a CAGR of 11.9%, supported by the start of commercial assembly and test operations at Micron's Sanand facility, inaugurated on 28 February 2026, and by construction of the Tata Electronics–PSMC 300 mm fab at Dholera. Japan, valued at USD 0.140 billion in 2025, benefits from the TSMC-led JASM operation in Kumamoto and the Rapidus 2 nm pilot line in Hokkaido.
North America, valued at USD 0.147 billion in 2025 and projected to reach USD 0.276 billion in 2032, is the fastest-growing region. The U.S. accounted for 90.2% of the regional market in 2025, while Mexico is the fastest-growing country in the region at a CAGR of 11.1%. Growth in the U.S. is linked to new leading-edge logic and memory fabs supported by the CHIPS and Science Act and to domestic pad capacity, including the 385,000-square-foot facility that Qnity opened in Newark, Delaware, in March 2026.
Europe was valued at USD 0.089 billion in 2025, with Germany holding 33.0% of the regional market and Italy growing fastest at a CAGR of 8.5%. The opening of Infineon's 300 mm Smart Power Fab in Dresden in July 2026 and the construction of ESMC in the same city support demand for power and logic pads. Latin America, at USD 0.020 billion, is led by Brazil with a 56.0% regional share, and Brazil is also the fastest-growing country in that region at 8.8%. In the Middle East & Africa, valued at USD 0.052 billion, the Rest of MEA grouping, which includes Israel's established fab base, held 81.4% of regional value, while Saudi Arabia grows fastest at 12.3%.
Competitive Landscape Summary
The CMP pads market is consolidated. A small group of suppliers with deep polyurethane chemistry, pad-design and fab-qualification experience accounts for most of the revenue, and the cost and time of qualifying a new pad on a production step act as a strong barrier to entry. Qnity Electronics, which completed its separation from DuPont on 1 November 2025, is the leading supplier of hard pads through the IC1000, Ikonic and newer Emblem platforms and has extended its soft-pad range with the Optivision Max family launched on 10 June 2026. Entegris, which acquired CMC Materials in July 2022, offers pads alongside slurries, pad conditioners, filters and post-CMP cleans, and announced USD 700 million of U.S. research and development spending on 21 August 2025 that includes CMP pads. Fujibo Holdings leads the soft-pad category, especially for final polishing of silicon wafers, and announced on 28 November 2025 an investment of JPY 8.7 billion to add polishing-material capacity at Fujibo Ehime.
Challengers include Hubei Dinglong, whose CMP pad revenue grew 52.3% in 2025 to RMB 1.091 billion as Chinese fabs localised consumables, and Enpulse, the Korean pad business acquired from SK enpulse by private equity firm Hahn & Co. under an agreement signed in December 2024. KPX Chemical, IVT Technologies, FNS Tech, TWI Incorporated and 3M serve specific steps, customers or regions. Competition centres on defectivity, removal-rate stability over pad life, lot-to-lot consistency, local technical support and supply assurance, rather than on list price.
Challenges and Opportunities
The main challenges are cyclical exposure to memory wafer starts, long qualification cycles that slow the adoption of new pad designs, and input-cost pressure on polyurethane prepolymers, curatives and specialty fillers. Trade measures add uncertainty: the United States imposed a Section 232 tariff of 25% on certain advanced computing chips from 15 January 2026 while negotiations on broader semiconductor tariffs continue, and China's export-licensing regime for gallium and germanium remains in place even though its outright ban on shipments to the United States is suspended until 27 November 2026. Regulatory scrutiny of chemicals used in pad manufacture and fab operations, including the proposed EU-wide PFAS restriction and REACH requirements for diisocyanate handling, also raises compliance costs.
The opportunities are closely tied to device complexity. Hybrid bonding for HBM and logic-on-logic stacking creates new planarization steps with very tight surface specifications. Silicon carbide and gallium nitride power devices require specialised pads for hard, chemically inert substrates. Localisation programmes in China, India, Japan, the United States and Europe create openings for suppliers that build regional manufacturing and application laboratories. Pad recycling and longer-life designs, such as the circularity work Entegris presented at its CMP Technology Day in Dresden on 8 October 2026, also respond to fab sustainability targets.
Future Outlook
Between 2025 and 2032 the market is expected to grow by USD 0.781 billion, with the forecast CAGR of 7.0% exceeding the growth of wafer starts because each advanced wafer consumes more pad area per unit of output. The mix will shift gradually towards 300 mm, composite / stacked constructions and packaging applications, while hard pads will retain the largest share because the core front-end planarization steps continue to rely on them. Regionally, Asia Pacific will remain the dominant source of demand, and North America will gain share as new fabs ramp. Supplier strategies are likely to focus on local-for-local production, co-development with chipmakers on node-specific pad designs, integrated offerings that combine pads with slurries and conditioners, and measurable reductions in slurry use and pad change frequency that lower cost of ownership for fabs.
Several uncertainties could move the outcome within the forecast range. A sharper or longer memory correction would reduce pad consumption at DRAM and NAND fabs, as happened in 2023, while faster adoption of hybrid bonding beyond HBM, for example in logic-on-logic stacking and image sensors, would lift the packaging segments above their current trajectory. The pace of construction at announced fabs is another variable, since several projects in the United States, Europe and India have moved their production start dates during 2025 and 2026. On the supply side, the entry of domestic Chinese suppliers into higher-specification steps and the continued investment by Qnity, Entegris and Fujibo in capacity close to customers are expected to keep supply adequate, with qualification speed and technical service, rather than capacity, acting as the main determinant of share gains.
The CMP Pads Market market is projected to grow at a CAGR of 6.2% from 2022 to 2032.
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View Subscription PlansDefinition
A CMP pad is a consumable polishing surface used in chemical mechanical planarization, the process step that removes excess material from a semiconductor wafer and leaves a surface that is flat at both the local (die) and global (wafer) scale. In a typical rotary CMP tool, the pad is laminated to a rotating platen with a pressure-sensitive adhesive. The wafer is held face down in a carrier head that applies a controlled down-force through a flexible membrane, while abrasive slurry is dispensed onto the pad. Material removal results from the combined effect of chemical reactions between the slurry and the film, such as oxidation of copper or tungsten or hydrolysis of silicon dioxide, and mechanical abrasion by slurry particles that are trapped between the wafer and the asperities on the pad surface. A diamond pad conditioner sweeps across the pad during or between polishes to cut away glazed material, reopen surface pores and maintain a consistent texture, so that removal rate stays stable from the first to the last wafer of the pad's life.
The pad performs several functions that slurry alone cannot. It transports fresh slurry to the wafer and carries away reaction products and debris through its pores and machined grooves. It transmits pressure to the high points of the wafer topography, which is the basis of planarization, and its stiffness determines how far that pressure is shared across neighbouring features. Its compliance allows it to follow the long-range bow of the wafer so that removal is uniform from centre to edge. Finally, its surface chemistry and hardness influence the number of scratches, residual particles and other defects left on the wafer. Pad properties that suppliers engineer and fabs specify include hardness (commonly reported on the Shore D scale for hard pads and Asker C for soft pads), density and porosity, pore size distribution, modulus and its temperature dependence, thickness, groove geometry (concentric, radial, XY or spiral patterns), sub-pad compliance, and the presence of a transparent window that allows optical or eddy-current endpoint detection through the pad.
Most hard CMP pads are made by reacting an isocyanate-terminated polyurethane prepolymer, typically based on toluene diisocyanate (TDI) or methylene diphenyl diisocyanate (MDI) and polyether or polyester polyols, with an aromatic diamine or polyol curative. Porosity is introduced by adding hollow polymeric microspheres, by blowing with gas or by other foaming routes. The mixture is cast into a cake or mould, cured, sliced or skived into sheets of the required thickness, laminated to a sub-pad where a stacked construction is required, grooved and finished. Soft pads are generally poromeric polyurethane on a non-woven or film substrate, made by coagulating a polyurethane solution so that it forms a nap of vertical, open pores, or polyurethane-impregnated non-woven felts. Composite or stacked pads combine layers with different properties, for example a hard top layer over a compliant foam sub-pad, and newer designs use additive manufacturing or engineered fixed structures to control the distribution and height of asperities more precisely than conventional casting allows.
In this study, the market comprises CMP pads used in semiconductor manufacturing and in the preparation of semiconductor substrates. Included are hard, soft and composite / stacked pads used for front-end planarization of dielectric films (pre-metal and inter-layer dielectrics, STI and related steps), copper and barrier layers, tungsten, cobalt, molybdenum, ruthenium and other metals, polysilicon and nitride films; pads used for stock removal and final polishing of silicon wafers and for compound substrates such as SiC, gallium nitride, gallium arsenide, indium phosphide and sapphire; and pads used in advanced packaging, including TSV reveal, redistribution-layer planarization, and dielectric and copper preparation for hybrid bonding. Pads supplied in all diameters for 300 mm, 200 mm and 150 mm-and-below tools are included, together with sub-pads sold as part of a pad assembly and pads supplied with integrated endpoint windows.
CMP steps occur throughout the device flow. In the front end of line, CMP planarizes the oxide that fills isolation trenches and, in replacement-metal-gate logic, removes overburden from the dummy poly gate and the metal gate stack. In the middle of line, tungsten or cobalt contacts are polished back to the dielectric. In the back end of line, each copper interconnect level requires a sequence of bulk copper, copper clearing and barrier steps, and each inter-layer dielectric may be planarized before the next level is patterned. Memory adds further steps: 3D NAND requires planarization of the thick staircase oxide and of the peripheral circuitry, and DRAM uses CMP on storage-node, bit-line and capacitor structures. Beyond the device wafer, silicon wafer manufacturers polish both faces and the edge of every prime wafer before it is shipped, and packaging sites polish dielectric and copper surfaces before bonding. A leading-edge logic flow can therefore include several dozen CMP steps, each with its own pad specification, and each new architecture tends to add steps rather than remove them.
The way a pad is consumed explains why the market behaves like a recurring materials business. Each pad has a finite life, usually expressed as the number of wafers or the hours of polishing it can support before its thickness, groove depth or removal rate falls outside the process window. Pad life varies widely by step: a hard pad on a long oxide polish may be changed far more often than a soft buffing pad on a short barrier clean-up step, and a pad on a high-pressure SiC polish wears differently from a pad on a low-pressure copper step. Replacing a pad requires the tool to be taken out of production, the new pad to be broken in with dummy wafers and the process to be re-verified, so fabs value pads that last longer and stabilise quickly as much as they value low unit prices. Pad consumption per wafer therefore depends on the number of CMP steps in the process flow, the pad life on each step and the wafer diameter, and these three factors together translate fab output into pad demand.
Fabs judge a pad against a set of measurable outcomes. Removal rate and its stability across pad life determine throughput and how often the recipe must be adjusted. Within-wafer non-uniformity measures how evenly material is removed from the centre to the edge. Dishing and erosion describe how far soft metal lines and dense arrays are recessed below the surrounding dielectric, which affects line resistance and the flatness of the next level. Defectivity covers micro-scratches, embedded particles, residues and corrosion, and is usually the most heavily weighted criterion at advanced nodes because a single scratch can kill a die. Planarization efficiency describes how quickly a pad reduces step height relative to blanket removal. Cost of ownership combines the pad price with pad life, break-in time, conditioner wear, slurry consumption and tool downtime. Because these outcomes conflict, for example harder pads planarize better but tend to scratch more, pad development is largely a matter of shifting the trade-off curve for a specific step.
Hard, soft and composite pads perform different roles in a process flow. Hard pads, with high modulus and closed or semi-closed cells, resist deformation into recessed areas and therefore remove high features faster than low ones; they are used where planarization efficiency is the priority, such as STI, inter-layer dielectric and bulk metal removal. Soft pads deform more easily, conform to the wafer surface and produce fewer scratches; they are used for barrier removal, buffing, final polishing of silicon wafers and other steps where low defectivity and smooth surfaces matter more than step-height reduction. Composite and stacked pads aim to combine both behaviours, using a firm upper layer for local planarity and a compliant lower layer for global uniformity, and are increasingly specified for multi-step polishing sequences in which the same platen handles more than one film. Pad selection is always made together with slurry selection, conditioner design and tool settings, so a pad is qualified as part of a complete process recipe rather than as an independent component.
Excluded from the market are CMP slurries, pad conditioners and diamond discs, retaining rings, post-CMP cleaning chemicals and brushes, filters, CMP equipment and its spare parts, and services such as pad recycling or refurbishing when billed separately. Also excluded are polishing pads used outside semiconductor manufacturing, such as pads for optical glass, hard disk drive media, display glass, metallurgical sample preparation and general lapping, even where the same supplier manufactures them. Values are measured at the level of the pad manufacturer's revenue from sales to device manufacturers, wafer manufacturers and packaging houses, including sales made through distributors.
Scope of the Study
The study covers the global CMP pads market, segmented in the same way as the underlying market model. By pad type, the market is divided into hard pads, soft pads, and composite / stacked pads. By application, it is divided into oxide / ILD & STI CMP; copper & barrier CMP; tungsten & other metal CMP; silicon & compound substrate polishing; and advanced packaging (TSV / hybrid bonding). By wafer size, it is divided into 300 mm, 200 mm, and 150 mm & below. By end user, it is divided into foundries; memory manufacturers (DRAM / NAND / HBM); IDMs (logic, analog & power); silicon & compound wafer manufacturers; and OSATs & advanced packaging houses.
Geographically, the study covers five regions and twenty country-level markets. North America includes the U.S., Canada and Mexico. Europe includes Germany, the U.K., France, Italy, Spain and the Rest of Europe. Asia Pacific includes China, India, Japan and the Rest of Asia Pacific, the last of which contains major producing economies such as Taiwan and South Korea as well as Singapore, Malaysia and other Southeast Asian markets. Latin America includes Brazil, Argentina and the Rest of Latin America. The Middle East & Africa includes the UAE, Saudi Arabia, South Africa and the Rest of MEA. Each region and each country is analysed across all four product and demand segmentations.
The historical period covers 2022, 2023 and 2024, with 2025 as the base year. The forecast period runs from 2026 to 2032, and compound annual growth rates are presented for 2026–2032. All values are expressed in USD billion at current prices, with values shown to three decimal places and shares and growth rates to one decimal place. Revenue is attributed to the country in which the pad is consumed, that is, the location of the fab, wafer plant or packaging site, rather than the country in which the pad is manufactured or the supplier is headquartered. This allocation is important in CMP pads because a large share of global supply is produced in the United States, Japan, South Korea, Taiwan and China and shipped to fabs in other countries.
The segment definitions follow the process step and the customer rather than the pad brand. Oxide / ILD & STI CMP covers planarization of silicon dioxide and related dielectric films used for isolation, pre-metal dielectric and inter-layer dielectric, as well as nitride and polysilicon steps that run on similar pads. Copper & barrier CMP covers bulk copper removal, soft landing and barrier or liner removal in damascene interconnects. Tungsten & other metal CMP covers tungsten contacts and plugs together with cobalt, molybdenum, ruthenium and other metals introduced at advanced nodes. Silicon & compound substrate polishing covers double-side polishing, edge polishing and final polishing of prime silicon wafers and the polishing of SiC, gallium nitride, gallium arsenide, indium phosphide and sapphire substrates. Advanced packaging (TSV / hybrid bonding) covers TSV reveal, redistribution-layer and interposer planarization, and dielectric and copper preparation for direct bonding.
On the customer side, foundries are contract manufacturers producing logic and specialty devices for third parties. Memory manufacturers (DRAM / NAND / HBM) are producers of dynamic and flash memory, including the stacked DRAM used in HBM. IDMs (logic, analog & power) are integrated device makers that design and manufacture their own logic, microcontroller, analog, mixed-signal, power and sensor devices. Silicon & compound wafer manufacturers are suppliers of polished prime and epitaxial wafers and compound substrates to device makers. OSATs & advanced packaging houses are outsourced assembly and test companies and the advanced packaging operations of foundries and memory makers where they are organised as separate packaging sites. Where a single company operates in more than one category, its pad consumption is allocated according to the activity carried out at each site.
The study considers the demand side through wafer starts by node and device type, the number of CMP steps per process flow and the pad life typical for each step, and the supply side through supplier capacity, qualification positions, pricing and regional manufacturing footprints. Qualitative analysis covers market dynamics, the value chain, competitive forces, regulation and the macro environment. The competitive assessment covers the leading pad suppliers and their recent product, capacity and partnership developments from 2022 onward.
Research Objectives
To estimate the size of the global CMP pads market for 2022–2025 and forecast it for 2026–2032 in USD billion, with consistent segment, regional and country splits.
To quantify demand by pad type and explain how hard, soft and composite / stacked pads are matched to specific planarization and polishing steps.
To assess how new device architectures, including gate-all-around transistors, backside power delivery, high-layer-count 3D NAND and HBM, change the number of CMP steps and pad consumption per wafer.
To evaluate the growth of CMP pad demand in advanced packaging, particularly TSV reveal and hybrid bonding, and its effect on OSATs and integrated device makers.
To analyse the regional distribution of pad demand in relation to new fab construction, localisation policy and supply-chain diversification in Asia Pacific, North America, Europe, Latin America and the Middle East & Africa.
To examine the competitive structure of the market, including supplier positioning, qualification barriers and recent product launches, investments and transactions.
To identify regulatory, trade and raw-material factors, such as chemical restrictions, export controls and polyurethane input costs, that influence pad supply and pricing.
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View Subscription PlansOverview of the Research Process
The study follows a structured process designed for a consumable whose demand is set by semiconductor manufacturing activity and whose supply is concentrated in a small number of specialised producers. The work began with the definition of the product scope, which separated CMP pads from adjacent consumables such as slurries, pad conditioners and post-CMP cleans, and with the agreement of the segmentation framework by pad type, application, wafer size, end user, region and country. The second stage assembled a fact base from secondary sources covering wafer fab capacity, wafer starts by node and device type, process flows, supplier revenues, product portfolios and trade data. The third stage tested and refined this fact base through primary discussions with participants across the supply chain, including pad manufacturers, raw-material suppliers, CMP tool and conditioner suppliers, process engineers at device makers and procurement staff at fabs and wafer plants.
Market sizing combined a top-down view, which started from total semiconductor materials spending and the share attributable to CMP consumables, with a bottom-up view, which built pad consumption from wafer starts, CMP steps per wafer and pad life. The two views were reconciled through data triangulation, and differences were investigated until the estimates converged within an acceptable range. Forecasts were then developed by linking the drivers of pad consumption, such as capacity additions, node migration, packaging adoption and pricing, to the base-year estimate. Each stage included internal review by analysts with semiconductor materials experience, and the final dataset was checked for arithmetic consistency so that every segmentation sums to the same total for each year and every region equals the sum of its countries.
The process was iterative rather than linear. Findings from primary interviews frequently led to revisions of the secondary fact base, for example when engineers indicated that a particular node used more or fewer pad changes than published process descriptions implied, or when suppliers clarified how revenue from sub-pads and window inserts is booked. Likewise, the forecast assumptions were revisited when new information on fab schedules, export controls or trade measures emerged during 2025 and 2026. This approach is suited to the CMP pads market because the product is technically specific, revenue is concentrated, and public disclosure at the level of individual pad lines is limited, so that no single source is sufficient on its own.
Secondary Research
Secondary research drew on several categories of sources relevant to semiconductor consumables. Industry associations provided the macro context and capacity data. SEMI publications, including its World Fab Forecast, 300mm Fab Outlook and Materials Market Data Subscription, were used to understand fab construction, equipment spending, installed capacity by region and wafer size, and the size of the wafer fab materials market. The Semiconductor Industry Association and the World Semiconductor Trade Statistics organisation provided device sales by product category and region, which helped to relate pad demand to logic, memory, analog and discrete output. Regional bodies such as the Korea Semiconductor Industry Association, the Taiwan Semiconductor Industry Association, the Japan Electronics and Information Technology Industries Association and the China Semiconductor Industry Association provided country-level production and investment information.
Government and regulatory sources were used for policy, trade and chemical-regulation inputs. These included the U.S. Department of Commerce and its CHIPS Program Office, the Bureau of Industry and Security, the U.S. International Trade Commission, the European Commission and the European Chemicals Agency, Japan's Ministry of Economy, Trade and Industry, China's Ministry of Industry and Information Technology and Ministry of Commerce, India's Ministry of Electronics and Information Technology and the India Semiconductor Mission, and national customs and trade statistics agencies. Customs data under the Harmonized System headings that cover polishing articles and polyurethane sheets were reviewed for directional trade flows, recognising that these headings also include non-semiconductor products.
Company sources formed the core of the supply-side analysis. Annual reports, quarterly results, investor presentations, securities filings and press releases were reviewed for Qnity Electronics, DuPont, Entegris, Fujibo Holdings, Hubei Dinglong, KPX Chemical, 3M and other suppliers, as well as for the principal chipmakers and wafer suppliers whose capital expenditure and capacity plans determine pad consumption. Brokerage research on listed suppliers, particularly in China, Japan and South Korea, was used to cross-check segment revenues where companies disclose CMP pad sales separately. Technical literature formed a further category: conference proceedings from the International CMP Planarization Conference, the CMP Users Group, SEMICON technical symposia, IEEE conferences and the Electrochemical Society, together with patents, were used to understand pad materials, pad-life ranges and process trends. Trade and technical journals covering semiconductor manufacturing and electronic materials supplemented these sources, and paid databases on fab capacity, company financials and trade flows were used where open sources were incomplete.
Primary Research
Primary research was used to validate assumptions that cannot be observed directly in published sources, such as the number of CMP steps in specific process flows, typical pad life by application, the split of pad types within each application, the regional pattern of consumption and current pricing. Interviews were conducted through structured telephone and video discussions, supplemented by written questionnaires for detailed quantitative questions and follow-up exchanges where answers required clarification. Interview guides were tailored to each respondent category, and the same core questions were asked across categories so that answers could be compared.
On the supply side, respondents included product managers, application engineers and sales managers at CMP pad manufacturers; managers at suppliers of polyurethane prepolymers, curatives, microspheres and sub-pad materials; and staff at CMP equipment, pad conditioner and slurry companies who observe pad usage at customer sites. Supply-side discussions focused on product portfolios, capacity and utilisation, qualification positions by customer and step, pricing trends, raw-material costs, and plans for new products and regional manufacturing. On the demand side, respondents included CMP process engineers and module owners at foundries, memory manufacturers and integrated device makers; procurement and supply-chain managers responsible for consumables; engineers at silicon and compound wafer manufacturers; and process staff at OSATs and advanced packaging sites. Demand-side discussions focused on CMP step counts, pad change frequency, pad selection criteria, the effect of node migration and packaging adoption on consumption, and expectations for local sourcing.
Additional input came from independent consultants and former employees of pad suppliers and fabs, who provided historical perspective on qualification cycles and competitive dynamics, and from distributors serving smaller fabs, research facilities and packaging houses. The objectives of the primary programme were to confirm or adjust the bottom-up consumption model, to validate the base-year market size and segment splits, to test the forecast assumptions, and to collect qualitative insight on drivers, restraints, opportunities and competitive behaviour. Responses were treated confidentially, and information was used only in aggregated form.
Market Size Estimation
The bottom-up approach estimated pad consumption from the installed and operating base of wafer capacity. For each region and country, wafer starts were estimated by wafer size and by device category, distinguishing leading-edge logic, mature logic and specialty, DRAM, NAND, analog and power, discrete and compound devices. For each category, the number of CMP steps per wafer was estimated from typical process flows and validated with engineers, and the pad life for each step type was estimated in wafers per pad. Dividing wafer passes by pad life gave the number of pads consumed, which was converted into value using average selling prices by pad type, diameter and application tier. Separate estimates were prepared for silicon and compound wafer manufacturing, based on wafer shipments and polishing steps per wafer, and for advanced packaging, based on the volume of TSV, interposer and hybrid-bonded wafers. Consumption was then allocated to end users according to the operator of each site.
The top-down approach started from the total market for semiconductor materials and the wafer fab materials segment, using SEMI data, and applied the share attributable to CMP consumables and then to pads, informed by supplier disclosures and expert interviews. Supplier revenue analysis provided a second top-down check: CMP pad revenues of the leading suppliers were estimated from segment disclosures, brokerage research and interviews, and adjusted for coverage of smaller and regional suppliers to arrive at a total. The resulting totals were compared with the bottom-up estimate for each historical year.
Data triangulation reconciled these approaches. Where the bottom-up and top-down estimates differed, the assumptions behind each were reviewed, for example pad life on a given step, price levels in a particular region or the coverage of non-semiconductor revenue in supplier disclosures. Regional and segment splits were checked against capacity distributions and supplier commentary, and adjusted so that all segmentations summed to the same global total. The base-year estimate for 2025 was then reviewed against the historical pattern of 2022–2024, including the decline in 2023, to confirm that the series was consistent with known changes in fab utilisation and memory output.
Forecasting Methodology
The forecast for 2026–2032 links pad demand to its underlying drivers. Capacity growth was modelled from announced fab projects, their stated construction and ramp schedules, and an assessment of the probability that each project will proceed as planned, informed by funding status, customer commitments and recent schedule changes. Utilisation assumptions reflect expectations for logic and memory demand, including the contribution of data-centre AI accelerators and HBM, and a normal level of cyclicality in memory. Process intensity was modelled through changes in CMP step counts as fabs migrate to gate-all-around transistors, backside power delivery, higher 3D NAND layer counts and new interconnect metals, and through changes in pad life resulting from new pad designs. Packaging demand was modelled from the expected adoption of hybrid bonding and TSV-based integration in HBM, logic stacking and image sensors.
Pricing assumptions distinguish between mature-node pads, where competition from regional suppliers is expected to hold prices broadly flat, and advanced-node and packaging pads, where tighter specifications and customisation support higher prices. Regional forecasts take account of localisation policies, trade measures and the location of new capacity, while segment forecasts reflect shifts in pad type, application and wafer-size mix. Compound annual growth rates for 2026–2032 were calculated from the forecast values for 2026 and 2032. The forecasts were reviewed with industry participants and tested against alternative scenarios for memory demand and fab timing, and the central case presented in this study reflects the most likely outcome given information available at the time of preparation.
Several specific factors were weighted in the forecast because of their particular relevance to CMP pads. The first is the ratio of pad consumption to wafer output at each node, which rises with node migration because gate-all-around, backside power and new interconnect metals add planarization steps. The second is the share of wafer starts in categories with high pad intensity, such as leading-edge logic and HBM, compared with categories with lower intensity, such as mature analog. The third is the rate at which new pad designs extend pad life, which can reduce unit consumption even as step counts rise. The fourth is the substitution of domestic for imported pads in China and, to a lesser degree, in other localising markets, which affects regional pricing more than regional volumes. Each factor was assessed separately by segment and region so that the combined forecast reflects their interaction rather than a single top-level growth assumption, and the resulting segment and regional values were reconciled to the global total for every forecast year.
Base Year and Forecast Period
The base year for the study is 2025, the most recent full year for which supplier results, fab utilisation information and trade data were available when the analysis was prepared. Historical estimates are presented for 2022, 2023 and 2024, a period that includes the post-pandemic peak in 2022, the memory-led downturn in 2023 and the recovery in 2024. The forecast period covers 2026 to 2032, a seven-year horizon that spans the expected ramp of most fabs announced under national semiconductor programmes and the introduction of several new device architectures. Growth rates are presented as compound annual growth rates for 2026–2032.
All market values are expressed in USD billion at current prices. Revenue reported in other currencies, such as Japanese yen, South Korean won, Chinese yuan, New Taiwan dollars and euros, was converted to U.S. dollars at average annual exchange rates for historical years, and forecasts assume exchange rates broadly in line with those prevailing in 2025. Values are presented to three decimal places, and shares and growth rates to one decimal place, with the same rounded figures used throughout the study. Because the CMP pads market is measured in USD billion, values for smaller countries and segments appear as small decimal figures, and the underlying model retains full precision so that totals and growth rates are not affected by rounding.
Base Year
2025
Historical Period
2022 – 2024
Forecast Period
2026 – 2032
Primary Interviews
150+
Historical data (2022–2025) and forecast period (2025–2032)
Our research process spans primary interviews with industry stakeholders combined with comprehensive secondary data analysis, validated through triangulation across multiple independent sources.
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The CMP pads market is consolidated. A small number of suppliers account for most global revenue, and one supplier, Qnity Electronics, which inherited the pad business built over several decades by Rodel, Rohm and Haas and DuPont, holds a particularly strong position in hard pads for front-end and interconnect steps. Entegris, which added the CMP pad business of CMC Materials through its acquisition completed in July 2022, and Fujibo Holdings, the leading producer of soft pads for silicon wafer and device polishing, form the rest of the leading group. Behind them, regional producers in China, South Korea and Taiwan have built positions with domestic chipmakers, and several specialist companies serve particular steps, materials or customers.
Competition in the market is driven primarily by performance and qualification rather than by price. Chipmakers select pads on the basis of removal-rate stability, planarization efficiency, defectivity, uniformity, pad life and consistency from lot to lot, and they qualify pads as part of a complete process recipe that includes slurry, conditioner and tool settings. Once qualified, a pad tends to remain in use for the life of the process node, which gives incumbents durable positions and makes node transitions and new fabs the main points at which market shares change. Suppliers compete for these openings through joint development with chipmakers, early access to new products, application laboratories near customer fabs, and integrated offerings that combine pads with slurries, cleaning chemistries and conditioners.
The competitive environment has become more dynamic since 2022. Corporate changes have reshaped the leading group: Entegris integrated CMC Materials' pads and slurries, DuPont separated its electronics business as Qnity Electronics on 1 November 2025, and SK enpulse sold its pad division to the private equity firm Hahn & Co. under an agreement signed in December 2024. Localisation policies have strengthened regional suppliers, especially Hubei Dinglong in China. New fab construction in the United States, Japan, Europe and India has created a wave of qualification opportunities, and new applications such as hybrid bonding and SiC polishing have opened areas where processes of record are not yet fixed. Leading suppliers have responded with capacity investments close to customers and with new pad platforms aimed at advanced nodes and packaging.
Key Player Positioning
The leaders in the market are Qnity Electronics, Entegris and Fujibo Holdings. Qnity is positioned as the leading supplier because of the breadth and depth of its pad portfolio, which spans hard pads such as IC1000, Ikonic and Emblem, soft pads such as Politex, Optivision and Optivision Max, and the Suba family for silicon polishing, and because its pads are the process of record on a large number of steps at leading foundries, memory makers and IDMs. It has a global manufacturing footprint in the United States and Asia, which it extended in 2026 with the opening of a facility in Newark, Delaware, and the acquisition of a site in the Hsinchu Science Park, and it has long-term relationships with major chipmakers, illustrated by its supply agreement with SK hynix in October 2025. Entegris is a leader because it combines pads with one of the broadest CMP consumables portfolios in the industry, including slurries, pad conditioners, filters, brushes and post-CMP cleans, allowing it to offer co-optimised solutions, and because of its strong position in SiC CMP and its global network of technology centres. Fujibo is a leader in soft pads, especially for silicon wafer final polishing, where its products are widely used by the major wafer manufacturers, and it has been expanding capacity in Japan.
The challengers are Hubei Dinglong, Enpulse and KPX Chemical. Hubei Dinglong has grown rapidly as the leading domestic supplier in China, with a broad range of pads for logic and memory steps, expanding capacity and a growing portfolio of slurries and cleaning chemistries that allow it to offer integrated CMP materials to Chinese fabs; its challenger status reflects its strong domestic position and growth, balanced by limited presence outside China. Enpulse, the former pad business of SK enpulse, has built positions with Korean memory makers over a decade of development and holds technology in prepolymer formulation and pore control, and its new ownership under Hahn & Co. gives it the focus of a stand-alone pad business. KPX Chemical, a Korean polyurethane and polyol producer, draws on its upstream chemical expertise to supply pads mainly to domestic customers.
The niche players are IVT Technologies, FNS Tech, TWI Incorporated and 3M. IV Technologies, known in the market as IVT Technologies, is Taiwan's domestic pad producer, supplying pads for chip manufacturing and advanced packaging, with customers that include TSMC and Micron according to its parent company, and it is expanding capacity; its position is significant in Taiwan but limited elsewhere. FNS Tech is a Korean producer of pads and other semiconductor and display components that serves selected steps at domestic customers. TWI Incorporated is a specialist pad producer focused on particular applications and customers. 3M is a large diversified company with a strong global presence and long experience in abrasives, whose CMP activities include fixed-abrasive pads and diamond pad conditioners; its niche positioning reflects the limited scope of its pad business relative to the leaders rather than its overall scale. Smaller producers in China, the United States and elsewhere, and technology-based entrants such as developers of functional or additively manufactured pads, also compete in specific segments.
Competitor Dashboard
The competitor dashboard rates each company on product portfolio, regional presence, strategic alliances and industry experience in the CMP pads market, using a scale of Low, Medium, High and Very High. The ratings reflect the qualitative positioning of each company and are consistent with its grouping as a leader, challenger or niche player. Table 11.1 presents the dashboard.
The two leaders with the broadest portfolios, Qnity and Entegris, receive the highest ratings across most criteria, reflecting their global manufacturing and application networks, their long-term agreements with major chipmakers and their decades of CMP experience. Fujibo's ratings reflect its leadership in soft pads and its long history in polishing materials, with a narrower portfolio and fewer publicised alliances. Among challengers, Hubei Dinglong's high portfolio rating reflects its range of pads and related CMP materials, while its regional presence is concentrated in China. 3M's very high regional presence reflects the company's global footprint rather than a large pad business, which is why it is grouped as a niche player.
Porter's Five Forces framework is used here to assess the structural attractiveness of the CMP pads market from the perspective of an established supplier. The analysis considers the threat of new entrants, the bargaining power of raw-material suppliers, the bargaining power of buyers, the threat of substitute technologies and the intensity of rivalry among existing competitors. Each force is rated High, Medium or Low according to its expected effect on supplier profitability during the forecast period. The assessment reflects conditions in 2025 and 2026 and takes account of the expected changes over 2026–2032, including the growth of domestic supply in China, the construction of new fabs in several regions and the emergence of new applications in advanced packaging and compound substrates. Because the market is small relative to the semiconductor industry as a whole and closely tied to it, several forces are shaped as much by the behaviour of chipmakers as by the pad suppliers themselves.
Threat of New Entrants (Low)
The threat of new entrants is rated Low. The most important barrier is qualification. A new pad supplier must persuade chipmakers to test its products on production steps, a process that consumes the customer's engineering time and tool capacity and that can take from several months to more than a year on critical steps, during which the entrant earns little or no revenue. Even after a successful qualification, chipmakers usually begin with small volumes on less critical steps and expand only after the entrant has demonstrated consistent quality over many lots. The second barrier is technology. Producing pads with uniform porosity, hardness and thickness across large castings, with defect levels acceptable at advanced nodes, requires accumulated know-how in polyurethane chemistry, curing, machining and contamination control that is largely tacit and protected by trade secrets as well as by patents held by the established suppliers. The third barrier is capital and infrastructure: a credible entrant needs not only a clean manufacturing facility but also an application laboratory with production-class CMP tools, metrology and defect inspection, and field engineers near customer fabs.
The fourth barrier is customer concentration, since a handful of chipmakers account for most pad demand and each has established supplier relationships. Entry has nonetheless occurred in specific circumstances. Chinese suppliers, led by Hubei Dinglong, have entered successfully with the support of domestic fabs that have policy reasons to qualify local materials, and Korean suppliers built positions after 2019 with domestic memory makers. Technology-based start-ups with novel pad architectures, such as functional or additively manufactured pads, may gain footholds on specific steps. These exceptions show that entry is possible where policy or technology creates an opening, but they do not change the overall assessment that the barriers to entry are high and that new entrants pose a limited threat to established suppliers outside localising markets. Even in localising markets, entrants typically gain positions first on mature-node or less critical steps, and the time needed to progress to advanced steps gives established suppliers an opportunity to respond with local investment, pricing adjustments and new products.
The capital needed to build a credible global presence, with plants and laboratories in several regions, is also beyond the reach of most new companies, which limits most entrants to a regional role for the foreseeable future.
Bargaining Power of Suppliers (Medium)
The bargaining power of raw-material suppliers is rated Medium. On one side, the inputs used in CMP pads are concentrated and specialised. Diisocyanates are produced by a small number of large chemical companies, high-purity prepolymers and aromatic diamine curatives come from a narrow group of producers, and expanded microspheres for pore formation are available from very few sources. Pad makers have usually qualified only one or two sources for each critical input, and changing a source requires internal testing and often customer notification or requalification, which gives incumbent input suppliers a degree of leverage. Logistics for moisture-sensitive prepolymers add to this dependence, because regional pad plants often rely on imports of key chemicals that must be shipped and stored under controlled conditions. Input prices are linked to petrochemical and energy markets, so pad makers are exposed to cost movements outside their control, as shown by the increases in raw-material and energy costs that pad makers cited in their 2026 outlooks. On the other side, several factors limit supplier power.
The semiconductor pad market is a very small customer for the large diisocyanate producers, which reduces their interest in exploiting it but also means that their pricing is set by broader market conditions rather than targeted at pad makers. Some leading pad makers produce their own prepolymers or have long-term agreements with input suppliers, which reduces exposure. Raw materials account for a modest share of the value of a finished pad compared with manufacturing know-how, quality control and technical service, so input price changes have a moderate effect on pad margins. And the major input suppliers have strong incentives to maintain relationships with pad makers, which give them a reference position in a high-technology market. On balance, suppliers can influence costs and pose a supply-continuity risk, particularly for smaller pad makers with single sources, but they cannot capture a large share of the value created in the pad market. The balance could shift if chemical regulation were to restrict a key input, such as a particular curative, without a qualified substitute, because the few suppliers of compliant alternatives would then gain leverage, and pad makers are therefore investing in alternative formulations as a precaution.
Bargaining Power of Buyers (Medium)
The bargaining power of buyers is rated Medium. Buyer concentration is high: a small number of foundries, memory makers and IDMs account for most global pad consumption, and the largest of them purchase pads in volumes that make them critical accounts for every supplier. These buyers have sophisticated procurement organisations, benchmark prices across suppliers and regions, seek annual price reductions and increasingly require dual sourcing, all of which strengthen their negotiating position. They also have the technical capability to evaluate alternative pads and, where a credible alternative exists, can use the threat of qualification to extract concessions. However, several factors offset this power. Once a pad is qualified on a step, switching costs are high, as requalification consumes engineering resources and carries yield risk, so buyers are reluctant to change suppliers on critical steps for the sake of modest savings. Pads account for a small share of the cost of a processed wafer, while their influence on yield is large, so buyers place more weight on performance and reliability than on price. On the most advanced steps, only one or two suppliers may be able to meet the specification, which limits buyers' options.
Buyer power therefore varies by segment: it is relatively high on mature-node and high-volume memory steps where several qualified suppliers compete and where local suppliers offer lower prices, and relatively low on leading-edge logic, HBM and hybrid-bonding steps where performance requirements narrow the field. Silicon wafer manufacturers and OSATs, which operate on thinner margins than chipmakers, are more price-sensitive, while the largest foundries are more focused on supply assurance and joint development. Long-term supply agreements, such as the agreement Qnity signed with SK hynix in October 2025, illustrate how the balance of power is managed in practice: the buyer secures volume and continuity, while the supplier secures a multi-year commitment that justifies investment in capacity and development.
Threat of Substitutes (Low)
The threat of substitutes is rated Low. CMP has been the standard technique for global planarization in semiconductor manufacturing since the 1990s, and no alternative technology currently offers comparable planarity, throughput and cost across the range of materials and steps where pads are used. Alternative planarization approaches, such as etch-back processes, spin-on dielectrics, electrochemical mechanical planarization and plasma-based smoothing, are used in specific situations but have not displaced CMP for mainstream steps, and in several cases new architectures have replaced etch-back with CMP rather than the reverse. Within CMP, the main substitution risk is between pad types and designs rather than against the pad itself: fixed-abrasive pads, functional pads that react with polishing fluids, and additively manufactured pads change the type of pad used but remain within the pad market. Abrasive-free and slurry-light processes may change the balance of value between pads and slurries, potentially increasing the pad's share. A further form of substitution is the reduction of pad consumption through longer pad life, which reduces the number of pads used per wafer without removing the need for pads.
For substrate polishing, alternative techniques such as ion-beam finishing or plasma-assisted polishing exist for specialised applications but are not cost-competitive at volume. In advanced packaging, some flows can avoid CMP by using different bonding approaches, such as thermo-compression bonding with micro-bumps, but the move towards finer pitches favours hybrid bonding, which requires more CMP rather than less. The low threat of substitutes is one of the most attractive structural features of the market. It means that the market's growth is tied to the growth of semiconductor manufacturing itself, and that suppliers can invest in pad development with confidence that the underlying process will remain in use throughout the forecast period and beyond.
Intensity of Competitive Rivalry (Medium)
The intensity of rivalry is rated Medium. The market is concentrated, with a leading supplier holding a strong position in hard pads, a small group of other established suppliers sharing much of the remaining value, and regional suppliers serving domestic markets. Concentration tends to moderate rivalry, as do differentiation and switching costs: suppliers compete primarily on performance, quality consistency, technical support and supply assurance, and price competition on qualified steps is limited by lock-in. Growth also moderates rivalry, since a market that expands with wafer output and process complexity allows suppliers to grow without necessarily taking share from one another. However, rivalry is increasing in several areas. In China, domestic suppliers compete aggressively on price and service for positions at local fabs, and brokerage research on Hubei Dinglong has highlighted the rapid expansion of its capacity, which adds supply to the market. At new fabs in the United States, Europe, Japan and India, suppliers compete for initial qualification, knowing that positions won during the ramp may last for decades. In emerging applications such as hybrid bonding and SiC polishing, where processes of record are not yet fixed, suppliers compete through new pad platforms and joint development.
Established suppliers have responded with investments in capacity close to customers, new product launches such as Qnity's Emblem and Optivision Max platforms, and integrated offerings combining pads with slurries and cleaning chemistries, as Entegris does across its CMP portfolio. Ownership changes have also altered the competitive set, with Qnity's separation from DuPont in November 2025 creating a focused semiconductor materials company and the acquisition of SK enpulse's pad business by Hahn & Co. in 2025 placing a major Korean producer under private equity ownership. Overall, rivalry is intensifying at the margins of the market while remaining moderate in its established core. Over the forecast period, the balance between these tendencies will depend on how quickly regional suppliers progress to advanced steps and on whether new applications consolidate around a few pad platforms or remain open to multiple suppliers.
Threat of New Entrants: Low; Long fab qualification cycles, tacit polyurethane process know-how and the need for application laboratories near customers.
Bargaining Power of Suppliers: Medium; Concentrated sources for diisocyanates, curatives and microspheres, offset by the small share of raw materials in pad value.
Bargaining Power of Buyers: Medium; Highly concentrated chipmaker demand, offset by high switching costs and the yield impact of pad performance.
Threat of Substitutes: Low; No alternative matches CMP for global planarization; new architectures and hybrid bonding add CMP steps.
Intensity of Competitive Rivalry: Medium; Concentrated and differentiated market, with rising competition in China, at new fabs and in emerging applications.
Market estimates by geography (2032)
InsightAsia Pacific leads with $1.51B by 2032, while North America is projected to grow fastest at a 7.8% CAGR.
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View Subscription Plans| REGION | 2022 | 2025 | 2032 | CAGR | SHARE |
|---|---|---|---|---|---|
| North America | $130.40M | $171.80M | $275.60M | 7.8% | 13% |
| Europe | $82.10M | $103.00M | $146.00M | 5.9% | 7% |
| Asia Pacific | $848.60M | $1.11B | $1.51B | 5.9% | 73% |
| Latin America | $17.40M | $24.10M | $36.00M | 7.5% | 2% |
| Middle East & Africa | $45.50M | $61.20M | $91.50M | 7.2% | 4% |
| Total | $1.12B | $1.47B | $2.06B | 6.2% | 100% |
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View Subscription PlansTotal Market Size
$2.06B
| APPLICATION | REVENUE ($B) | GROWTH RATE | MARKET PENETRATION |
|---|---|---|---|
| Hard Pads | $1.08B | 5.5% | 52% |
| Soft Pads | $602.10M | 5.6% | 29% |
| Composite / Stacked Pads | $376.20M | 10.0% | 18% |
* Revenue projections based on 2025 estimates. Growth rates represent CAGR 2024–2030. Market penetration indicates current adoption rate within addressable market segments.
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Analytical insights on CMP Pads Market covering market dynamics, competitive landscape, and strategic outlook.
The CMP Pads Market market is projected to reach $2.06B by 2032, growing at 6.2% CAGR. The Hard Pads segment holds the largest share.
Demand for CMP pads is derived demand. Pads are not bought for their own sake but because every wafer that passes through a planarization step wears away a small fraction of a pad, and the pad must be replaced when it can no longer hold the process within specification. The forces that shape the market therefore operate at three levels. At the macro level, semiconductor end-markets, government industrial policy, trade measures and the cost of petrochemical inputs determine how many wafers are produced, where they are produced and what it costs to make pads. At the process level, device architecture determines how many CMP steps each wafer needs and how demanding those steps are. At the supplier level, qualification practices, product innovation and cost-of-ownership competition determine which pads are used, how long they last and what price they command.
These forces are examined in turn, beginning with a scored assessment of the main macro and micro factors over three parts of the forecast period, followed by a discussion of the principal drivers that are expanding pad consumption, the restraints that slow it or limit the value captured by suppliers, the opportunities that could add new demand beyond the established front-end applications, and the trends that are changing how pads are designed, specified and used. The discussion is qualitative and draws on developments reported by chipmakers, pad suppliers, industry associations and regulators during 2025 and 2026, so that the factors can be related to the current state of the industry rather than to earlier cycles.
Market Growth Factor Analysis
The factors that most influence CMP pad demand over 2026–2032 were assessed on a scale of 0 to 10, where a higher score indicates a stronger effect on the market in the direction shown, whether promoting growth, inhibiting it or holding it steady. The scores are analyst assessments based on secondary research and interviews with suppliers and users, and they are intended to show the relative weight and timing of each factor rather than to measure it precisely. Five macro factors, which originate outside the pad industry, and five micro factors, which arise within the CMP process and its supply chain, are assessed for three periods: 2026–2027, 2028–2030 and 2031–2032. Table 4.1 presents the assessment.
Among the macro factors, semiconductor demand from AI and data-centre computing carries the highest score in the near term. Global semiconductor sales reached USD 298.5 billion in the first quarter of 2026 according to the Semiconductor Industry Association, and the leading-edge logic and HBM capacity that serves AI accelerators runs at high utilisation, which translates directly into pad consumption. The score eases slightly in the later periods because some normalisation of AI infrastructure spending is expected after the current build-out, although the installed base will remain large. Government incentive programmes score highest in 2028–2030, when most fabs funded under the U.S. CHIPS and Science Act, the European Chips Act, Japan's subsidy programme, the India Semiconductor Mission and China's national investment funds are expected to be in volume production. Trade tariffs and export controls are rated as inhibiting, with the effect concentrated in 2026–2027 while the U.S. Section 232 process on semiconductors and China's licensing regime for critical minerals remain unsettled. Memory cyclicality is assessed as a persistent inhibiting factor of medium strength across all periods, reflecting the experience of 2023. Petrochemical feedstock and energy prices are assessed as steady: they affect supplier margins and pricing, but pad costs are a small share of wafer cost and fabs rarely change consumption in response to pad prices.
Among the micro factors, the rise in CMP steps per wafer carries the highest scores across the forecast period, because gate-all-around transistors, backside power delivery, higher-layer 3D NAND and new interconnect metals each add planarization steps that persist once adopted. Advanced packaging adoption starts from a lower score and increases steadily, reaching the highest score of all factors in 2031–2032 as hybrid bonding spreads from HBM and selected logic products to a wider range of devices. Qualification time and process-of-record lock-in is rated as inhibiting because it slows the uptake of new pads and of new suppliers, although its effect eases slightly as chipmakers introduce dual-sourcing policies. Domestic pad supply in China is assessed as steady: it changes who supplies pads and at what price more than it changes how many pads are consumed. Longer pad life and cost-of-ownership improvements are rated as inhibiting and rising, because successful new designs reduce the number of pads needed per thousand wafers, partly offsetting the gains from higher step counts while allowing suppliers to charge more per pad.
More Planarization Steps in Advanced Logic and Memory Architectures
The most durable driver of CMP pad demand is the steady increase in the number of planarization steps required to build each advanced wafer. CMP was introduced into volume manufacturing in the early 1990s to flatten inter-layer dielectrics, and every major change in device architecture since then has added steps rather than removed them. The transition to copper damascene interconnects added bulk copper, clearing and barrier steps at every metal level. The adoption of high-k metal gates added replacement-gate CMP steps in the front end. FinFETs increased the precision required for STI and gate planarization. The present generation of changes is continuing this pattern. TSMC started volume production of its N2 process, its first gate-all-around nanosheet node, in the fourth quarter of 2025, and Samsung and Intel are producing their own gate-all-around processes. In a nanosheet transistor the channel is formed from a stack of alternating silicon and silicon-germanium layers, and the flow includes additional dielectric fill and planarization steps around the stacked channels, the inner spacers and the gate, each with tight thickness targets.
Because these steps sit in the front end of line, the pads used for them must deliver both high planarization efficiency and very low defectivity, which pushes demand towards premium hard and composite pads with closely controlled porosity and groove design. Gate-all-around flows also tend to replace some etch-back steps with CMP, because CMP can stop more reliably on thin liner layers when the pad and slurry are tuned together, and process engineers have described the use of selective, low-pressure polishes that remove only a few nanometres of material. Steps of this type place unusual demands on the pad: it must deliver a very low and stable removal rate, avoid local pressure concentrations at the edges of dense arrays, and leave no residue that could interfere with the next deposition. The result is that a single node transition can add several new pad specifications to a fab's consumables list, each requiring separate qualification and each consumed at a rate that reflects the volume of wafers passing through the step.
Backside power delivery adds a further layer of process content. In conventional chips, power and signal lines share the interconnect stack above the transistors. In backside power designs, power is routed through the back of the wafer, which requires the device wafer to be bonded to a carrier, thinned from the back to within a few hundred nanometres of the transistors, and then processed again to build the power network. Intel introduced its PowerVia approach with the 18A process, which entered high-volume production for client processors in late 2025, and TSMC plans to introduce its Super Power Rail with the A16 process. Each of these flows adds CMP steps for wafer thinning, for the planarization of backside dielectrics and for the metal layers of the backside network, and the bonding step itself requires very flat surfaces. For pad suppliers, backside power is significant because it effectively adds a second interconnect stack to every wafer that uses it, and because the thinning and bonding steps demand uniformity across the full wafer that only a narrow range of pad and sub-pad combinations can achieve.
Chipmakers also continue to introduce new interconnect metals, including cobalt, ruthenium and molybdenum, in contacts and the lowest metal levels, and each new metal requires its own CMP step and pad qualification. These metals behave differently from copper under polishing. Ruthenium is hard and chemically resistant, cobalt corrodes easily in the wrong slurry chemistry, and molybdenum requires careful control of oxidation, so the pad must be matched to slurries that are themselves new, and pad suppliers frequently develop the pad and slurry as a pair. Where a chipmaker introduces a metal at only one or two levels, the step may still require a dedicated platen and pad, adding to the variety of pads in use. Over time, the proliferation of metals and dielectrics means that a modern fab uses a portfolio of pad types rather than a small number of general-purpose pads, which increases the value of supplier relationships that span the whole CMP module.
Memory devices show the same pattern. 3D NAND has moved from 32 and 64 layers a decade ago to products with more than 300 word-line layers, such as SK hynix's 321-layer NAND, which entered mass production in 2025. Higher layer counts are generally achieved by stacking two or three decks of layers, and each deck interface, each staircase region and the peripheral circuitry under or beside the array need oxide and polysilicon planarization. Stacking the decks also makes the overall film stack thicker and more stressed, so wafer bow becomes harder to control and global uniformity during CMP becomes more important. In DRAM, scaling to 1b and 1c nanometre-class nodes has increased the aspect ratio of storage capacitors and the number of patterning steps, and the move towards vertical-channel and 3D DRAM structures that memory makers have described in their technology roadmaps would add further planarization. The memory flows that feed HBM also include TSV formation and backside processing for every die in the stack, which increases the CMP content of each HBM wafer compared with a standard DRAM wafer.
Memory makers have also begun to bond separate wafers for the memory array and the peripheral logic in some 3D NAND architectures, an approach known in the industry as CMOS-bonded-array or by company-specific names, which requires both wafers to be planarized to bonding quality before they are joined. This practice moves wafer-bonding CMP, previously associated mainly with image sensors, into high-volume memory production. Because NAND wafers are produced in very large volumes, even one additional bonding-grade polish per wafer represents a significant increase in pad consumption, and the specification for these steps is closer to that of advanced packaging than to conventional memory CMP.
The commercial effect of these changes is that pad consumption grows faster than wafer output. A wafer at an advanced logic node passes through many more CMP steps than a wafer at a mature node, and the pads used on critical steps are changed more frequently because process windows are narrower and defect limits are stricter. Suppliers have responded with pad platforms aimed at advanced nodes, including Qnity's Ikonic and Emblem families and Entegris's portfolio of pads paired with its slurries, and they work with chipmakers through joint development programmes that begin several years before a node enters production. For the market, this driver affects hard pads and composite / stacked pads most strongly, because these types are used on the front-end and interconnect steps that are being added. Among applications, the strongest effect is on oxide, STI and dielectric planarization and on copper, barrier and other metal steps, and among end users it is concentrated at foundries and memory manufacturers that operate leading-edge 300 mm lines. The driver is also self-reinforcing, because each new architecture tends to remain in production for many years after it is introduced, carrying its higher step count into the installed base.
There is also a qualitative dimension to the driver. As the number of steps rises, the cumulative effect of small defects or non-uniformities across many CMP passes becomes a larger contributor to yield loss, so chipmakers place more emphasis on pad consistency from lot to lot and from the first wafer to the last wafer of a pad's life. Suppliers that can document tight control of density, hardness and groove dimensions, and that can provide statistical process data with each shipment, are favoured in these environments. This strengthens the position of established suppliers with mature quality systems while setting a high threshold for newer entrants seeking to supply advanced-node steps.
AI Accelerator and High-Bandwidth Memory Production Raising Fab Utilisation
While step counts determine how many pads each advanced wafer needs, the volume of advanced wafers depends on end demand, and the most important source of incremental demand in 2025 and 2026 has been computing infrastructure for artificial intelligence. Data-centre operators and cloud providers have expanded purchases of GPU and custom accelerator systems, and each accelerator package combines one or more large logic dies made at the most advanced foundry nodes with several stacks of HBM. The effect on semiconductor output has been visible in industry statistics. The Semiconductor Industry Association reported global semiconductor sales of USD 298.5 billion in the first quarter of 2026, an increase of 25% over the fourth quarter of 2025, and SEMI reported in May 2026 that global semiconductor materials revenue reached a record USD 73.2 billion in 2025, with growth attributed to higher process complexity and continued investment in high-performance computing and HBM. For CMP pads, the significance of this demand lies in its composition. AI accelerators are made on the nodes with the highest CMP step counts, and the large die sizes mean that more wafers are needed for each unit of output, so pad consumption per unit of end-market value is high.
The reticle-limited dies used in the largest accelerators also leave less room for yield loss, so chipmakers run CMP on these products with conservative process windows and change pads before the end of their nominal life when there is any sign of drift. Customers for these products pay for wafers rather than for good dies in many foundry contracts, but the foundry itself has every incentive to protect yield on its highest-value wafers, and CMP consumables are a small cost relative to the value of the wafer. As a result, pad choice on AI-related logic steps is driven by performance rather than price, which supports the premium pad platforms that leading suppliers have introduced since 2024.
High-bandwidth memory amplifies this effect on the memory side. HBM is built by stacking eight, twelve or sixteen DRAM dies connected by TSVs on top of a base logic die, and each generation increases the number of dies per stack and the number of stacks per accelerator. Producing HBM consumes more wafer area per bit than conventional DRAM because the dies are larger, yields across the stack must be managed, and TSVs and micro-bumps occupy space. Memory makers have therefore allocated a growing share of their DRAM capacity to HBM, and they have added dedicated capacity for it. Each HBM wafer also passes through additional backside processing: after the front-side circuitry is completed, the wafer is thinned to reveal the TSVs, and the revealed surface is planarized before bumps or bonding pads are formed. The long-term CMP pad supply agreement that Qnity signed with SK hynix on 7 October 2025, which the companies described as supporting SK hynix's next-generation manufacturing and mass production processes, illustrates how memory makers are securing pad supply for these flows.
JEDEC published its HBM4 standard in April 2025, and the transition from HBM3E to HBM4 doubles the interface width and moves the base die to logic processes at foundries, which brings foundry CMP steps into the HBM supply chain as well. Memory makers have responded with new capacity dedicated to HBM and its packaging. SK hynix has expanded HBM production in Cheongju and Icheon and is building a cluster in Yongin, and it announced in 2024 an advanced packaging plant in West Lafayette, Indiana. Samsung and Micron have both expanded HBM capacity, with Micron adding HBM assembly and test capacity in Asia. Each of these investments adds CMP content at the front-end DRAM fab, at the TSV and backside processing stage, and at the packaging stage, so HBM effectively creates pad demand at three points in the supply chain rather than one.
High utilisation is the mechanism that converts this demand into pad sales. CMP pads are consumed only when wafers are processed, so a fab running at full loading uses pads at its maximum rate, while a fab with idle tools does not. During the 2023 downturn, memory makers reduced wafer starts and pad consumption fell accordingly. In 2025 and 2026, by contrast, leading-edge foundry lines and HBM lines operated at or near full capacity. Chinese brokerage research published in May 2026 noted that the foundry and IDM customers of Hubei Dinglong were generally running at full capacity, and Dinglong reported that its CMP pad revenue rose 52.3% in 2025 and 71.2% in the first quarter of 2026 compared with a year earlier. Fujibo Holdings reported that sales in its polishing materials segment, which includes CMP pads for silicon wafer and device polishing, increased 16.8% in the fiscal year ended March 2026, which it attributed to demand for advanced semiconductors related to generative AI. Entegris reported that unit-driven growth in 2025 was supported by CMP consumables as volume increased in the most advanced technologies.
These results are consistent with a market in which demand is constrained less by customers' willingness to buy than by the speed at which advanced capacity can be added. In such conditions, pad suppliers focus on supply assurance, lead times and the ability to support rapid ramps at new fabs, and long-term supply agreements become more common because both sides want to lock in volume and continuity. It also means that consumption at existing advanced fabs is close to its practical maximum, so further growth depends on new capacity coming on line and on higher step counts in new process generations rather than on further increases in loading.
Hybrid Bonding and Wafer-Level Advanced Packaging
Hybrid bonding is the most significant new source of CMP pad demand to emerge since the introduction of copper interconnects. In a hybrid bond, two surfaces containing copper pads embedded in a dielectric, usually silicon oxide or silicon carbonitride, are brought into direct contact without solder or micro-bumps. The dielectric surfaces bond at room temperature through molecular attraction, and a subsequent anneal causes the copper pads to expand and fuse. The method allows interconnect pitches of a few micrometres or less, far finer than micro-bump technology, and it reduces the height of a die stack because no bump layer is needed. However, it imposes specifications on the bonding surfaces that only CMP can deliver. The dielectric must be extremely flat and smooth, typically with roughness below a nanometre, so that the surfaces make intimate contact across the full area, and the copper pads must be recessed below the dielectric by a carefully controlled depth, usually a few nanometres, so that they close the gap during annealing without preventing dielectric contact. Any particle, scratch or local variation in recess can create voids that cause the bond to fail.
Achieving these results requires a dedicated CMP sequence, often with separate copper, barrier and dielectric steps, using pads and slurries designed for very low defectivity and precise control of copper recess across dense and sparse pad layouts. Image sensor makers, led by Sony, have used wafer-to-wafer hybrid bonding in volume since the mid-2010s, so the basic process is proven; what is changing is the spread of the technique to logic and memory products and to die-to-wafer formats. Die-to-wafer bonding in particular raises the CMP burden, because both the receiving wafer and the wafer from which the dies are cut must be planarized to bonding quality, the dies must survive thinning, singulation and handling without contaminating their bonding surfaces, and any variation in die thickness must be accommodated in the stack. These steps also require cleaning and metrology at a level that front-end fabs take for granted but packaging lines are only beginning to install. Pad suppliers that can share front-end know-how on defect control with packaging customers therefore add value beyond the pad itself.
The opportunity is growing on several fronts at once. In high-bandwidth memory, the industry has relied on thermo-compression bonding with micro-bumps up to HBM3E and early HBM4 products, but the increase in stack height to sixteen dies and beyond, combined with the package height limits set by JEDEC, is pushing memory makers towards hybrid bonding for later HBM generations, and all three major memory producers have discussed hybrid bonding in their technology roadmaps and at industry conferences. In logic, TSMC's SoIC platform uses hybrid bonding to stack dies, and AMD has used it in processors with stacked cache since 2022. Wafer-to-wafer bonding is also being adopted for backside power delivery, where the device wafer is bonded to a carrier, and for the 3D NAND architectures that bond separate array and periphery wafers. Each of these applications adds at least one bonding-grade CMP sequence per wafer, and die-to-wafer hybrid bonding adds planarization of both the target wafer and the dies before they are singulated.
Research organisations are also extending the process to thick dielectric layers: at Entegris's CMP Technology Day in Dresden on 8 October 2026, CEA-Leti presented work on die-to-wafer CMP for thick oxide planarization in the range of 3 to 20 micrometres, a regime that requires pads capable of high removal rates while preserving bonding-quality flatness. The same event included a session on high-performance copper CMP for advanced packaging and 3D integration, indicating that pad and slurry suppliers now treat packaging as a distinct application area with its own product roadmaps rather than as an extension of front-end interconnect polishing. Equipment suppliers have taken a similar view, introducing CMP and cleaning systems configured for bonding preparation, and several research institutes in Europe, Asia and the United States operate pilot lines where pad suppliers can test materials on hybrid-bonding flows before customers commit to production.
For pad suppliers, the opportunity lies not only in volume but in specification. Bonding-grade CMP calls for soft and composite pads that minimise micro-scratches and edge effects, for sub-pads that maintain uniformity across warped and thinned wafers, and for consistent performance across the full pad life so that the copper recess remains within its tolerance from the first wafer to the last. These are areas in which established pad suppliers have relevant platforms, such as Qnity's soft-pad families and Entegris's combined pad and slurry offerings for copper and barrier steps, but the packaging context also creates openings for new approaches. Packaging lines often handle reconstituted wafers, bonded wafer stacks and wafers with large topography, which behave differently from standard device wafers on a CMP tool and may need pads with different compliance or groove design. Equipment makers have developed CMP tools for packaging lines, and the pad, slurry and conditioner must be co-optimised with these tools.
Suppliers able to offer an integrated package of pad, slurry, cleaning chemistry and process support are therefore well placed, because packaging engineers, many of whom come from assembly rather than front-end backgrounds, value turnkey solutions that shorten development time and reduce the number of parties involved in solving a problem. The economics of packaging CMP also differ from front-end CMP in ways that favour higher-value pads. Wafers reaching the bonding stage have already accumulated most of their manufacturing cost, and in the case of HBM and stacked logic a failed bond can destroy several known-good dies at once, so the cost of a defect is much higher than at an early front-end step. Packaging engineers are therefore prepared to pay for pads that demonstrably reduce bonding voids or improve recess control, and they evaluate pads on yield outcomes measured after bonding rather than on removal rate alone.
The opportunity affects the market structure in ways that differ from the established front-end business. A significant share of hybrid bonding takes place at foundries and memory makers, which perform advanced packaging in their own facilities, but OSATs and advanced packaging houses are also investing in wafer-level processes that include CMP, and some are expected to offer hybrid bonding services as the technology matures and spreads beyond the largest chipmakers. This broadens the customer base for CMP pads to include companies that have historically bought few or none, and it places pad suppliers in contact with procurement organisations that are accustomed to different qualification practices and cost structures. The most relevant application segment is advanced packaging, which covers TSV reveal, redistribution layers and hybrid bonding, and the most relevant end-user segment is OSATs and advanced packaging houses, while memory manufacturers and foundries benefit through their in-house packaging operations. The 300 mm segment captures nearly all of this demand, because hybrid bonding is performed on 300 mm wafers in practice, and composite and soft pads are the most relevant pad types given the emphasis on defectivity and uniformity over bulk removal rate.
Regionally, the opportunity is concentrated where HBM and advanced logic packaging are performed, principally South Korea, Taiwan, Japan and the United States, with growing activity in China and Southeast Asia as packaging capacity diversifies. Malaysia and Singapore host significant packaging operations of global chipmakers and OSATs, and investments in advanced packaging in Arizona and Indiana are expected to bring hybrid bonding to North America during the forecast period, extending pad demand into locations where front-end CMP has historically been limited.
Polishing of Silicon Carbide and Other Compound Semiconductor Substrates
Compound semiconductor substrates present a distinct opportunity for CMP pad suppliers because their physical and chemical properties make polishing slow, difficult and pad-intensive. Silicon carbide is the most important case. SiC is one of the hardest materials used in electronics and is chemically inert under most conditions, so the removal rates achievable by CMP are far lower than for silicon, and polishing a SiC wafer to the surface quality required for epitaxy can take hours rather than minutes per step. The process typically involves several stages, including grinding or lapping to remove saw damage, a rough polishing step using hard pads with diamond or strongly oxidising slurries, and a final CMP step using softer pads with colloidal silica or specialised slurries, often containing permanganate or other oxidisers that convert the surface to a softer oxide that can be removed mechanically. These aggressive conditions wear pads quickly and can degrade conventional polyurethane, so pad life is short and suppliers have developed pads with different chemistries, porosity and backing to withstand them. The combination of long polishing times and short pad life means that SiC substrate polishing consumes a disproportionate number of pads per wafer relative to silicon.
Pad selection also interacts with throughput economics. Because SiC polishing is slow, substrate producers measure productivity in wafers per tool per day and are prepared to pay for pads that raise removal rate even modestly, since every hour saved on a polishing step frees expensive tool capacity. This creates a market for performance-differentiated pads in which the value of a pad is assessed against tool time and slurry cost rather than against its own price, and in which suppliers can be rewarded for innovations such as pads that tolerate higher pressure or more aggressive chemistries without degradation.
Demand for SiC substrates is driven by power electronics in electric vehicles, charging infrastructure, renewable energy inverters, industrial drives and, increasingly, data-centre power supplies, where SiC and gallium nitride devices improve efficiency at high voltages and switching frequencies. The industry is transitioning from 150 mm to 200 mm SiC wafers, which requires new pads in larger diameters with uniformity suited to the larger area, and several substrate producers have announced 200 mm capacity in the United States, Europe, Japan and China, while Chinese producers have also demonstrated 300 mm SiC substrates in 2025. Supply relationships illustrate the importance of polishing consumables in this chain. Entegris announced on 7 August 2024 a long-term supply agreement with onsemi under which it provides a broad range of co-optimised CMP solutions for SiC applications, including slurries, pads, brushes and post-CMP cleans, and stated that it had become a leader in SiC CMP over the preceding four years. Device makers that grow their own SiC crystals, such as onsemi and Wolfspeed, polish wafers in-house and are direct consumers of pads, while others buy polished substrates from independent producers, which then account for the pad consumption.
The growth of Chinese SiC substrate producers has been especially rapid, and they have expanded capacity significantly since 2022, which has lowered substrate prices globally and increased the volume of wafers being polished. The shift to larger diameters adds to pad demand per wafer, because a 200 mm SiC wafer has nearly twice the area of a 150 mm wafer and the larger area demands tighter control of pad uniformity and conditioning. Price pressure on substrates is in turn prompting producers to seek lower polishing costs, which favours pads that combine longer life with stable removal rates, and it has encouraged domestic Chinese pad suppliers to develop products for SiC as part of their wider push into compound semiconductor consumables.
Beyond SiC, gallium nitride, gallium arsenide, indium phosphide and sapphire substrates each require their own polishing processes. Gallium nitride is used increasingly in power devices and radio-frequency amplifiers, mostly as epitaxial layers on silicon, SiC or sapphire, but native GaN substrates are also polished for laser diodes and high-performance devices. Gallium arsenide and indium phosphide substrates support radio-frequency front ends, optical communications and photonic integrated circuits, whose demand has risen with the build-out of optical interconnects in AI data centres. These materials are softer than SiC but chemically sensitive, and their pads must avoid surface damage and contamination that would affect epitaxial growth. Supply of gallium and germanium is a constraint for some of these substrates: China added both to its export-control list in 2023 and banned shipments to the United States in December 2024, and although the ban was suspended on 9 November 2025 until 27 November 2026, the licensing requirement remains, which has encouraged substrate production and recycling outside China and, with it, new demand for polishing consumables in other regions. Photonics is a further area of interest.
Indium phosphide lasers and modulators and silicon photonics devices used in optical transceivers require polished substrates and, in some integration schemes, bonding of dissimilar materials, which brings hybrid-bonding style CMP requirements to compound semiconductor production. As data-centre operators adopt co-packaged optics to reduce power consumption, the number of photonic devices per system is expected to rise, adding a modest but high-value stream of pad demand.
Long Qualification Cycles and Process-of-Record Lock-in
Once a CMP pad has been qualified on a production step, it becomes part of the process of record, the documented combination of materials, tool settings and metrology limits that a fab has validated for that step and, in the case of foundries, has often committed to its customers. Changing the pad means reopening that validation. The new pad must be tested on blanket and patterned wafers, its removal rate, uniformity, dishing, erosion and defect performance must be compared with the incumbent across the full pad life, and the resulting wafers must pass electrical tests and, for many products, reliability tests that take months to complete. Where a foundry has a contractual obligation to notify customers of material changes, the customers may require their own evaluation, and automotive customers in particular apply formal change-control procedures under quality standards such as IATF 16949 that add further time. Industry participants describe qualification periods ranging from several months for a minor change to well over a year for a new supplier on a critical step at an advanced node.
During that period the challenger supplier must provide samples, engineering support and tool time without revenue, and the chipmaker must commit engineering resources that could otherwise be devoted to yield improvement or new product introduction. For many fabs, the expected savings from a cheaper or marginally better pad do not justify the cost and risk of the change, so incumbency persists for the life of a process node, which can be a decade or more. Because foundries often run the same node for many customers and many product generations, a pad qualified at the start of a node may remain in use long after newer designs become available. The same logic applies to changes made by the incumbent supplier. If a pad maker alters a raw material, moves a production step to another line or modifies its curing schedule, it must normally notify its customers in advance, and the customer may require samples and data before accepting the change. Suppliers therefore manage their own processes conservatively, which slows internal cost reduction and the introduction of improved raw materials.
This lock-in restrains the market in several ways. It slows the adoption of new pad designs that could lower cost of ownership or improve yield, because even a technically superior pad must wait for a convenient point in the product cycle, typically a new node or a new fab, before it is introduced. It limits price competition on established steps, which supports supplier margins but also means that customers seeking to reduce consumables spending have limited room to do so, and it can lead chipmakers to defer decisions to dual-source until supply problems force them to act. It concentrates revenue among a small number of suppliers that held positions when the major nodes in use today were qualified, which raises the barrier for newer entrants and for regional suppliers seeking to serve local fabs. And it makes the market slow to respond to new sources of capacity: a supplier that builds a new plant must still qualify pads produced at that plant with each customer, because a change of manufacturing site is itself treated as a material change, even when the pad formulation is unchanged.
Qnity's new facilities in Delaware and Taiwan and Fujibo's expansions in Ehime and Oita will therefore contribute to supply only after site qualifications are completed with each customer. Lock-in also shapes pricing behaviour over the life of a node. Suppliers often accept modest margins during the qualification phase in order to secure a position and then hold prices relatively stable once the pad is in production, while customers seek annual price reductions through procurement negotiations. The balance between these positions tends to favour the incumbent on critical steps and the customer on less critical steps, where a credible alternative already exists. In practice, this produces a market in which the most profitable pad positions are also the most difficult to contest, and in which new suppliers must accept a period of low returns while they build a record of reliable supply on less critical steps. Several years of consistent performance on such steps are usually needed before a fab will consider a newer supplier for a more demanding application.
The effect is strongest on the most demanding applications. At advanced logic nodes, front-end steps such as STI and gate planarization and the lowest interconnect levels carry the strictest specifications, and fabs are least willing to change pads on these steps. In memory, high-volume steps on established 3D NAND and DRAM products are similarly locked in for the life of each product generation. Silicon wafer manufacturers also qualify polishing pads with their own customers, because final polishing determines the surface quality that device makers specify, so a change of soft pad at a wafer supplier can trigger requalification at downstream fabs. The restraint is weaker in mature-node and specialty fabs, in packaging, and in new fabs that are qualifying their entire materials set, which is why new and regional suppliers have tended to gain their first positions in these settings. Hubei Dinglong's growth in China, for example, has come largely through qualifications at domestic fabs that were building or expanding capacity and had policy reasons to qualify local materials, while the Korean pad business now owned by Hahn & Co. built its positions with domestic memory makers over a long period of joint work.
Packaging and compound-semiconductor applications show a more open pattern, since their processes are newer, specifications are still being defined, and many users are prepared to evaluate several pads before fixing a process of record. This openness creates entry points, but it also means that positions won in these areas may be less durable than those in established front-end steps until the processes mature and become locked in their turn.
There are signs that lock-in is easing at the margin, though not disappearing. Supply disruptions during 2021 and 2022, followed by trade restrictions and geopolitical tension, have led many chipmakers to adopt policies requiring at least two qualified sources for critical materials, and to qualify second sources at the start of a new node rather than after a problem arises. Some suppliers have introduced pad platforms designed to be tuned to a customer's process without a full change of materials, through configurable groove patterns, porosity levels and sub-pad options, which can shorten the evaluation period when a customer moves from one variant to another within the same platform. Digital process-control tools that compare pad performance using in-situ data may also reduce the number of test wafers needed. Even so, the fundamental economics remain: a CMP pad accounts for a small share of the cost of a processed wafer, while a defect excursion caused by a poorly understood material can cost far more, so chipmakers will continue to treat pad changes conservatively, and the market will continue to adjust slowly to new technology and new entrants.
For forecasting purposes, this means that market share changes among suppliers are expected to occur mainly at node transitions and at new fabs, and that the introduction of new pad technologies will be spread over several years rather than concentrated in a short period. It also means that the benefits of new pad designs to customers, such as longer pad life or lower slurry use, will reach the installed base gradually, moderating their effect on overall pad consumption during the forecast period.
Raw-Material Cost Volatility and Tightening Chemical Regulation
CMP pads are made from a small set of specialised chemical inputs, and the cost and availability of those inputs constrain both supplier margins and the speed with which capacity can be added. The polyurethane matrix of most hard pads is formed from isocyanate prepolymers based on toluene diisocyanate or methylene diphenyl diisocyanate, which are produced by a limited number of large chemical companies and whose prices move with benzene, toluene, natural gas and chlorine costs as well as with the balance of global isocyanate capacity. Aromatic diamine curatives, such as those based on methylene bis(chloroaniline) or its alternatives, are produced by even fewer suppliers. Hollow polymeric microspheres used to create porosity, polyols, non-woven polyester or polypropylene substrates for soft pads, pressure-sensitive adhesives, transparent window materials and foam sub-pads complete the bill of materials. Many of these inputs must meet purity and consistency specifications far tighter than those required by the furniture, automotive or construction markets that consume most polyurethane chemicals, so pad makers cannot easily switch between suppliers or grades.
When prices of basic petrochemicals rise, as they did in 2022 and again in 2026 when Fujibo cited the situation in the Middle East as a factor raising raw-material and energy prices in its outlook for the fiscal year ending March 2027, pad makers face higher costs that they can only pass on to customers with a lag, usually at the next contract renegotiation. Contracts with large chipmakers frequently fix prices for a year or more, and some include annual price-reduction targets, so cost increases during the contract period are absorbed by the supplier. Logistics add to the cost picture. Isocyanate prepolymers are moisture-sensitive and some must be transported and stored under controlled temperatures, while finished pads are bulky relative to their value and must be shipped in clean packaging that protects them from contamination and deformation. Freight rates and delivery times on Asia–Europe and trans-Pacific routes have been volatile since 2021, and any disruption to shipping lanes or ports raises both cost and inventory requirements for suppliers serving distant fabs.
Chemical regulation adds a second layer of pressure. In the European Union, diisocyanates are subject to a REACH restriction under Annex XVII, entry 74, which since 24 August 2023 has required that industrial and professional users handling products containing more than 0.1% of monomeric diisocyanates complete certified training before use. This applies to pad manufacturing in Europe and to the handling of prepolymers by distributors, and it raises the compliance burden for smaller operations. The EU-wide restriction proposal on per- and polyfluoroalkyl substances (PFAS) is another factor. The European Chemicals Agency's Committee for Risk Assessment adopted its final opinion on 2 March 2026, its Committee for Socio-Economic Analysis agreed a draft opinion on 10 March 2026, and the consultation on that draft, which ran until 25 May 2026, showed that electronics and semiconductors were the sector most frequently addressed by respondents. The socio-economic committee aims to adopt its final opinion by the end of 2026, after which the European Commission will propose a restriction to member states.
While CMP pads themselves are predominantly non-fluorinated polyurethane, some processing aids, release films, fluorinated surfactants and components used in fab fluid handling fall within the proposed scope, and fabs and their suppliers must document their use and plan for substitutes or derogations. Even where pads fall outside a restriction, customers increasingly ask suppliers for full material declarations covering restricted substances, conflict minerals and substances of very high concern, and the preparation of such declarations for a product made from many specialised inputs requires detailed information from the supplier's own suppliers. This documentation work is a modest cost for large suppliers with established compliance teams but a meaningful burden for smaller producers. Regulatory uncertainty also affects product development. Suppliers developing new pad chemistries must consider whether candidate materials could become subject to restriction during the many years a pad may remain in production, and they tend to avoid ingredients under regulatory review even where those ingredients offer performance advantages. This caution narrows the range of materials available for innovation and adds screening work to development programmes.
In the United States, the Environmental Protection Agency's PFAS reporting rule under the Toxic Substances Control Act requires manufacturers and importers of PFAS-containing articles to report historical use, and its submission period has been deferred into 2026 while the agency reconsidered the scope of the rule. Other jurisdictions are developing their own measures, including the United Kingdom, which published a PFAS plan on 3 February 2026 that indicates an intention to align its chemicals regime more closely with the EU by December 2028. Chinese and Korean regulators have tightened rules on hazardous chemical storage and emissions at industrial parks. For pad manufacturers, these requirements translate into investment in emissions control, worker training, material traceability and documentation, which increases fixed costs and lengthens the time needed to establish new plants. They also affect the location of new capacity, since suppliers prefer to expand where permitting is predictable and where chemical-handling infrastructure already exists, which tends to reinforce existing production clusters in the United States, Japan, South Korea, Taiwan and China rather than encouraging pad production close to new fabs in other regions.
In China, which hosts a growing domestic pad industry, new chemical projects are normally located in designated chemical parks with central treatment of emissions and waste, and the approval of new isocyanate-handling capacity is subject to safety and environmental review at provincial level. These requirements are manageable for established producers such as Hubei Dinglong but extend lead times for new entrants.
Engineered and Configurable Pad Platforms Replacing Generic Designs
For much of the history of CMP, a small number of pad designs served a wide range of steps. A rigid cast polyurethane pad stacked on a compliant non-woven sub-pad became the reference for oxide and many metal steps, and a poromeric soft pad became the reference for barrier and buffing steps and for final polishing of silicon wafers. Fabs adapted their processes to these pads through slurry choice, conditioning and tool settings, and pad suppliers improved consistency rather than changing the basic architecture. That pattern is giving way to platforms that are engineered for specific steps and can be configured for individual customers. Qnity's Ikonic family, launched as a platform for advanced nodes, combines a range of hardness levels and porosities with a surface designed to be easy to condition, and offers distinct series for high defectivity performance, higher removal rate and copper bulk or barrier steps. The Ikonic 9000 series, which received a 2025 Edison Award announced in April 2025, was presented as an expansion aimed at productivity and sustainability in advanced chip manufacturing.
Qnity then introduced the Emblem platform in 2025, with the Emblem 5171X pad as its first product, describing it as offering multidimensional customisation and improvements in throughput, planarization and defect reduction together with lower slurry and conditioner disk consumption and longer pad life. On 10 June 2026 the company launched Optivision Max, a soft-pad family with improved defect control and extended pad life, whose first product, Optivision Max 8300, can be supplied with integrated windows for endpoint detection and tailored to customer requirements. Other suppliers have followed similar paths. Entegris presents its pad roadmap at customer events as a programme to improve planarization efficiency, reduce defectivity and increase process stability, with attention to the control of surface texture, uniform asperity distribution and reduced conditioning requirements, and Fujibo continues to extend its soft-pad range for silicon and device polishing. Smaller suppliers in South Korea, China and the United States have introduced their own step-specific pads, often targeting a single application such as tungsten, oxide or SiC, where a focused design can compete with broader platforms on performance for that step. Such focused products allow smaller companies to build qualification records that can later be extended to adjacent steps.
The common feature of these platforms is that the pad is treated as a design space rather than a fixed product. The parameters that can be adjusted include the hardness and modulus of the polishing layer, the size, distribution and volume fraction of pores, the depth, width, pitch and pattern of grooves, the thickness and compliance of the sub-pad, the position and material of endpoint windows, and the surface texture produced at the factory before the pad reaches the customer. By offering combinations of these parameters within a single qualified platform, suppliers can respond to the needs of a particular step without introducing an entirely new material, which shortens evaluation for the customer and reduces development cost for the supplier. Customers benefit because they can fine-tune pad behaviour to their own slurry, tool and pattern density, and because changes within a platform are often treated as less disruptive than a change of platform or supplier. The trend is supported by improvements in pad manufacturing, including tighter control of casting and curing, automated grooving with finer tolerances, and inspection systems that measure thickness, density and groove dimensions on every pad.
It is also reinforced by the competitive need to differentiate on performance in a market where established pad formulations have been widely studied and, in some cases, are no longer protected by patents. Digitalisation adds another dimension. Some suppliers now provide pad-level traceability data, linking each pad to the production lot, measured properties and inspection results, so that customers can correlate process behaviour with pad characteristics and identify the causes of excursions more quickly. This data supports configurable platforms because it allows both parties to see how specific parameter choices translate into results on the customer's tools, and it builds a record that can shorten later evaluations. Over time, such data could support predictive pad replacement, in which pads are changed on the basis of measured condition rather than a fixed wafer count.
New manufacturing methods extend the trend further. Additive manufacturing allows pad structures to be built layer by layer with controlled geometry, so that asperity height, porosity and local stiffness can be specified directly rather than emerging from a casting and foaming process. Developers of printed pads have argued that this control can reduce the dependence on diamond conditioning, which is itself a source of variability and pad wear, and can produce surfaces whose contact behaviour remains stable over the life of the pad. Functional pads that participate chemically in the polishing process represent another direction. On 11 February 2026, ChEmpower introduced Chakra, described as a functional pad for abrasive-free planarization, which works with a proprietary chemical polishing fluid so that the pad, rather than abrasive particles in the slurry, provides the mechanical action; the company presented it for AI chips, HBM and advanced packaging and cited longer pad life and lower tool wear as benefits. Fixed-abrasive pads, in which abrasive particles are embedded in the pad, have been used in some STI and substrate applications for many years and remain an alternative where slurry-free processing offers advantages.
These approaches remain at an early stage relative to conventional cast pads, but they indicate that the boundary between pad and slurry is becoming less fixed. For customers, the attraction of these technologies lies in the possibility of decoupling performance parameters that are linked in conventional pads, such as stiffness and defectivity, or removal rate and pad life. For suppliers, they represent a route to intellectual property positions in a market where the basic cast polyurethane technology is mature, and several companies have filed patents covering printed pad structures, functional chemistries and novel groove and window designs.
The trend affects the market in several ways. It raises the value of each pad, because engineered and customised pads command higher prices than generic designs, which supports revenue growth even where improvements in pad life reduce the number of pads consumed. It increases the importance of application engineering and joint development, since configuring a pad for a customer's step requires access to the customer's process data and often to tool time at the supplier's own laboratory, and this strengthens suppliers with large laboratory networks near major fab clusters. It favours suppliers that can manufacture many variants economically, which requires flexible production lines and sophisticated quality systems. And it creates an opening for technology-led entrants with novel architectures, provided they can demonstrate consistency at volume. The segments most affected are composite / stacked pads, which are by nature engineered combinations of layers, and hard pads used on advanced-node front-end and interconnect steps, together with soft pads for packaging and final-polish steps where defectivity requirements are the most demanding. The trend is most visible at foundries and memory makers running leading-edge processes, where customers have both the need and the engineering resources to exploit configurable designs.
Mature-node fabs and silicon wafer manufacturers are expected to adopt engineered platforms more selectively, focusing on variants that lower cost of ownership on their highest-volume steps, while packaging lines may adopt them more quickly because their processes are newer and less locked in to legacy pad designs.
Cost-of-Ownership and Sustainability Targets Reshaping Pad Specifications
A second trend concerns the criteria by which fabs judge pads. Historically, the main questions were whether a pad delivered the required removal rate, uniformity and defectivity and what it cost per unit. Increasingly, chipmakers evaluate pads on their total effect on the cost and environmental footprint of the CMP module. A pad that lasts longer reduces the frequency of pad changes, and each change avoided saves tool downtime, break-in wafers, technician time and requalification checks. A pad that holds a stable surface with less aggressive conditioning reduces wear on the diamond conditioner disk, which is itself a consumable with a significant cost. A pad that transports slurry more efficiently, through optimised grooves and pore structures, can deliver the same removal rate with a lower slurry flow, and since slurry typically costs more per wafer than the pad, reductions in slurry consumption often outweigh any difference in pad price. Suppliers now quote these system-level benefits in their product launches: Qnity's description of the Emblem 5171X pad emphasised lower slurry and disk consumption and extended pad life, and its Optivision Max soft pads were launched with an emphasis on extended pad lifetime and process efficiency.
This change in emphasis reflects a shift in who participates in pad decisions. In the past, pad selection was largely the domain of process engineers focused on performance, with procurement negotiating price afterwards. Today, many chipmakers evaluate consumables through cross-functional teams that include process engineering, procurement, equipment maintenance and environmental, health and safety staff, and they compare suppliers on modelled cost per wafer pass and on environmental indicators as well as on process results. Suppliers have adapted by preparing cost-of-ownership models and by running extended evaluations that measure pad life, slurry consumption and conditioner wear over full pad lifetimes. These evaluations are lengthy, but they produce data that can be reused across a customer's fabs and that help justify premium pricing where savings are demonstrated.
Sustainability commitments by chipmakers give this trend additional weight. Leading foundries, memory makers and IDMs have set targets for reductions in greenhouse gas emissions, water consumption and waste, many of which extend to their supply chains through procurement criteria and supplier reporting requirements. CMP is a notable contributor to fab water use and chemical waste, because slurries are dispensed continuously during polishing, wafers are rinsed and cleaned after each step, and spent pads and slurry residues must be disposed of. Pads therefore feature in sustainability programmes in two ways. First, longer-life pads and lower slurry flow reduce the volume of consumables manufactured, transported and disposed of per wafer. Second, the pad itself is a waste stream: used pads are contaminated with slurry residues and metal particles and are commonly treated as industrial waste, sometimes as hazardous waste depending on the materials polished and local regulations. Industry bodies have reinforced this focus; SEMI launched the Semiconductor Climate Consortium in November 2022 to coordinate emissions reductions across the value chain, and customers increasingly ask suppliers for product carbon footprints and data on recyclability.
Some chipmakers have also begun to include consumables in their supplier sustainability scorecards and to set expectations for renewable electricity use and emissions reductions at supplier plants. Chipmakers in Taiwan, South Korea and Japan have been among the most active in extending such requirements to materials suppliers, reflecting both corporate targets and the expectations of their own global customers in consumer electronics and computing. For pad manufacturers, whose production involves energy-intensive curing ovens, solvent handling for soft pads and controlled-environment finishing, these expectations translate into investment in energy efficiency, solvent recovery and renewable power purchasing, and into the preparation of life-cycle assessments for major pad families so that customers can account for them in their own reporting.
Pad circularity is an emerging response. At its CMP Technology Day in Dresden on 8 October 2026, Entegris presented its Renaissance initiative, which it described as converting CMP pads from a hazardous, high-cost waste stream into a source of value, alongside work on materials lifecycle engineering and circularity strategies across its CMP portfolio. Approaches being explored across the industry include cleaning and reconditioning used pads for less critical steps, recovering polyurethane through chemical recycling routes such as glycolysis, and using recovered material in non-semiconductor applications. Pad manufacturers are also reducing waste in their own processes, for example by improving the yield of usable sheets from cast cakes and by reusing offcuts, and some are moving towards formulations with lower volatile organic compound emissions in manufacturing and towards packaging that reduces plastic use. Suppliers are also examining adhesives and sub-pad materials, since the separation of the polishing layer from its backing and adhesive is one of the practical obstacles to recycling, and designs that allow layers to be separated more easily after use would make recovery of the polyurethane more feasible. Regulatory developments may accelerate this work.
Waste classification rules for used pads vary by jurisdiction and by the materials polished, and stricter treatment of industrial waste in East Asia and Europe raises disposal costs for fabs. If disposal costs continue to rise, the economic case for take-back and recycling schemes operated by pad suppliers or third parties will strengthen, and pad designs that make recovery easier will gain an advantage in procurement. Several fabs have also started to measure consumable waste per wafer as a formal metric, which gives pad life and recyclability a direct place in operational reporting rather than leaving them as qualitative considerations.
The value chain of the CMP pads market runs from a narrow base of specialty chemical inputs, through a small number of pad manufacturers with highly controlled production processes, to a concentrated group of semiconductor manufacturers that consume pads in their CMP modules. Value is added at each stage, but the largest share of value is created in pad design and manufacturing, where formulation know-how, process control and qualification positions with chipmakers allow suppliers to earn margins far above those available to the chemical producers that supply their inputs. The chain is also characterised by long relationships: chemical suppliers are qualified by pad makers, pad makers are qualified by chipmakers, and each qualification creates dependencies that persist for years. Understanding these dependencies is central to understanding how the market responds to changes in demand, technology and policy.
The first stage of the chain is the supply of raw materials and components. The polishing layer of a hard pad is a polyurethane formed by reacting an isocyanate-terminated prepolymer with a curative. The prepolymers are made from aromatic diisocyanates, principally toluene diisocyanate (TDI) and methylene diphenyl diisocyanate (MDI), reacted with polyether or polyester polyols. Global diisocyanate production is concentrated among a few large chemical companies, including Covestro, BASF, Wanhua Chemical, Dow and Huntsman, which sell mainly to the foam, coatings, elastomer and adhesive industries; semiconductor pads represent a very small share of their output. Prepolymers suitable for CMP pads are produced either by the pad makers themselves or by specialised prepolymer producers that can meet the tight specifications on free isocyanate content, molecular weight distribution and impurity levels. Curatives are typically aromatic diamines, such as methylene bis(chloroaniline) or substituted toluenediamines supplied under brands such as Albemarle's Ethacure range, or polyols for softer formulations. Porosity is commonly created with expanded hollow thermoplastic microspheres, such as those sold by Nouryon under the Expancel name, or by gas blowing or other foaming techniques. Soft pads require polyurethane resins dissolved in solvents such as dimethylformamide, together with non-woven or film substrates made from polyester or other fibres. Further inputs include foam or felt sub-pads, pressure-sensitive adhesives and release liners, transparent polymer windows for optical endpoint detection, and cleanroom packaging materials.
Value added at the raw-material stage lies mainly in purity, consistency and documentation. A pad maker needs each lot of prepolymer, curative and microspheres to behave identically, because small variations in reactivity, particle size or moisture content can change the hardness, porosity and defect performance of the finished pad. Suppliers of these inputs therefore provide certificates of analysis, notify pad makers of changes in their own processes and raw materials, and in some cases reserve dedicated production lines or lots for semiconductor customers. The dependency runs both ways. Pad makers depend on a few qualified sources for key inputs and cannot switch quickly without requalifying their own products with chipmakers. Input suppliers, for their part, gain only modest revenue from the semiconductor segment but must maintain special handling for it. The concentration of diisocyanate production also links pad costs to wider petrochemical markets: when energy and feedstock prices rise, pad makers face higher input costs that they pass on only gradually, and when supply is disrupted by plant outages or logistics problems, pad makers must draw on inventories or alternative qualified sources.
The second stage is pad manufacturing, which is where the market's core technology resides. For hard pads, the prepolymer and curative are metered, mixed with microspheres or other pore formers and cast into moulds, where the mixture reacts and cures under controlled temperature profiles. The resulting cakes or sheets are post-cured, skived or sliced into sheets of uniform thickness, and machined to create groove patterns using computer-controlled cutting. Where a stacked construction is required, the polishing layer is laminated to a sub-pad with adhesive, and windows for endpoint detection are inserted and sealed. Pads are then cut to the diameter required for the customer's tool, inspected for thickness, density, hardness, groove dimensions and surface defects, cleaned and packaged in controlled conditions. Soft pads follow a different route in which polyurethane solution is coated onto a substrate and coagulated in a water bath to form a porous nap, then washed, dried, buffed to open the surface and laminated. Each of these steps involves know-how that is not fully captured in patents: the control of exotherm during curing, the uniformity of pore distribution across a large casting, the reduction of internal stress that could cause pads to warp, and the cleanliness needed to avoid particles that would scratch wafers.
Value added at the manufacturing stage is high because the pad's performance is determined here, and because qualification positions, once gained, protect the manufacturer's revenue. Pad makers invest heavily in application laboratories equipped with production CMP tools, where they polish test wafers under customer conditions, analyse defects and develop new designs. They also invest in statistical process control and traceability systems that allow every pad to be linked to its production data. The key participants at this stage include Qnity Electronics, which inherited DuPont's long-established pad business and its brands such as IC1000, Suba, Politex, Ikonic, Optivision and Emblem, with manufacturing in the United States and Asia; Entegris, which acquired the pad business of CMC Materials, including technology from NexPlanar; Fujibo Holdings, a Japanese producer with a strong position in soft pads for silicon wafer polishing and device CMP, manufacturing through Fujibo Ehime and other sites in Japan; Hubei Dinglong, the leading Chinese producer through its subsidiary Hubei Dinghui Microelectronics; and Korean producers including Enpulse, formerly the CMP pad division of SK enpulse, KPX Chemical and FNS Tech. Other participants include IVT Technologies, TWI Incorporated and 3M, as well as a number of smaller producers in China, Taiwan and the United States. Several pad makers also produce slurries, conditioners or cleaning chemistries, which allows them to optimise the combination and to offer integrated solutions.
The third stage is distribution and technical service. Large chipmakers buy pads directly from manufacturers under frame agreements that specify prices, volumes, quality requirements and change-notification obligations, often for one or more years. Pads are shipped to regional warehouses close to fab clusters, from which they are delivered on a just-in-time basis, and some suppliers operate consignment or vendor-managed inventory arrangements in which they hold stock at or near the customer's site and invoice on consumption. Because pads are bulky and must be protected from contamination and deformation, logistics represent a meaningful cost, and suppliers increasingly manufacture or finish pads close to major customers to reduce lead times and risk. Smaller fabs, research institutes, university cleanrooms, compound semiconductor producers and packaging houses are often served through specialised distributors that provide local stock, customs handling and first-line technical support. The value added at this stage comes from supply assurance, responsiveness and support: application engineers based at or near customer sites help to install new pads, troubleshoot excursions, run evaluations of new products and transfer processes between fabs. For many customers, the quality of this support is a decisive factor in supplier selection, and it is one reason why local presence carries so much weight in the localising markets of China, India, the United States and Europe.
The final stage is consumption by end users, whose requirements shape every earlier stage. Foundries such as TSMC, Samsung Foundry, GlobalFoundries, UMC and SMIC operate the largest number of CMP steps per wafer in their advanced logic processes and set the most demanding specifications. Memory manufacturers such as Samsung, SK hynix, Micron, Kioxia, YMTC and CXMT consume very large volumes of pads on oxide, polysilicon and tungsten steps in 3D NAND and DRAM, and are increasing their use of pads for HBM-related steps. Integrated device makers such as Intel, Infineon, Texas Instruments, STMicroelectronics, NXP and onsemi use pads across logic, analog, power and sensor processes, often on both 200 mm and 300 mm lines. Silicon wafer manufacturers, including Shin-Etsu Handotai, SUMCO, GlobalWafers, Siltronic and SK siltron, use large volumes of soft and hard pads for double-side and final polishing of prime wafers, while SiC and other compound substrate producers use pads under particularly demanding conditions. OSATs such as ASE, Amkor and JCET, together with the packaging operations of foundries and memory makers, are growing consumers as wafer-level packaging and hybrid bonding spread. CMP equipment makers, principally Applied Materials and Ebara, and pad conditioner suppliers are important influencers at this stage, because pads must be co-optimised with their tools and conditioners, and they often participate in joint evaluations.
The geography of the chain does not match the geography of consumption, and this mismatch is an important feature of the market. Hard-pad manufacturing has historically been concentrated in the United States, with additional plants in Taiwan, South Korea, Japan and China serving local customers. Soft-pad manufacturing is concentrated in Japan, where several producers developed the coagulated polyurethane technology originally for synthetic leather and later adapted it to semiconductor polishing. Chinese production has grown rapidly since 2020 but serves mainly domestic fabs. Consumption, by contrast, is spread across Taiwan, South Korea, China, Japan, the United States, Southeast Asia, Europe and Israel, and it is shifting as new fabs open. Pads therefore cross borders in large volumes, and their trade is affected by tariffs, export controls, customs procedures and freight conditions. The shift towards local-for-local production, in which suppliers manufacture or at least finish pads in the region where they are consumed, is reducing this mismatch over time, but it requires suppliers to replicate their manufacturing know-how at new sites and to requalify the resulting products with customers.
The distribution of value along the chain has also changed as the role of the pad has evolved. When pads were relatively standard products, much of the value in the CMP module accrued to slurry suppliers, whose formulations were more closely tailored to individual steps. As pads have become engineered and configurable, and as customers have recognised their influence on slurry consumption, defectivity and tool uptime, a larger share of value has shifted to pad makers that can demonstrate system-level benefits. This shift is reflected in the growth of integrated offerings, in which a single supplier provides pad, slurry, conditioner and cleaning chemistry, and in joint development agreements in which a pad maker and a chipmaker co-design pads for a specific node. It has also increased the importance of data exchange between stages, since the pad maker's ability to add value depends on access to the customer's process results.
The value chain reveals several dependencies that shape market behaviour. Chipmakers depend on a small number of qualified pad suppliers for each step, which gives those suppliers pricing stability but also exposes chipmakers to supply risk, prompting dual-sourcing and localisation. Pad makers depend on a few chemical inputs from concentrated sources, which exposes them to cost and supply disruptions that they cannot easily pass on. All participants depend on the interaction between pad, slurry, conditioner and tool, so changes at any point require coordinated qualification. These dependencies explain why the market favours integrated suppliers with broad portfolios and global footprints, why regional suppliers gain ground most easily in new fabs and mature processes, and why the chain responds to demand changes with a lag, since capacity additions at pad makers must themselves be qualified before they can serve customers.
CMP pads are not regulated as a product category in their own right, but the market is shaped by four groups of rules: industrial policy that determines where fabs are built, trade and export-control measures that govern cross-border flows of semiconductors, equipment and materials, chemical regulation that applies to the substances used to make pads and to fab operations, and quality and safety standards that govern how pads are made and used. The relevant measures differ by region, and their current status in 2026 is summarised by region.
North America
In the United States, the CHIPS and Science Act, signed in August 2022, created manufacturing incentives administered by the Department of Commerce and an advanced manufacturing investment tax credit for semiconductor fabs and equipment. The tax credit rate was raised from 25% to 35% for qualifying projects under legislation enacted in July 2025, increasing the incentive for new fabs that will consume pads. Trade policy has become more active. Following an investigation under Section 232 of the Trade Expansion Act, the President issued a proclamation on 14 January 2026 imposing a 25% tariff on a narrow set of advanced computing chips from 15 January 2026, while directing negotiations with trading partners and indicating that broader tariffs on semiconductors, semiconductor manufacturing equipment and derivative products, paired with an offset programme for companies investing in U.S. manufacturing, could follow. The United States has reached framework agreements with Taiwan, South Korea and Japan that may reduce their exposure to future semiconductor tariffs in exchange for investment commitments. Export controls administered by the Bureau of Industry and Security, introduced in October 2022 and expanded in October 2023 and December 2024, restrict exports of advanced semiconductor equipment, certain items and technology to China and other destinations, which affects the pace and nature of capacity additions in China and, indirectly, the mix of pad demand there.
Chemical regulation in the United States is administered mainly by the Environmental Protection Agency under the Toxic Substances Control Act. The PFAS reporting rule under section 8(a)(7) of that Act requires manufacturers and importers of PFAS and PFAS-containing articles to report historical use; its submission period has been deferred into 2026 while the agency reconsidered its scope. The Occupational Safety and Health Administration maintains a National Emphasis Program on occupational exposure to isocyanates, launched in 2013, which applies to facilities that handle the diisocyanate prepolymers used in pad production. In Canada, the Canadian Environmental Protection Act and its chemicals management plan, which includes an assessment of PFAS as a class, apply to imports and manufacture, while Mexico's participation in the United States-Mexico-Canada Agreement and its Plan Mexico industrial strategy, which includes the Kutsari semiconductor design initiative announced on 6 February 2025, influence investment in the region. The six-year joint review of the USMCA, due in 2026, adds uncertainty for cross-border supply chains in electronics.
Europe
The European Chips Act, Regulation (EU) 2023/1781, entered into force on 21 September 2023 and established a framework for state aid to first-of-a-kind facilities, a chips pilot-line programme and a crisis-monitoring mechanism. Projects supported under it include Infineon's Smart Power Fab in Dresden, which received final German funding approval in 2025 and opened in July 2026, and ESMC in the same city. On 3 June 2026 the European Commission proposed a Chips Act 2.0, a new regulation intended to replace the 2023 act, which places greater emphasis on advanced manufacturing, demand-side measures, faster permitting and supply-chain resilience; the proposal is in the ordinary legislative procedure, and the Council held a policy debate on it on 24 September 2026.
Chemical regulation in Europe is the most extensive of any region. Under REACH, the restriction on diisocyanates in Annex XVII, entry 74, has required since 24 August 2023 that industrial and professional users of products containing more than 0.1% of monomeric diisocyanates complete certified training, which applies to pad manufacturing and prepolymer handling in the EU. The proposed universal restriction on PFAS, submitted in January 2023 by authorities from Denmark, Germany, the Netherlands, Norway and Sweden, is in the final stage of scientific evaluation: the Committee for Risk Assessment adopted its opinion on 2 March 2026, the Committee for Socio-Economic Analysis agreed a draft opinion on 10 March 2026 that supports a broad restriction with targeted derogations, and the consultation on that draft closed on 25 May 2026. The socio-economic committee aims to adopt its final opinion by the end of 2026, after which the Commission will prepare a proposal for a vote by member states. The revised Industrial Emissions Directive, adopted in 2024, tightens permitting and emissions requirements for industrial installations, including chemical plants. In the United Kingdom, UK REACH applies, and the government's PFAS plan published on 3 February 2026 indicates an intention to align more closely with the EU by December 2028.
Asia Pacific
China regulates exports of strategic materials under its Export Control Law of 2020 and its dual-use items list. Gallium and germanium were placed under export licensing from August 2023, and in December 2024 China banned their export to the United States; that ban was suspended on 9 November 2025 until 27 November 2026, although licensing requirements remain. These controls affect compound semiconductor substrate production outside China and therefore pad demand in that segment. Domestically, China supports semiconductor manufacturing and materials through the National Integrated Circuit Industry Investment Fund, whose third phase was launched in May 2024 with registered capital of RMB 344 billion, and through local government programmes. New chemical substances are subject to registration with the Ministry of Ecology and Environment under rules effective since January 2021, and hazardous chemical handling is regulated at national and provincial level.
Japan supports semiconductor investment through subsidies for TSMC's JASM fabs in Kumamoto and for Rapidus in Hokkaido, and it regulates chemicals under the Chemical Substances Control Law and the Industrial Safety and Health Act. Since July 2023, Japan has required export licences for 23 categories of advanced semiconductor manufacturing equipment. South Korea supports chip investment through enhanced tax credits for national strategic technologies, expanded in 2023, and regulates chemicals under the Act on the Registration and Evaluation of Chemicals and the Chemicals Control Act, which were introduced after industrial accidents and impose strict requirements on handling facilities. Taiwan regulates chemicals under its Toxic and Concerned Chemical Substances Control Act and offers investment tax credits for advanced technology under its Statute for Industrial Innovation. India's semiconductor programme, the India Semiconductor Mission, provides fiscal support for fabs and packaging units, and by May 2026 twelve manufacturing projects had been approved. Across Asia Pacific, the practical effect of these regimes on pad suppliers is twofold.
Plants in China, Japan, South Korea and Taiwan must comply with demanding national rules on the storage and use of isocyanates, solvents and other hazardous chemicals, which require investment in containment, monitoring and permitting and which lengthen the time needed to add capacity. At the same time, export controls and investment incentives influence where chipmakers build new lines, so that pad suppliers must follow capacity to locations such as Kyushu, Hokkaido, Gyeonggi province, central and southern Taiwan and Gujarat, each with its own permitting authorities and local requirements for foreign-invested chemical operations.
Other Regions and Industry Standards
In Latin America, Brazil enacted Law No. 14,968 in September 2024, establishing the Brazil Semiconductor Programme and extending incentives for the semiconductor and information technology sectors, and the government has worked to revive the state-owned chipmaker CEITEC. In the Middle East, Saudi Arabia launched its National Semiconductor Hub in June 2024 with a fund of more than SAR 1 billion focused on chip design, while Israel, which hosts established fabs, regulates chemicals through its Ministry of Environmental Protection. Across all regions, industry standards are as important as government regulation for pad suppliers. Pad makers are generally required by customers to hold ISO 9001 quality management and ISO 14001 environmental management certification, and those serving automotive device makers are expected to support IATF 16949 change-control requirements. SEMI standards govern aspects of equipment safety, materials handling and cleanroom practices, and customers' own specifications for packaging cleanliness, traceability and change notification function as de facto regulation of pad quality. Automotive and industrial customers also increasingly expect suppliers to follow functional-safety and supply-continuity practices, including documented business continuity plans and multiple production sites for critical materials, and these expectations have influenced recent decisions by pad makers to designate secondary plants as backup capacity.
Data-protection and cybersecurity rules are a newer consideration, since pad makers increasingly exchange process data and traceability records with chipmakers through digital systems that must meet customers' security requirements. Taken together, these rules raise the cost of compliance, favour suppliers with established regulatory and quality systems, and shape the location of new capacity, while policy incentives in all major regions support the growth of the wafer capacity that ultimately drives pad demand.
Since 2022, the leading pad suppliers have pursued acquisitions, divestitures, capacity expansions, long-term supply agreements and product launches to strengthen their positions, with activity intensifying during 2025 and 2026 as AI-related demand and new fab construction increased the need for local supply and advanced pads. Table 11.2 lists the main developments in date order.
06 Jul 2022: Entegris; Acquisition; Completed the acquisition of CMC Materials, adding CMP pads and slurries to its CMP consumables portfolio.
07 Aug 2024: Entegris; Partnership; Entered a long-term supply agreement with onsemi to provide co-optimised CMP solutions, including pads, for silicon carbide applications.
24 Dec 2024: Enpulse (SK enpulse); Divestiture; SK enpulse agreed to sell its CMP pad division to private equity firm Hahn & Co. for KRW 341.0 billion; the business now operates as Enpulse.
12 Jun 2025: Hubei Dinglong; Acquisition; Board approved the purchase of a further 8% of pad subsidiary Hubei Dinghui Microelectronics for RMB 240 million, raising its holding to 99.35%.
18 Jul 2025: Entegris; Expansion; Opened its Korea Technology Center at the Hanyang University ERICA campus in Ansan to support customers in South Korea.
21 Aug 2025: Entegris; Expansion; Announced USD 700 million of U.S. research and development spending, including a technology centre in Aurora, Illinois, covering CMP pads.
07 Oct 2025: Qnity Electronics; Partnership; Signed a long-term CMP pad supply agreement with SK hynix for next-generation manufacturing and mass production processes.
01 Nov 2025: Qnity Electronics; Spin-off; Completed its separation from DuPont as an independent company listed on the New York Stock Exchange.
28 Nov 2025: Fujibo Holdings; Expansion; Announced a JPY 8.7 billion investment in a new building and production lines for polishing materials at Fujibo Ehime, with operations planned for the second half of fiscal 2028.
06 Mar 2026: Qnity Electronics; Expansion; Announced a USD 61.5 million investment in a research and manufacturing facility in the Hsinchu Science Park, Taiwan, expected to begin operations in early 2027.
11 Mar 2026: Qnity Electronics; Expansion; Opened a 385,000-square-foot facility in Newark, Delaware, to scale production of CMP pads for AI and high-performance computing chips.
10 Jun 2026: Qnity Electronics; Product Launch; Launched the Optivision Max soft CMP pad family, with Optivision Max 8300 available for sampling and orders in all regions.
The PESTEL framework examines the political, economic, social, technological, environmental and legal conditions in which the CMP pads market operates. Each factor is considered for its specific effect on pad demand, pad supply and the competitive position of suppliers, rather than for its general effect on the semiconductor industry.
Political
Political factors influence the CMP pads market mainly through the geography of semiconductor manufacturing. Governments in the United States, the European Union, Japan, South Korea, Taiwan, China and India treat chipmaking as a strategic capability and fund new fabs through grants, tax credits and state investment funds, which determines where future pad demand will arise. Rivalry between the United States and China has produced successive rounds of export controls on advanced chips and equipment, Chinese controls on critical minerals such as gallium and germanium, and tariff measures, including the U.S. Section 232 semiconductor proclamation of January 2026. For pad suppliers, these measures create both risk and opportunity: they can restrict sales or raise costs for cross-border shipments, but they also encourage chipmakers to diversify suppliers and to qualify local or allied sources, which benefits suppliers with plants in the relevant regions. Political stability around Taiwan, which hosts the largest concentration of advanced foundry capacity and therefore of premium pad consumption, remains a factor that chipmakers and suppliers consider in their contingency and inventory planning. Many chipmakers now hold larger safety stocks of critical consumables than before 2020 and ask suppliers to maintain buffer inventories in more than one region.
Industrial policy also shapes supplier ownership: governments review foreign acquisitions of materials companies more closely, and transactions involving semiconductor materials businesses, including the sale of SK enpulse's pad division to a domestic private equity firm in 2025, take place against a background of attention to the nationality of strategic suppliers.
Economic
Economic conditions affect the market through semiconductor demand, fab utilisation and input costs. Pad consumption follows wafer starts, so it rises with strong end demand and falls when chipmakers cut output, as memory makers did in 2023. In 2025 and 2026, demand from AI data centres supported high utilisation at leading-edge logic and HBM fabs, while demand for chips used in consumer electronics, industrial equipment and some automotive applications was more uneven, which created a two-speed pattern in pad consumption between advanced and mature lines. Exchange rates matter because pad production is concentrated in the United States, Japan, South Korea and China while consumption is spread more widely; the weakness of the Japanese yen in recent years has supported the price competitiveness of Japanese soft-pad producers in export markets. Input costs are linked to petrochemical and energy prices, which rose in 2026 according to supplier outlooks. Interest rates and capital costs influence the pace of fab construction, particularly for projects that are not fully funded by governments or large chipmakers. On the supply side, pad makers' own investment decisions depend on expected returns, and the strong results reported by several suppliers for 2025, including growth in pad revenue at Hubei Dinglong and in polishing-material sales at Fujibo, have supported capacity expansion announcements. Price competition from domestic suppliers in China puts pressure on average prices for mature-node pads, while premium pads for advanced steps hold their value.
Social
Social factors include the availability of skilled labour, the expectations of employees and communities around chemical and semiconductor plants, and the demand patterns of consumers. The semiconductor industry faces shortages of process engineers, technicians and materials scientists in several regions, and CMP expertise is particularly specialised; new fabs in the United States, Europe and India must recruit and train CMP engineers, and pad suppliers must staff application laboratories and field service teams near these fabs. Training requirements for workers handling diisocyanates in Europe illustrate how worker safety expectations translate into operating obligations. Communities near fabs and chemical plants increasingly scrutinise water use, emissions and waste, which affects permitting and the social licence to operate for both chipmakers and pad makers. At the consumer level, the adoption of AI services, connected devices and electric vehicles drives the semiconductor demand that ultimately determines pad consumption, while public attention to the environmental footprint of electronics supports chipmakers' efforts to reduce the resource intensity of manufacturing, including CMP.
Demographic trends matter as well: ageing workforces in Japan and South Korea, where much pad production and consumption is located, increase the importance of automation in pad manufacturing and inspection, and suppliers are investing in automated casting, grooving and optical inspection to maintain output with fewer operators. Universities and training programmes linked to new fab clusters, such as those in Arizona, Saxony and Gujarat, are expected to ease skill shortages over time, but the specialised nature of CMP means that supplier field engineers will remain a scarce resource in new regions during the forecast period.
Technological
Technology is the factor that most directly shapes pad demand and specifications. Gate-all-around transistors, backside power delivery, new interconnect metals and high-layer-count 3D NAND add CMP steps and tighten defect requirements, while hybrid bonding brings bonding-grade CMP into advanced packaging. The transition of SiC substrates from 150 mm to 200 mm and the use of compound semiconductors in power, radio-frequency and photonic devices create demand for pads suited to hard or chemically sensitive materials. Pad technology itself is advancing through configurable platforms with tailored porosity, hardness and groove patterns, integrated endpoint windows, additive manufacturing of pad structures and functional pads for abrasive-free processes, as illustrated by product launches such as Qnity's Optivision Max family in June 2026 and ChEmpower's Chakra pad in February 2026. Process control is becoming more data-driven, with in-situ monitoring of removal and pad condition and the use of machine learning to adjust recipes, which increases the value of pads with consistent and well-characterised properties. CMP tool makers are also introducing platforms with more polishing heads and platens, integrated cleaning and metrology, and configurations tailored to packaging and SiC, each of which affects how pads are used and how quickly they wear. Technology therefore works in two directions for the market: it increases the number and difficulty of CMP steps, raising demand and value, while improving pad life and process efficiency, moderating the number of pads consumed per wafer.
Environmental
Environmental considerations are growing in importance. CMP consumes significant quantities of ultrapure water and slurry and generates waste streams that include spent slurry, rinse water and used pads, so chipmakers' targets for water, waste and emissions reduction extend to CMP consumables. Pads that last longer, require less conditioning and allow lower slurry flow reduce the resource footprint of each wafer, and suppliers increasingly present these benefits in product launches. Used pads are a waste stream contaminated with slurry and metal residues, and initiatives to recycle or recover pad materials, such as the circularity work Entegris presented in October 2026, are at an early stage. Pad manufacturing involves energy-intensive curing and, for soft pads, solvent use, which suppliers are addressing through solvent recovery and energy efficiency. Customers' requests for product carbon footprints and the scrutiny of PFAS across the semiconductor supply chain add to the environmental requirements that pad makers must meet. Climate-related physical risks are another consideration, since several major fab clusters, including those in Taiwan, southern Japan and Texas, have experienced droughts, typhoons or extreme weather events in recent years that disrupted water or power supplies. Such events affect pad consumption indirectly by reducing fab output and directly by disrupting logistics, and they reinforce the case for regional diversification of pad production and warehousing.
Legal
Legal factors include chemical regulation, trade law, intellectual property and contract terms. In Europe, REACH governs the substances used in pad production, including the diisocyanate restriction in force since August 2023, and the proposed PFAS restriction is expected to move to the Commission and member states after the final scientific opinions due by the end of 2026. In the United States, TSCA reporting obligations and occupational safety rules apply, and export-control and tariff regulations govern cross-border trade. Intellectual property is significant in pad technology: suppliers protect pad formulations, groove designs, window constructions and manufacturing methods through patents, and leading suppliers of CMP consumables have enforced their patents through litigation and administrative proceedings in the United States, Taiwan and China. As Chinese suppliers expand into more advanced pad designs, the scope for disputes over formulation and groove-design patents is likely to grow, and suppliers entering new markets must conduct freedom-to-operate reviews before launching products. Supply contracts with chipmakers include strict change-notification clauses, quality obligations and, increasingly, sustainability and conflict-minerals reporting requirements, which create legal obligations that pad suppliers must manage across all their markets.
Profiles of 32 companies operating in the CMP Pads Market market, including revenue, employee count, and market positioning where available.
Showing 32 of 32 companies
TWI is one of the few independent, founder-owned CMP pad makers left in the United States. It is a small Silicon Valley specialist that has outlasted a market now dominated by a few chemical and materials conglomerates. The company started with textile wipers and hard-disk-drive (HDD) polishing and texturing tapes. In the mid-1990s it used its knowledge of non-woven fibres and polyurethane to enter CMP. It became known in tungsten CMP: after a 1995 SEMATECH benchmark, TWI described itself as the world's largest supplier of tungsten CMP pads. Its technology combines the porosity of non-woven polyester with the hardness of solid polyurethane. It makes pads in sheets rather than cast cakes, and it holds patents on centrifugal casting of multilayer and optically transmissive pads. Its position today is niche. It serves tungsten, 200 mm and mature-node CMP, plus HDD tapes, through distributors in Europe and Asia. Its main appeal is lower cost of ownership: less slurry use, longer pad life and consistent pad-to-pad performance. --- **What the company does.** TWI designs, manufactures and sells consumable polishing materials used in two precision-manufacturing industries: 1. **Semiconductor fabrication.** It makes polishing pads for chemical mechanical planarization (CMP), the step that removes excess topography from silicon wafers after each metal or dielectric layer is deposited. TWI's pads are mainly used in tungsten CMP and also in oxide and copper/low-k steps. They have been qualified on all major polishing tool platforms, including Applied Materials' Mirra. 2. **Hard disk drive (HDD) manufacturing.** It makes textile polishing, texturing and wipe tapes used to finish disk media. Customers have included IBM, Komag, Akashic Memories and Showa Denko. **Company self-description.** TWI's website describes the company as an innovation leader in the HDD and semiconductor industries for more than 35 years. It says it offers customizable, durable product lines focused on CMP, backed by an in-house research and innovation team and a rigorous, personalized quality assurance system. Its standard description reads: "Located in Silicon Valley, Thomas West (TWI), incorporated in 1981, is a supplier of polishing, texturing and wipe tapes for hard disk drives (HDD), and polishing pads for Chemical Mechanical Planarization (CMP) in semiconductor manufacturing." **Business model.** TWI makes physical consumables and sells them as products. It does not disclose any subscription, licensing or service revenue. Its pads and tapes wear out in use, so demand follows customers' wafer starts and disk production rather than their capital-equipment cycles. That gives the business recurring revenue once a product is qualified. The CMP pad business follows the usual specialty-consumables pattern: a qualification at a fab takes a long time to win but tends to stay in place for years, because the fab must requalify its process before switching pads. TWI sells to customers in the United States directly and to customers in Europe and Asia through a network of semiconductor-supply distributors. **Revenue model mix.** **Product sales: CMP pads:** Role in the model: Main revenue line. Consumable pads sold per unit or per sheet. **Product sales: HDD tapes:** Role in the model: Long-standing second line. Polishing, texturing and wipe tapes for disk makers. **Product sales: backing films and accessories:** Role in the model: WestFilm carrier backing films for CMP polishing heads **Services:** Role in the model: Applications support from the Sunnyvale applications cleanroom. Not sold separately. **Licensing:** Role in the model: No out-licensing of the patent portfolio has been disclosed **Value-chain position.** TWI sits in the tier-two consumables layer of the semiconductor supply chain. Upstream are polyurethane prepolymers, curatives, non-woven polyester and adhesives. Downstream are wafer fabs and, through tool qualification, CMP equipment makers. Fabs buy its pads as process-of-record consumables. Pads are used with slurries from other suppliers, such as Entegris (CMC Materials), Fujimi, Resonac and Merck, so TWI's pitch rests on cutting slurry use, which its founder has said accounts for about 75% of total CMP consumable cost. **Customer types.** Integrated device manufacturers (IDMs) such as Texas Instruments; foundries and logic/analog fabs in Taiwan, China, Korea, Malaysia, the United States and Europe; mature-node 200 mm fabs; and HDD media makers. **End markets.** Semiconductor front-end fabrication (tungsten plug and interconnect CMP, oxide CMP, copper/low-k CMP), mostly at mature and specialty nodes; HDD media finishing; and other polishing uses named in the company's patents (metallurgical samples, optical components, lenses and photomask substrates). **Independent characterisation.** TWI is a niche, engineering-led consumables maker. At its peak in the early 2000s it was a real technology challenger in tungsten CMP. Since then its share has shrunk as DuPont (Rohm and Haas / Rodel), Entegris (CMC Materials / NexPlanar), Fujibo and, more recently, Chinese and Korean suppliers expanded. Its patent filings and distributor network are still active. However, it has made almost no public statements since about 2017. This suggests a company in maintenance mode, serving installed qualifications rather than competing for leading-edge process-of-record positions.
FNS Tech is a small-cap Korean supplier of process equipment and consumables that is moving from cyclical capital equipment to recurring semiconductor consumables. Its history is in wet-process equipment (cleaners, strippers, etchers, developers) for OLED display production, sold mainly to Samsung Display. Over the past decade it has built a materials and parts business. That business includes chemical-mechanical polishing (CMP) pads, a technology it acquired from InnoPad of the US in 2013 and localised in 2015. It also includes UV lamps and total-organic-carbon (TOC) units for ultrapure-water systems, and OLED mask and parts cleaning. In 2025 the company bought control of ASAHI LAMP, a Taiwanese maker of tungsten-halogen lamps for RTP and epitaxy tools that supplies Applied Materials and TSMC. In the first half of 2026, materials and parts made up 72% of revenue. CMP pads now ship for HBM3E/HBM4 production, and the company says it was the first to develop large-area CMP pads for glass-core packaging substrates. The investment case rests on high-margin consumables replacing lumpy display equipment as the main source of earnings. --- **Company description (FY2025 annual business report).** The company says it manufactures and sells equipment, parts and materials for semiconductor and display processes. It was founded to make flat-panel-display equipment and parts and materials for semiconductor manufacturing. For internal management it runs two operating units, Equipment Manufacturing and Parts & Materials. It reports a single segment because the two share customers, production sites and sales channels. **What the company does.** FNS Tech works in three areas of the fab supply chain: 1. **Display wet-process equipment.** It designs and builds turnkey wet stations for OLED and TFT-LCD panel lines: cleaners, strippers, etchers, developers and metal-mask cleaners, covering Gen-6 to Gen-8.6 IT panel lines. It has supplied OLED mass-production lines since 2009. It also offers roll-to-roll wet-process equipment and is extending its wet line-up to glass-core substrate processing (etching, cleaning, plating, developing, stripping, TGV processing). 2. **Semiconductor consumables and parts.** The products are polyurethane CMP pads (backside, recycled/reusable, and advanced-node/HBM grades, plus a new large-area glass-substrate pad), high-output UV lamps and TOC units for ultrapure-water treatment, and, through ASAHI LAMP, halogen lamps used as heat sources in rapid thermal processing (RTP) and epitaxial (EPI) deposition tools. 3. **Cleaning services.** These cover OLED fine-metal-mask and open-mask cleaning and process-part cleaning for display makers. **Business and revenue model.** Revenue is product revenue: equipment sold under project contracts and recognised as tools are delivered and accepted, and consumables sold on repeat purchase orders. Cleaning is a fee-for-service activity tied to customers' line utilisation. The company has no subscription or licensing revenue. The mix has changed sharply. Equipment was 72% of revenue in FY2024 and 53% in FY2025. Materials and parts reached 72% in the first half of 2026. SK Securities estimates that materials and parts generate about 90% of operating profit. At ASAHI LAMP, about 85% of revenue comes from aftermarket replacement sales rather than OEM tool shipments. **Value-chain position.** In display, FNS Tech is a tier-1 equipment vendor to panel makers. In semiconductors it is a tier-1 consumables supplier to device makers (Samsung Electronics, SK hynix, Micron, TSMC, CXMT). Through ASAHI LAMP it is also a component supplier to equipment OEMs (Applied Materials) and to fabs buying aftermarket lamps. **Customer types and end-markets.** Named customers include Samsung Display, Samsung Electronics, SK hynix, TSMC, CXMT and Chemtronics. ASAHI LAMP's customers include Applied Materials, TSMC, Micron, Samsung Electronics, SK hynix, and Chinese and Taiwanese foundries and toolmakers. End-markets are OLED panels for IT devices and foldables, DRAM and HBM memory, NAND, leading-edge and mature foundry, and advanced packaging (glass-core substrates for AI accelerators). **Independent characterisation.** FNS Tech is best seen as a consumables company growing inside a shrinking display-equipment shell. Display equipment depends on Samsung Display's capital spending, which has been irregular. In 2024 the company described its main display customer as bringing some OLED front-end wet equipment in-house. The consumables business, by contrast, has recurring demand linked to wafer starts, HBM stack counts and the number of CMP steps per wafer. It also has structurally higher margins: lamps and pads run at operating margins above 30%, and ASAHI LAMP at about 50%. The open question is whether CMP pads can grow beyond a niche position against Qnity (formerly DuPont), which holds roughly 80% of the global market.
IV Technologies was the first Taiwanese company to break the near-monopoly of the US majors in CMP polishing pads using its own technology. It is now the only domestic CMP pad supplier qualified at Taiwan's leading foundries, memory makers and packaging houses. The company grew out of a polyurethane (PU) chemicals business founded in 1986 and controls its whole value chain, from in-house PU synthesis and pore-forming chemistry through groove design and machining. It says it is the only company that makes CMP pads by reaction injection molding (RIM). It holds 142 patents in Taiwan, the US and China and has shipped more than 1.1 million pads. Its global CMP pad share is about 3 to 4%, against roughly 80% for the DuPont business now operating as Qnity Electronics. Management aims to reach 10% through advanced-packaging pads for CoWoS and SoIC, a new soft-pad line for CoWoS-L, silicone membranes, and dual production bases in Taiwan and mainland China that serve customers in both markets as supply chains are localized. Customers include TSMC, Micron and Nexchip. The financial profile is that of a high-margin specialty-materials company: consolidated gross margin was 53.9% in the first half of 2026, and the semiconductor line earns above the group average. --- **What the company does.** IV Technologies designs, formulates, manufactures and services polymer polishing pads for the CMP step in semiconductor manufacturing. CMP flattens the wafer surface between lithography, deposition and etch layers. It is repeated many times per wafer, and the number of steps rises as logic nodes shrink, as 3D NAND gains layers and as advanced packaging adds hybrid-bonding and redistribution layers. The pad works alongside the slurry, the diamond disc conditioner and the wafer. Its hardness, compressibility, pore structure and groove pattern determine removal rate, uniformity and defect levels. Management estimates that the pad accounts for about one third of the cost of CMP consumables. The group also makes polishing-head silicone membranes, soft polishing pads, sub-pads and pads with endpoint-detection windows. Its customers span reclaimed wafers and wafer substrates, logic and memory front-end fabs, and back-end advanced packaging. **The parent's own description.** PVI describes itself as a group built on PU materials technology with three product lines: "semiconductor polishing pads and consumables," "medical and sports products," and "green, environmentally friendly adhesives," with the semiconductor polishing pad business as its strategic focus. Its description of IV Technologies is the subsidiary that first broke the international majors' monopoly in CMP polishing pads with proprietary technology, with products adopted across the upstream, midstream and downstream semiconductor supply chain. The group's chemicals and medical businesses sit mainly in a second subsidiary, PVI Chemical Co. (久陞昌企業). That subsidiary is the exclusive contract manufacturer of medical insoles for Dr. Scholl's, North America's largest insole brand, and holds about 18% of the North American professional medical insole market. **Business and revenue model.** **Product sales, no licensing or subscriptions:** Pads are high-value consumables used up on every wafer. Revenue therefore tracks wafer starts and the number of CMP steps per wafer rather than tool purchases, which makes this a replacement business and not a capital-equipment one. **Specification-driven qualification:** Each pad is qualified for a specific customer, tool, slurry, disc and process step. Management says a new pad must deliver at least 30% better value to the customer before it is adopted. As of June 2026 the company had 212 products in mass production and 403 development projects. Once qualified, a pad is rarely displaced, so revenue is sticky. **Consignment and vendor-managed inventory:** In mid-2026 the largest customer switched from invoice-on-shipment to consignment, with revenue recognized when the pad is used. That pushed recognition back by about six weeks in June and July 2026. **Value-chain position:** IV Technologies sits in Tier-1 materials: it supplies fabs directly and works with tool makers. It synthesizes key PU prepolymers within the group and keeps about six months of raw-material inventory. That gives it more control over costs and supply than competitors that buy PU systems from outside. **Customer types and end-markets.** **Wafer substrate / reclaim:** Examples (disclosed in public reporting): GlobalWafers (supply-chain reports); reclaim-wafer houses; Pad applications: Stock removal and final polishing of silicon substrates and reclaimed wafers **Foundry: advanced and mature logic:** Examples (disclosed in public reporting): TSMC, UMC, Powerchip (PSMC), Nexchip; Pad applications: Oxide, STI, tungsten and copper CMP steps; advanced-node FEOL and BEOL **Memory:** Examples (disclosed in public reporting): Micron, Macronix, Winbond; Powerchip's DRAM legacy (first adopter, 2003); Pad applications: DRAM and NAND dielectric and metal CMP **Advanced packaging / OSAT:** Examples (disclosed in public reporting): ASE; foundry-run CoWoS and SoIC lines; Pad applications: Redistribution-layer, interposer and hybrid-bonding planarization; CoWoS-L soft-pad steps **Independent characterization.** IV Technologies is a niche challenger with real qualification depth in a market controlled by one US supplier. Its competitive edge does not come from scale. It comes from three things. First, a cost and design advantage from RIM and single-piece free-foaming. Second, chemistry it controls, including water-blown carbon dioxide pores that avoid some solvent-based blowing agents. Third, its position as the domestic second source to the world's most important foundry, at a time when fabs want supply diversity and the US-China split is pushing Chinese fabs away from US vendors. Revenue is split almost equally between Taiwan and mainland China, so IV Technologies benefits from localization pressure on both sides of the Strait. The consolidated group still carries a lower-margin non-semiconductor business, about one third of revenue, which dilutes reported growth and margins but provides cash flow.
Enpulse is Korea's leading domestic producer of CMP polishing pads, the polyurethane consumable used with slurry to planarize wafers after deposition, etch and lithography. It started in 2015 as an import-substitution project inside SKC and broke into a market where two U.S. suppliers have historically held more than 90% of global share. It qualified pads at Korean memory and foundry fabs and, by its own account, overtook DuPont as the leading pad supplier at a major Korean customer in March 2021. Its differentiators are in-house prepolymer and additive synthesis, a hybrid pore system that combines solid microspheres with inert-gas foaming, single-sheet casting, and a highly automated Cheonan plant. Since the 2025 carve-out under Hahn & Company, Enpulse has been a standalone pure-play pad company. It is widening qualifications to Chinese and Taiwanese chipmakers, building a Yongin R&D center, and marketing VDC-free, MOCA-free, chlorine-reduced and bio-based pads. Its scale is small next to the market leaders. Last disclosed annual revenue was KRW 40.3 billion (FY2023). **Relationship to "SK enpulse":** Global CMP pad market studies, including the Global CMP Pads Market reports, list this business as "SK enpulse." Until April 2025 the CMP pad operation was a division of SK enpulse Co., Ltd. (formerly SKC Solmics, KOSDAQ: 057500), a wholly owned semiconductor-materials subsidiary of SKC Co., Ltd. (KRX: 011790). Private equity firm Hahn & Company agreed to buy the division in December 2024 through a special-purpose company, Hahn & Co No. 32 Co., Ltd. The deal closed on 4 April 2025 at KRW 334.6 billion, and the acquiring company took the name Enpulse Co., Ltd. that month. The former parent, SK enpulse, sold or spun off its other businesses and was merged into SKC on 22 December 2025. It no longer exists as a separate company. Enpulse Co., Ltd. is the only current entity that makes and sells the CMP pads tracked under the "SK enpulse" name. **What the company does.** Enpulse designs, makes and sells CMP polishing pads for semiconductor wafer fabrication and does related R&D. The company lists its business scope as "CMP Pad manufacturing and sales, and research and development." It has no other product line. Before the carve-out, SK enpulse also ran blank masks, CMP slurry, testers and EFEM equipment. None of those businesses moved to Enpulse. The blank mask and slurry units were sold to other buyers, and the back-end equipment business went to ISC Co., Ltd. **Company self-description.** The corporate website calls Enpulse a CMP Pad technology company that aims to become "Global No.1" in semiconductor CMP pads. It says it offers a "total solution" that integrates development, production, quality and safety, health and environment (SHE). It highlights a fully automated smart factory with real-time data, customer-specific pad design backed by integrated evaluation and analysis, and SHE-based management. The CEO message says Enpulse began developing CMP pads in 2015 in Korea, which then had no domestic CMP pad industry. It also says the company built the world's first fully automated CMP pad smart factory in Cheonan in 2020 and is building a Yongin research center for basic and product-development R&D. "Global No.1" is a stated ambition. On available market data, Enpulse is a mid-tier supplier by global revenue. **Business model and revenue model.** Revenue comes entirely from product sales of a recurring, high-turnover fab consumable. Pads wear out and are replaced at regular intervals on each CMP platen, so demand tracks wafer starts and the number of CMP steps per wafer. The number of CMP steps rises with 3D NAND layer counts, DRAM and HBM complexity, and advanced logic interconnect layers. No service, subscription or licensing revenue has been disclosed. Pads are qualified process-of-record (POR) materials. Each design-in follows months to years of joint development and fab qualification for a specific layer, slurry and tool. Once a pad is qualified, switching costs are high and volumes are sticky. That makes qualification wins the main leading indicator of future revenue. **Value-chain position.** Enpulse sits in the front-end fab-materials layer. Upstream, it buys isocyanates, polyols, curing agents, microspheres and sub-pad laminates. Its stated advantage is that it synthesizes its own prepolymers and additives rather than buying finished prepolymer. Downstream, it sells directly to integrated device manufacturers (memory and logic) and foundries running 200 mm and 300 mm lines. CMP tool makers and slurry suppliers are partners in co-optimization. **Customer types and end-markets.** The customers are memory IDMs, logic and foundry fabs, and 200 mm specialty foundries. Korean press reports name SK hynix and DB HiTek as main supply relationships. Enpulse's corporate history gives anonymized qualification records with customers in Korea ("S", "D", "O"), China ("I", "S") and Taiwan ("M"). The English site claims more than 100 global clients but names none. The end-markets are DRAM and HBM, 3D NAND, foundry and logic, and mature-node analog and power devices on 200 mm. **Independent characterization.** Enpulse is a focused, sub-scale challenger in a concentrated oligopoly. Qnity (formerly DuPont Electronics) and Entegris (which absorbed CMC Materials) lead the market. Hubei Dinglong is scaling fast inside China. Enpulse's advantages are proximity to Korean memory fabs, vertical integration into raw materials and a demonstrated record of qualifications. Its weaknesses are revenue concentration, scale (about 180,000 pads a year of installed capacity against Dinglong's roughly 600,000 target), and the change in ownership, which turned a captive SK-group supplier into an independent PE-owned company. The investment case rests on diversifying customers in China and Taiwan, moving the mix to advanced nodes, and margin recovery that began in 2024.
RTX occupies a structurally advantaged position that no other prime replicates: roughly half its revenue is commercial aerospace and half defence, giving it a natural hedge across two cycles that rarely peak together — and which, unusually, are peaking together in 2026. Collins Aerospace and Pratt & Whitney are entrenched on the installed base of the global narrowbody and widebody fleet, generating decades-long, high-margin aftermarket annuities. The Raytheon segment is the Western world's dominant supplier of ground-based air and missile defence effectors — Patriot, GEM-T, AMRAAM, Standard Missile, ESSM — precisely the munitions category that European rearmament and Middle East conflict have made scarce. A record $289 billion backlog at 30 June 2026, equal to roughly three years of sales, converts that positional advantage into unusual revenue visibility. The offsetting reality is that RTX carries $37 billion of debt, an $85 billion goodwill-and-intangible balance from the merger, and the unresolved cost tail of the GTF powder-metal remediation. RTX Corporation is the world's largest aerospace and defence company by revenue, and the only prime contractor that simultaneously holds franchise positions in commercial aircraft engines, commercial aerospace systems, and ground- and sea-based integrated air and missile defence. It was created in April 2020 by the merger of Raytheon Company with the aerospace businesses of United Technologies Corporation, and it renamed itself from Raytheon Technologies to RTX in July 2023 alongside a consolidation from four operating segments to three. --- ### What the company does RTX designs, manufactures, and services aerospace and defence systems for commercial airlines, aircraft OEMs, business aviation operators, the U.S. Government (principally the Department of Defense, latterly styled the Department of War in contract announcements), and allied governments worldwide. Its FY2025 Form 10-K describes the three segments as follows: Collins Aerospace provides advanced aerospace and defence products; Pratt & Whitney supplies aircraft engines; and Raytheon delivers defensive and offensive threat detection and mitigation capabilities. The company's independent characterisation is better expressed as three distinct economic engines bolted onto one balance sheet: 1. **An installed-base annuity business (Pratt & Whitney and, to a lesser degree, Collins).** Engines and nacelles are sold at or near cost — sometimes at a loss — to win position on an airframe, after which spare parts, overhauls, and long-term service agreements generate profit for twenty to thirty years. This is why Pratt & Whitney's reported segment margin (8.3% in FY2025) looks weak against Collins (16.2%) despite comparable revenue: Pratt is still absorbing original-equipment loss content on the GTF ramp while the aftermarket annuity has yet to reach maturity. 2. **A cost-plus and fixed-price government contracting business (Raytheon, plus Collins' defence lines).** Revenue is recognised over time on the percentage-of-completion basis, which makes reported margins highly sensitive to estimate-at-completion revisions. The FY2024 $575 million charge on a terminated foreign fixed-price development contract is the canonical illustration. 3. **A component and systems supply business (Collins).** Avionics, interiors, power management, and aerostructures sold to Airbus, Boeing, Embraer, Bombardier, and defence primes, with a large parts-and-repair aftermarket layered on top. ### Revenue model and mix | Metric | FY2025 | |---|---| | Commercial share of sales | 48% | | Defence share of sales | 52% | | Products share of sales | ~74% | | Services share of sales | ~26% | | Sales to U.S. Government (excl. FMS) | $33,279m (38% of net sales) | | Total international sales | $41,312m (47% of net sales) | | Total backlog | $268bn ($161bn commercial / $107bn defence) | | Backlog expected to convert within 12 months | ~25% | Sources: FY2025 Form 10-K Item 1 (U.S. government and international sales tables, backlog); RTX 2025 Annual Report sales-mix infographic; Q3 2025 disclosure for the product/service split. Note the structural shift: U.S. Government sales fell from 46% of revenue in FY2023 to 38% in FY2025 — not because U.S. volume declined (it rose from $31.6bn to $33.3bn) but because international and commercial revenue grew far faster. This is the single most important mix fact in the company today, because international direct commercial sales carry materially better margins than U.S. cost-type work, and because European air-defence procurement is the fastest-growing pool RTX addresses. ### Value chain position and customers RTX sits at the prime and Tier-1 layers simultaneously. On F-35 it is a major subsystem supplier (F135 propulsion via Pratt; sensors and avionics via Collins) to prime contractor Lockheed Martin — a direct competitor at the enterprise level. On Patriot and SPY-6 it is the prime. On A320neo it is a propulsion and nacelle supplier to Airbus, which in March 2026 was reported to be formally seeking damages from Pratt & Whitney over GTF disruption. This simultaneous supplier/competitor/counterparty posture across the same customer set is a defining feature of RTX's commercial relationships and a recurring source of litigation and negotiation risk. **End-markets served:** commercial air transport (OE and aftermarket); regional and business aviation; rotorcraft; military fixed-wing and rotary propulsion; integrated air and missile defence; naval combat systems; precision-guided munitions; space sensing and communications; airport and airline IT infrastructure; and government training and mission services.
### Identity and listing | Item | Detail | |---|---| | Entity profiled | Illinois Tool Works Inc. (exact legal-name match; active; publicly listed). The input classification "Public company" is confirmed | | Former names | None of significance disclosed. The company has operated as Illinois Tool Works since founding. Commonly abbreviated "ITW" | | Founded | 1912, Chicago, Illinois. Incorporated 1915 (Form 10-K FY2025) | | Jurisdiction of incorporation | Delaware, USA (Form 10-K FY2025) | | IRS Employer ID | 36-1258310 | | Headquarters | 155 Harlem Avenue, Glenview, Illinois 60025, USA. Tel. (847) 724-7500 | | Exchange / ticker | New York Stock Exchange: ITW (common stock) | | Other listed securities (NYSE) | Euro notes: 0.625% due 2027 (ITW27); 3.250% due 2028 (ITW28); 2.125% due 2030 (ITW30); 1.00% due 2031 (ITW31); 3.375% due 2032 (ITW32); 3.00% due 2034 (ITW34) | | ISIN / CUSIP | US4523081093 / 452308109 | | Fiscal year end | 31 December | | Index membership | S&P 500 constituent. Fortune 300 company (company description, 2026) | ### Scale and organisation | Item | Detail | |---|---| | Employees (latest) | About 43,000 at 31 Dec 2025; about 16,000 in the U.S. (Form 10-K FY2025) | | Employee trend | About 46,000 (FY2022 release); about 45,000 (FY2023); about 44,000 (FY2024 release); about 43,000 (FY2025). This is a steady decline driven by 80/20 simplification and productivity, not by revenue contraction | | Organisation | 88 divisions in 49 countries; about 410 plants and office facilities (Form 10-K FY2025) | | Auditor | Deloitte & Touche LLP. Ratification proposed for FY2026 (2026 Proxy) | | Holders of record | About 3,957 at 31 Jan 2026 | | Website | www.itw.com / investor.itw.com | ### Market data | Item | Detail | |---|---| | Shares outstanding | 288.2 million at 31 Jan 2026 (Form 10-K). About 284 million estimated at 30 Jun 2026, after 4.3 million shares were repurchased in H1 2026 (10-Q Q2 FY2026; derived) | | Market capitalisation (current) | About $82 billion. Basis: share price of roughly $288–$295 (5 Aug 2026 close $295.06; early-September 2026 dividend yield of 2.39% implies about $288) × about 284 million shares | | Market cap at 31 Dec 2025 | About $71 billion (2026 Proxy) | | Market cap discrepancies | Third-party aggregators show $71bn–$85bn depending on date. Live verification is recommended | | 52-week range | $238.82 – $303.16 (as of Aug 2026, aggregator data) | Illinois Tool Works is a 114-year-old, Glenview-based multi-industrial manufacturer with $16.0 billion of FY2025 revenue across seven segments: - Automotive OEM - Food Equipment - Test & Measurement and Electronics - Welding - Polymers & Fluids - Construction Products - Specialty Products ITW does not compete on scale or vertical integration. Its edge is a proprietary operating system, the "ITW Business Model," built on three elements: - **80/20 Front-to-Back management**, which concentrates resources on the largest, most profitable customers and products. - **Customer-Back Innovation (CBI)**, which develops products from customer pain points rather than from a central R&D lab. **A decentralised, entrepreneurial culture:** of 88 scaled-up divisions. Since launching its Enterprise Strategy in late 2012, ITW has lifted operating margin from 15.9% to 26.3% and after-tax ROIC from 14.5% to 29.3%. It has done this while shrinking revenue through divestiture of commoditised businesses (2026 Proxy). The "Next Phase" (2024–2030) pivots the agenda from margin expansion to sustained 4%+ organic growth, powered by a 3%+ CBI revenue yield. ITW is a Dividend King, with 63 consecutive annual dividend increases. --- ### Company's own description (Form 10-K FY2025, paraphrased) ITW describes itself as a global manufacturer of a diversified range of industrial products and equipment, organised into 88 divisions operating in 49 countries. Its seven reportable segments are grouped by similar product offerings and end markets. Products are distributed mainly direct to industrial manufacturers and through independent distributors. Backlog is not considered significant because delivery periods are short and inventory turns quickly. The company names its core competitive advantage as the ITW Business Model: - 80/20 Front-to-Back process - Customer-Back Innovation - Decentralised entrepreneurial culture Primary raw materials are steel, resins and chemicals, sourced from numerous commercial suppliers. ### Business model | Revenue type | Characterisation | Evidence | |---|---|---| | Product sales: consumables | Majority of revenue. Welding filler metals; Polymers & Fluids chemicals; fasteners; Hi-Cone carriers; marking inks; test consumables; contamination-control wipes | Segment product lists (10-K FY2025) | | Product sales: capital equipment | Welding power sources; food equipment; test systems (Instron, MTS); electronic assembly equipment; line automation | Segment product lists (10-K FY2025) | | Services | Food Equipment service, maintenance and repair (service organic growth +2.8% FY2025, +4.8% FY2024); aftermarket service in Test & Measurement | 10-K FY2025 Food Equipment discussion | | Software / subscription | Test & measurement software is embedded with equipment. Not reported separately | Not publicly disclosed | | Licensing | Not material / not disclosed | Not publicly disclosed | ITW's model rests on niche leadership in fragmented, technically demanding markets. Its businesses typically hold strong positions in specialised applications where: - the product is a small share of the customer's total cost but critical to performance (e.g., an automotive fastener, a weld wire, a test frame); and - differentiation comes from engineering, application know-how, brand and service. The 80/20 discipline continually prunes low-value SKUs and customers through Product Line Simplification (PLS). PLS deliberately reduced organic revenue by about 60 basis points in FY2024, about 60 bps in FY2025, and about 60 bps in H1 FY2026, in exchange for structurally higher margins (10-K FY2025; 10-Q Q2 FY2026). **Revenue model mix.** ITW does not report a formal product/service/subscription split. The analyst characterisation is: ### Value-chain position ITW sits as a Tier-1/Tier-2 component supplier (Automotive OEM, Specialty appliance components) and as an OEM of branded equipment and consumables (Welding, Food Equipment, Test & Measurement, Construction Products, Polymers & Fluids). It typically manufactures "in the market, for the market." This localisation was cited in FY2025 as the reason ITW could largely offset U.S. tariff costs through pricing and supply-chain actions (FY2025 release; 10-K FY2025). ### Customer types and end markets | Segment | Primary end markets (10-K FY2025) | Customer type | |---|---|---| | Automotive OEM | Automotive OEMs and tiers | Global and Chinese OEMs; Tier-1 suppliers | | Food Equipment | Food service, food retail, food institutional/restaurant | Restaurant chains, independents, institutions (healthcare, education), supermarkets | | Test & Measurement and Electronics | Electronics/semiconductor, general industrial, auto OEM/tiers, energy, industrial capital goods, consumer durables | R&D labs, quality labs, semiconductor fabs, electronics assemblers | | Welding | General industrial (fabrication, shipbuilding), construction, energy, MRO, capital goods, auto | Fabricators, contractors, OEMs; heavily via distributors | | Polymers & Fluids | Automotive aftermarket, general industrial, MRO | Retail auto-care, body shops, industrial maintenance | | Construction Products | Residential construction, renovation/remodel, commercial construction | Contractors, truss fabricators, big-box retail | | Specialty Products | Food and beverage, consumer durables, airlines, general industrial, capital goods, printing/publishing | Beverage packers, appliance OEMs, airports/airlines, packaging converters | ### Independent characterisation ITW is best understood as a portfolio of about 88 mid-sized, high-return niche franchises bound together by a common management system. Corporate allocates capital. Divisions run the business. Strengths of this structure: - A low-capital-intensity, cash-generative model. Capex was 2.6% of revenue in FY2025 ($419M on $16,044M), and after-tax ROIC is about 29–31%. - Demand is diversified across consumer, industrial and capex cycles. Weaknesses of this structure: - Organic growth has historically been modest (FY2023–FY2025 averaged roughly 0–2%). - PLS creates a built-in headwind to reported growth. - The company has unusually high exposure to Detroit-3 and European auto content, short-cycle construction, and the semiconductor capex cycle. The FY2026 data, with Q2 organic growth of +4.5% and double-digit growth in Welding and Test & Measurement, is the first meaningful evidence that the CBI-driven growth pivot may be gaining traction.
110 interactive charts drawn from the CMP Pads Market dataset — market size, each segment breakdown, and every region and country by segment. Open one to read its full data table and download it.
Global CMP Pads Market By Region
Global CMP Pads Market By Pad Type
Global CMP Pads Market By Application
Global CMP Pads Market By Wafer Size
Global CMP Pads Market By End User
Global CMP Pads Market — North America by Country
Global CMP Pads Market — North America by End User
Global CMP Pads Market — North America by Pad Type
Global CMP Pads Market — North America by Wafer Size
Global CMP Pads Market — North America by Application
Global CMP Pads Market — U.S. by End User
Global CMP Pads Market — U.S. by Pad Type
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