Market Size (2025)
$3.84B
Vertical: SEMIBase Year: 2025
Market Size (2025)
$3.84B
Projected (2032)
$6.45B
CAGR (2022–2032)
6.6%
Key Players
12+
Market Overview
Chemical mechanical planarization (CMP) is the polishing step that restores a flat, defect-free wafer surface after deposition and etch, and it is repeated many times during the fabrication of every advanced logic, memory and power device. The consumables used in that step, the abrasive slurries that combine chemical attack with mechanical removal and the polymer pads that carry the slurry and transmit polishing pressure, form a recurring materials market whose demand is tied to wafer starts, to the number of planarization steps in each process flow and to the material diversity of each device generation. The Global CMP Slurries and Pads Market was valued at USD 3.842 Billion in 2025 and is projected to reach USD 6.454 Billion by 2032, expanding at a CAGR of 7.6% over 2026–2032. This represents an absolute increase of USD 2.612 Billion between 2025 and 2032.
The historical series reflects the cyclical character of semiconductor materials demand. Market value stood at USD 3.412 Billion in 2022 and contracted in 2023, when memory makers cut wafer starts sharply and foundry utilisation on mature nodes fell, before recovering to USD 3.517 Billion in 2024 and moving above the 2022 level in 2025. Because slurries and pads are consumed in proportion to wafers polished rather than purchased as capital equipment, the market tracks fab utilisation closely and recovers as soon as wafer starts return. The forecast period is characterised by steady year-on-year growth rather than a single step change, supported by additional CMP steps at gate-all-around and backside power nodes, by the rising number of layers in 3D NAND and high-bandwidth memory, and by the use of CMP in hybrid bonding and wafer-level packaging.
Key Findings
By product type, Oxide & STI Slurries (Ceria / Colloidal Silica) form the largest segment, with a value of USD 1.042 Billion and a 27.1% share in 2025. These slurries polish the silicon dioxide and silicon nitride films used for shallow trench isolation, interlayer dielectrics and the many oxide layers of 3D NAND stacks, which makes them the most widely used chemistry in any fab. Specialty Slurries (Poly-Si, Nitride, SiC / GaN) are the fastest-growing product type, with a CAGR of 10.8% over 2026–2032, rising from USD 0.308 Billion in 2025 to USD 0.640 Billion in 2032 as gate-all-around transistors, polysilicon-heavy memory structures and wide-bandgap substrates call for formulations with tightly controlled selectivity.
By application or process step, BEOL Interconnect (Cu, Barrier, ILD) is the largest segment at USD 1.480 Billion, or 38.5% of the market in 2025, because each additional copper metal layer requires bulk copper, barrier and dielectric polishing. Advanced Packaging & Hybrid Bonding (TSV, RDL) is the fastest-growing application, with a CAGR of 11.7%, and its value is projected to rise from USD 0.386 Billion in 2025 to USD 0.852 Billion in 2032.
By end user, Foundries are both the largest and the fastest-growing segment. They accounted for USD 1.412 Billion, or 36.7% of 2025 value, and are expected to grow at a CAGR of 8.4% to reach USD 2.504 Billion in 2032, reflecting the concentration of leading-edge logic and advanced packaging capacity in foundry hands.
By region, Asia Pacific is the leading market with USD 2.851 Billion and a 74.2% share in 2025, a position grounded in the concentration of foundry, memory and wafer-manufacturing capacity in Taiwan, South Korea, China and Japan. Middle East & Africa is the fastest-growing region, with a CAGR of 8.6%, although from a small base of USD 0.092 Billion in 2025. North America follows closely with a CAGR of 8.4%, as new fabs in Arizona, Texas, New York and Idaho ramp.
By country, China is the largest individually reported country market with USD 0.855 Billion in 2025, equal to 22.3% of global value, and it is projected to grow at 8.2% annually to USD 1.494 Billion in 2032. The Rest of Asia Pacific grouping, which aggregates several large producing economies, is larger in combined value at USD 1.511 Billion. India is the fastest-growing country market, with a CAGR of 14.4%, rising from USD 0.103 Billion in 2025 to USD 0.274 Billion in 2032 as its first fabrication and assembly projects move into production.
Segmentation Summary
The market is analysed across three segmentations taken from the study data, Product Type, Application / Process Step and End User, together with five regions and twenty country-level entries. Across these segmentations, the largest category in each segmentation is a high-volume, front-end application that is present in every fab, while the fastest-growing categories are concentrated in newer process requirements: specialty slurries, packaging-related planarization and the foundry customer base that leads node migration.
Several patterns stand out. The pad categories behave differently from one another: Hard Polyurethane CMP Pads hold USD 0.875 Billion, or 22.8% of 2025 value, and grow at 7.4%, close to the market average, while Soft & Specialty CMP Pads grow faster at 8.6% because finishing, buffing and packaging steps require compliant pads with lower defectivity. Among slurries, Copper & Barrier Slurries grow at 8.0%, faster than Oxide & STI Slurries at 6.9%, reflecting the increase in metal layers in AI processors, while Tungsten, Cobalt & Other Metal Slurries grow at the slowest rate of 5.9% because contact and via metallisation is partly shifting toward alternative metals and thinner fills. Within applications, MOL / Contact (W, Co) grows at the slowest rate of 6.4%, consistent with this shift. Bare Wafer & Substrate Polishing (Si, SiC, GaN) grows at 6.9%, supported by silicon wafer volume and the transition of silicon carbide substrates to 200 mm.
Regional and Country Highlights
Asia Pacific dominates consumption because the world's largest foundry, memory and wafer-manufacturing bases are located there. Within the region, the Rest of Asia Pacific grouping holds USD 1.511 Billion in 2025, China USD 0.855 Billion, Japan USD 0.382 Billion and India USD 0.103 Billion. China's growth of 8.2% is driven by continued fab construction and by the substitution of imported consumables with domestic slurries and pads, while Japan grows at 6.5% as memory output and new logic capacity in Kumamoto and Hokkaido offset a mature installed base. India grows at 14.4%, the highest rate of any country in the study, reflecting the start-up of assembly and test facilities in Gujarat and Assam and the first silicon fab under construction at Dholera.
North America is the second-largest region at USD 0.561 Billion in 2025 and is expected to reach USD 0.992 Billion by 2032. The U.S. accounts for USD 0.497 Billion of regional value in 2025 and is the fastest-growing country in the region at 8.5%, as fabs supported by the CHIPS and Science Act move from construction into volume production. Mexico, at USD 0.035 Billion, and Canada, at USD 0.029 Billion, are smaller markets centred on assembly, test and specialty device activity.
Europe recorded USD 0.304 Billion in 2025 and is projected to grow at 7.9%. Germany is the largest country market at USD 0.103 Billion, anchored by Dresden's logic and power fabs and by silicon wafer production, while Italy grows fastest at 8.4%, supported by silicon carbide and advanced packaging investment. Latin America, at USD 0.035 Billion in 2025, is led by Brazil, and Middle East & Africa, at USD 0.092 Billion, is led by the Rest of MEA grouping, which includes the region's established fabrication base; within the named Gulf markets, Saudi Arabia grows fastest at 10.7%.
Competitive Landscape Summary
The market is moderately consolidated. A small group of suppliers with global manufacturing networks and deep qualification histories at leading foundries and memory makers accounts for most of the value, while regional specialists compete in particular chemistries or customer bases. Entegris, which acquired CMC Materials in July 2022, offers the broadest combined portfolio of slurries, pads, post-CMP cleans and slurry filtration. Qnity Electronics, separated from DuPont on 1 November 2025, leads in polyurethane pads and also supplies slurries; in October 2025 it signed a long-term CMP pad supply agreement with SK hynix and in March 2026 opened a new facility in Newark, Delaware, whose first line produces pad components. Fujifilm is a leading supplier of copper and barrier slurries and has expanded production in Kumamoto and Belgium. Resonac holds a strong position in ceria slurries for oxide and STI polishing, and Merck KGaA, through its Versum Materials heritage, supplies dielectric, tungsten and copper slurries. Fujimi Incorporated leads in silicon wafer polishing slurries, AGC supplies ceria-based formulations, and Anji Microelectronics and Hubei Dinglong have become the principal domestic suppliers of slurries and pads in China.
Competition centres on process performance at the customer's tool, including removal rate, selectivity, dishing and erosion control and, above all, defectivity, rather than on list price. Long qualification cycles create high switching costs, so share changes tend to occur at node transitions or when a new fab is qualified. Capacity investment close to customer fabs, co-optimisation of pad, slurry and cleaning chemistry, and supply-chain resilience for abrasives and polymer precursors are the main levers suppliers are using to defend and gain share.
Challenges and Opportunities
The principal challenges relate to supply security and customer concentration. Ceria abrasives depend on rare-earth supply chains centred in China, and China's 2025 export-control actions on rare-earth items, partly suspended until November 2026, have prompted slurry makers to qualify second and third sources. Pad production relies on specialised polyurethane precursors and hollow microspheres from a limited number of producers. A small number of foundry and memory customers account for a large share of global demand, which gives them considerable pricing power and makes supplier revenue sensitive to their capacity decisions, as the 2023 contraction showed. Chemical regulation is also tightening: the European Union's proposed universal PFAS restriction advanced through the scientific committees of the European Chemicals Agency in 2026, and suppliers must document the fluorinated surfactants and additives used in some formulations.
Opportunities are concentrated where process requirements are changing fastest. Hybrid bonding for chiplets and stacked memory requires copper and dielectric surfaces with nanometre-level control of dishing and roughness, which raises the value of each packaging-related polish. Gate-all-around transistors, backside power delivery and new contact metals such as molybdenum and ruthenium call for new selective chemistries. Silicon carbide and gallium nitride substrates require specialised slurries and pads, and domestic semiconductor programmes in the U.S., Japan, Europe and India create demand for locally produced and locally qualified consumables.
Future Outlook
The market is expected to grow every year of the forecast period, from USD 4.153 Billion in 2026 to USD 6.454 Billion in 2032. Growth will be broad-based across product types, but the mix will move gradually toward specialty slurries, copper and barrier chemistries and soft pads, and toward packaging-related applications, whose share is projected to rise steadily through 2032. Foundries will remain the anchor customer group, and memory makers will continue to add CMP intensity as 3D NAND layer counts rise and high-bandwidth memory stacks become taller. Asia Pacific will remain the dominant region, while North America, Middle East & Africa and India will grow faster than the global average as new fabrication and assembly capacity is commissioned. Suppliers that combine broad chemistry portfolios with regional manufacturing, secure raw-material sourcing and close process engineering support at the customer's fab are best placed to capture this growth. Several uncertainties could shift the path of the market within this overall trajectory.
The pace at which memory makers convert higher prices into new wafer capacity, the timing of hybrid bonding adoption in high-bandwidth memory, the outcome of China's rare-earth export-control suspension in November 2026, and the scope of any broader U.S. tariffs on semiconductor supply chains are the main variables to monitor. Price erosion on mature consumables will continue to offset part of the volume growth, so the introduction of new formulations for advanced nodes, bonding and wide-bandgap materials will remain the principal source of value growth for suppliers.
The CMP Slurries and Pads Market market is projected to grow at a CAGR of 6.6% from 2022 to 2032.
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View Subscription PlansDefinition
Chemical mechanical planarization, also referred to as chemical mechanical polishing, is a wafer-processing step that removes surface topography and excess material by combining a chemical reaction at the wafer surface with mechanical abrasion. In a CMP tool, a rotating wafer held face down in a carrier head is pressed against a rotating polishing pad while a slurry is dispensed onto the pad. The chemistry of the slurry softens, oxidises, complexes or hydrolyses the top few nanometres of the film being polished, and abrasive particles suspended in the slurry, together with the asperities of the pad surface, remove that modified layer. Because high points on the wafer experience greater local pressure than low points, they are removed faster, and the surface is progressively flattened. The process ends either at a fixed time or, more commonly in advanced fabs, when an endpoint detection system senses that an underlying stop layer has been exposed.
The technique was developed for semiconductor manufacturing at IBM and entered volume production as chips moved from one or two metal layers to multilevel interconnects. Before CMP, each deposited layer reproduced the topography of the layer beneath it, so surface steps accumulated as layers were added and eventually exceeded the depth of focus of lithography tools and caused breaks in metal lines. CMP solved this problem by restoring a flat surface after each critical layer, and it then enabled the damascene method of forming copper interconnects, in which metal is deposited into etched trenches and the excess is polished away. Without CMP, neither modern lithography nor copper wiring would be practical, which is why the process has become indispensable at every advanced node and in most specialty processes.
The CMP slurries and pads covered by this market are the two consumables that make this process work. A CMP slurry is an engineered aqueous dispersion containing abrasive particles, typically colloidal or fumed silica, ceria or alumina, with particle sizes ranging from a few tens to a few hundred nanometres, together with oxidisers such as hydrogen peroxide, complexing agents, corrosion inhibitors, pH buffers, surfactants and selectivity modifiers. Each slurry is formulated for a specific film stack and must deliver a target removal rate on the film being polished, a much lower removal rate on the stop layer, minimal dishing of wide features and minimal erosion of dense arrays, and very low levels of scratches, residual particles and metallic contamination. Slurries are usually delivered as concentrates in high-purity containers, diluted and mixed with oxidiser at the fab, filtered and supplied to the tool through a slurry distribution system.
A CMP pad is a consumable polymer disc, normally based on cast polyurethane, that is mounted on the polishing platen. Hard pads, which are usually closed-cell polyurethane containing hollow polymer microspheres to create pores, provide planarisation efficiency over long distances and are used for most bulk removal steps. Soft pads, which may be based on poromeric polyurethane, felt-like non-woven structures or composite designs, conform more closely to the wafer and are used for final buffing, defect reduction and polishing of fragile or bonded surfaces. Many production pads are stacked structures with a hard top layer and a compliant sub-pad. The pad surface is grooved to distribute slurry and is continuously roughened by a diamond conditioner to maintain consistent texture during use. Pads wear out and are replaced after a defined number of wafers, which, together with the continuous consumption of slurry, makes both products recurring purchases linked directly to wafer output.
The slurry and the pad work as a system rather than as independent products. The pad's hardness, compressibility and surface texture determine how polishing pressure is distributed across the wafer and within individual features, while its pores and grooves determine how fresh slurry reaches the wafer and how debris is carried away. The slurry's chemistry determines which films are softened or dissolved and how fast, and its abrasive particles determine how efficiently the modified surface layer is removed. A slurry that performs well on one pad may perform poorly on another, and the conditioning process that renews the pad surface also affects how the slurry behaves. For this reason, chipmakers and suppliers usually develop and qualify slurry and pad combinations together, and the performance of a CMP step is described by a set of outputs that depend on both products: removal rate, within-wafer and wafer-to-wafer uniformity, planarization efficiency, dishing of wide metal lines, erosion of dense arrays, selectivity between materials, surface roughness and the number of defects such as scratches, residual particles and corrosion spots.
CMP is used throughout the device flow. In front-end-of-line processing, it planarises the oxide fill of shallow trench isolation, polysilicon and gate structures, and the nitride and oxide layers of replacement metal gate processes. In the middle of line, it removes excess tungsten or cobalt after contact and local interconnect fills. In back-end-of-line processing, it is used on every copper damascene level to remove bulk copper, the tantalum-based or cobalt-based barrier liner and part of the interlayer dielectric. Outside the transistor and interconnect flow, CMP is used to polish through-silicon vias and redistribution layers in advanced packaging, to prepare copper and dielectric surfaces for hybrid bonding, and to produce the mirror finish of prime silicon wafers and the epitaxy-ready surfaces of silicon carbide and gallium nitride substrates. Each of these steps uses a dedicated combination of slurry and pad, and a leading-edge logic process now contains dozens of separate CMP operations.
The market is defined as the value of CMP slurries and CMP pads sold to semiconductor manufacturers and to wafer and substrate producers worldwide, measured at the point of first sale by the consumable manufacturer. It includes oxide and STI slurries based on ceria or colloidal silica; copper and barrier slurries; tungsten, cobalt and other metal slurries; specialty slurries for polysilicon, nitride, silicon carbide and gallium nitride; hard polyurethane CMP pads; and soft and specialty CMP pads, including sub-pads sold as part of stacked pad products. Slurries and pads supplied for bare wafer polishing by wafer and substrate makers and for planarisation steps performed by outsourced assembly and test companies are included.
Consumption of CMP slurries and pads is governed by a small number of physical relationships that make the market predictable in structure, even if its level fluctuates with the semiconductor cycle. Slurry is dispensed continuously while each wafer is polished, so slurry use is proportional to the number of wafers polished, the number of steps per wafer and the polishing time of each step. Pads are replaced after a defined number of wafers or hours of use, so pad consumption is proportional to the same activity divided by pad life. Both quantities rise when wafer starts increase, when process flows add steps or when new materials require longer polishing, and both fall when fabs reduce utilisation. Price levels, by contrast, depend on the sophistication of each product: commodity silica slurries for mature steps are priced very differently from engineered ceria or selective slurries for leading-edge steps, and standard hard pads are priced differently from pads designed for specific advanced applications.
The market excludes CMP equipment such as polishers, carrier heads and endpoint systems; pad conditioners and diamond discs; retaining rings; post-CMP cleaning chemistries and brushes; slurry filtration and delivery hardware; and abrasive powders sold as raw materials to slurry formulators, to avoid double counting. Lapping and grinding consumables used in wafer slicing, and polishing products used for optical glass, hard-disk media, display glass or metallurgical sample preparation, are also excluded because they serve different end markets with different specifications. Where a supplier sells an integrated package of slurry, pad and cleaning chemistry, only the value attributable to slurries and pads is included.
The products in this market are distinguished from general industrial abrasives by their purity, consistency and qualification requirements. Trace metal content is controlled at parts-per-billion levels, large particle counts are monitored to prevent scratching, and lot-to-lot variation is held within tight limits because a small change in removal rate or selectivity can change the yield of a fab producing tens of thousands of wafers each month. For this reason, once a slurry or pad is qualified for a specific step at a specific fab, it is rarely changed without a formal requalification, and process-of-record status becomes the main competitive asset of a supplier.
Scope of the Study
This study quantifies the Global CMP Slurries and Pads Market in value terms for the period 2022–2032. Market values are expressed in USD Billion. The years 2022, 2023 and 2024 are treated as historic years, 2025 is the base year, and 2026–2032 is the forecast period. Compound annual growth rates are presented for 2026–2032.
The market is analysed by three segmentations. The Product Type segmentation covers Oxide & STI Slurries (Ceria / Colloidal Silica); Copper & Barrier Slurries; Tungsten, Cobalt & Other Metal Slurries; Specialty Slurries (Poly-Si, Nitride, SiC / GaN); Hard Polyurethane CMP Pads; and Soft & Specialty CMP Pads. The Application / Process Step segmentation covers FEOL (STI, Poly-Si, Gate); MOL / Contact (W, Co); BEOL Interconnect (Cu, Barrier, ILD); Advanced Packaging & Hybrid Bonding (TSV, RDL); and Bare Wafer & Substrate Polishing (Si, SiC, GaN). The End User segmentation covers Foundries; Memory Manufacturers (DRAM, HBM, 3D NAND); Logic & Analog / Power IDMs; and OSATs & Wafer / Substrate Makers. The three segmentations are applied consistently to the global market and to every region and country, so that the same categories can be compared across geographies.
The geographic scope comprises five regions and twenty country-level entries. North America covers the U.S., Canada and Mexico. Europe covers Germany, the U.K., France, Italy, Spain and Rest of Europe. Asia Pacific covers China, India, Japan and Rest of Asia Pacific. Latin America covers Brazil, Argentina and Rest of Latin America. Middle East & Africa covers the UAE, Saudi Arabia, South Africa and Rest of MEA. For each region and country, the study presents values by product type, by application or process step and by end user.
The product type segmentation distinguishes between the chemistries and constructions that reflect distinct technical requirements and supplier capabilities. The application or process step segmentation follows the order in which polishing steps occur in device fabrication, from the front end of the line through the middle of line and the back end of the line to packaging, with substrate polishing treated as a separate stage that precedes device fabrication. The end user segmentation groups buyers by business model rather than by product: foundries manufacture chips designed by others, memory manufacturers produce DRAM, high-bandwidth memory and NAND flash, logic and analog or power integrated device manufacturers design and manufacture their own chips, and the final group combines outsourced assembly and test companies with the wafer and substrate makers that polish silicon, silicon carbide and gallium nitride wafers before shipping them to device makers. Integrated device manufacturers that also offer foundry services are allocated according to the nature of the wafers they process.
The study presents its results in a consistent sequence for every segmentation and geography: values for each year from 2022 to 2032 with the compound annual growth rate for 2026–2032, the share of each category in 2025 and a graphical view of the 2025 distribution. Country entries labelled Rest of Europe, Rest of Asia Pacific, Rest of Latin America and Rest of MEA aggregate the remaining economies in each region and are treated as single entries in the tables, even though some of them include substantial producing countries. Qualitative analysis covers the forces that shape demand and supply over the forecast period, the structure of the value chain, competitive intensity, the regulatory environment in the main producing regions, and the positioning and recent strategic developments of the leading suppliers of CMP slurries and pads.
Demand is allocated to the location where the consumables are used, that is, the location of the fab, assembly site or wafer plant, rather than the location of the supplier's headquarters or production plant. This approach reflects the way CMP consumables are qualified and purchased, since each fab qualifies its own process of record and buys for its own production lines. The study also examines the qualitative factors shaping the market, including drivers, restraints, opportunities and trends, the value chain, competitive forces, the regulatory environment and the competitive positioning of leading suppliers.
Research Objectives
To estimate the value of the global CMP slurries and pads market for 2022–2025 and to forecast its development through 2032, with CAGRs for 2026–2032.
To measure demand for each slurry chemistry and pad category and to explain how node migration, new materials and device architectures change the product mix.
To quantify consumption by process step, from shallow trench isolation and gate polishing through contact, interconnect, packaging and bare wafer polishing, and to identify the steps adding CMP intensity fastest.
To assess how demand differs between foundries, memory manufacturers, logic and analog or power IDMs, and OSATs and wafer or substrate makers.
To analyse regional and country demand in relation to installed and planned fab capacity, government semiconductor programmes and the localisation of consumable supply.
To evaluate supply-side risks, including abrasive and polymer precursor sourcing, export controls and chemical regulation, and their effect on supplier strategy.
To profile the competitive structure of the market by positioning the leading slurry and pad suppliers and tracking their capacity investments, partnerships and portfolio changes since 2022.
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View Subscription PlansOverview of the Research Process
The research process for this study combined structured secondary research, primary interviews with participants across the CMP consumables value chain, and a quantitative model that links consumable demand to semiconductor manufacturing activity. The work was organised in five stages. The first stage defined the market boundary, the product and process taxonomy and the geographic framework, with particular attention to separating slurries and pads from adjacent consumables such as pad conditioners, post-CMP cleans and filtration products. The second stage assembled an evidence base from public and proprietary sources covering wafer capacity, wafer starts by node and device type, CMP step counts, supplier revenues and capacity announcements. The third stage tested and refined that evidence through discussions with suppliers, distributors, equipment makers and process engineers at device manufacturers. The fourth stage built the market estimates through complementary top-down and bottom-up calculations and reconciled them. The fifth stage produced the forecast and subjected the results to internal review for consistency across segments, regions and years.
CMP consumables lend themselves to a model driven by physical activity because consumption is proportional to the number of wafers polished, the number of CMP steps in each process flow, the volume of slurry used per step and the number of wafers processed per pad. These parameters vary by device type, node, wafer size and process step, and they change as new architectures are introduced. The research therefore placed considerable weight on understanding process flows and their evolution, rather than relying only on supplier revenue disclosures, which are often reported at a level that combines CMP products with other electronic materials.
Throughout the process, the study applied a consistent set of definitions. Values are recorded at the first point of sale by the consumable manufacturer, allocated to the country of consumption and expressed in nominal U.S. dollars. Where suppliers report in other currencies, revenues were converted using annual average exchange rates for the relevant year. The segmentation used in the study was fixed at the start of the work and applied uniformly to every geography.
Secondary Research
Secondary research provided the factual foundation for the market model and for the qualitative analysis. Industry association publications were a central source. SEMI publishes data on global semiconductor materials revenue by region and category, equipment billings, and fab capacity and construction through its World Fab Forecast and related services. The World Semiconductor Trade Statistics organisation publishes semiconductor market data and forecasts by product and region. National associations, such as the Semiconductor Industry Association in the U.S., the Japan Electronics and Information Technology Industries Association, the Korea Semiconductor Industry Association, the Taiwan Semiconductor Industry Association and the China Semiconductor Industry Association, provided country-level context on production and investment.
Company filings were used extensively. Annual reports, securities filings, quarterly earnings presentations and investor-day materials of slurry and pad suppliers such as Entegris, Qnity Electronics, Fujifilm, Resonac, Merck KGaA, Fujimi Incorporated, AGC, Anji Microelectronics and Hubei Dinglong were reviewed for segment revenues, product commentary, capacity plans and regional sales. Filings and capital expenditure guidance of device manufacturers, including foundries, memory makers and integrated device manufacturers, were used to track wafer capacity additions, node transitions and utilisation trends, which are the primary determinants of consumable demand.
Government and regulatory sources informed both the capacity outlook and the regulatory analysis. These included documents published under the U.S. CHIPS and Science Act, the European Chips Act and its proposed successor, Japan's semiconductor support programmes, the India Semiconductor Mission and China's industrial policy statements, as well as export-control notices from the U.S. Department of Commerce and China's Ministry of Commerce, and chemical regulation documents from the European Chemicals Agency and the U.S. Environmental Protection Agency. Customs and trade statistics were used to cross-check regional flows of abrasive powders and polishing preparations.
Technical literature formed a further layer of secondary research. Papers presented at conferences such as the International Conference on Planarization and CMP Technology, the IEEE International Electron Devices Meeting, the VLSI Symposium and the Electronic Components and Technology Conference, as well as articles in trade journals covering semiconductor manufacturing and materials, were used to understand step counts, slurry and pad consumption rates and the process changes associated with new architectures. Patent filings by leading suppliers were reviewed to identify emerging chemistries and pad structures. Paid databases covering company financials, trade flows and fab capacity were used to fill gaps and validate figures.
Primary Research
Primary research was used to validate secondary findings, to obtain parameters that are not published, and to capture the views of practitioners on how demand will evolve. Interviews were conducted on a semi-structured basis using discussion guides tailored to each respondent type, and responses were treated as confidential.
On the supply side, respondents included business and product managers, application engineers and regional sales leaders at slurry and pad manufacturers, as well as executives at suppliers of abrasive particles, polyurethane precursors and microspheres. Distributors and logistics providers that handle slurry concentrates and pads in regions where suppliers do not sell directly were also consulted. Equipment makers were interviewed for their view of CMP tool installations and of how new tool architectures affect consumable use.
On the demand side, respondents included CMP process engineers, module owners, purchasing and supplier-quality managers and fab operations managers at foundries, memory manufacturers, logic and analog or power IDMs, outsourced assembly and test companies, and wafer and substrate producers. These respondents provided insight into the number of CMP steps at each node, consumption per wafer, pad life, qualification practices and the criteria used to select and retain suppliers.
The objectives of primary research were to confirm or adjust the step counts and consumption ratios used in the model; to understand the share of each process step and product type in total spending; to assess price levels and price trends by product category and region; to identify capacity additions and process changes that would affect demand in the forecast period; and to test the qualitative drivers, restraints and opportunities identified through desk research. Divergent views were explored through follow-up questions and reconciled against documentary evidence. Primary research was also used to identify emerging applications whose demand is not yet visible in supplier disclosures, such as polishing for backside power delivery, hybrid bonding in memory and new contact metals, and to understand the timing of their introduction at different customers. Interviews with respondents in China, India and other countries where public disclosure is limited were particularly important for estimating demand in those markets.
Market Size Estimation
Market size was estimated through two independent approaches whose results were then triangulated.
The bottom-up approach started from wafer activity. Installed and utilised wafer capacity was compiled by fab, wafer size, device type and technology node, and converted into wafers processed per year. For each combination of device type and node, the number of CMP steps by process stage was estimated, together with average slurry volume per step, average wafers per pad and average selling prices by product category and region. Multiplying these parameters produced consumption values by product type, process step and end user for each fab, which were aggregated to country, region and global totals. Bare wafer and substrate polishing was modelled separately from silicon wafer, silicon carbide and gallium nitride substrate output, and packaging-related demand was modelled from the capacity of through-silicon via, redistribution layer and hybrid bonding lines.
The top-down approach started from supplier revenues. The CMP slurry and pad revenues of the leading suppliers were compiled from company disclosures where available and estimated from segment data, product commentary and primary interviews where not. Revenues from the remaining suppliers were estimated from regional and product-level evidence. The total was then allocated to product types, process steps, end users and regions using customer and shipment information gathered during the research.
Data triangulation reconciled the two approaches with a third set of reference points, including semiconductor materials revenue reported by industry associations, trade data for polishing preparations, and wafer start trends. Where the bottom-up and top-down results differed, the underlying assumptions were reviewed, for example by revisiting the number of CMP steps at a particular node, the pad life assumed for a given application or the price premium of specialised formulations. The final estimates reflect the outcome of this reconciliation and were checked to ensure that segment totals equal the overall market in every year and every geography.
Forecasting Methodology
The forecast was built on the same activity-based structure as the base-year estimate. Future consumption was projected from wafer capacity additions announced or under construction, expected utilisation rates, the migration of output to more advanced nodes and denser memory architectures, and the expected change in CMP steps and consumable intensity per wafer at each node. Price trends by product category were projected from the balance between cost reductions in mature formulations and the premium attached to new chemistries, with consideration of raw-material costs and regional competition.
The factors considered included the pace of gate-all-around and backside power adoption in logic; layer count increases in 3D NAND and stack height in high-bandwidth memory; the adoption of hybrid bonding in logic and memory packaging; the transition of silicon carbide substrates to 200 mm; government programmes supporting new fabs in the U.S., Europe, Japan, India and other countries; the localisation of consumable supply, particularly in China; export controls and trade measures; and chemical regulation affecting formulation choices. The forecast also considered macroeconomic conditions, end-market demand for data centre, smartphone, personal computer, automotive and industrial electronics, and the cyclical behaviour of memory pricing and capacity.
The approach combined time-series analysis of historical demand with scenario testing of key assumptions. Base-case assumptions were tested against alternative paths for wafer starts and node migration to ensure that the resulting growth rates were plausible and internally consistent across product types, process steps, end users and regions. Analyst judgement was applied where structural changes, such as the introduction of a new process step, are not captured by historical trends. The forecast for each region and country was built from the expected capacity and process mix of the fabs, assembly sites and wafer plants located there, and was then checked against national semiconductor programmes, announced investment schedules and the views of local respondents. Regional totals were reconciled with the global forecast so that the sum of regions equals the global market in every year, and the sum of segments equals the total for each region and country. Growth rates for individual segments were reviewed for consistency with the drivers identified for each product type, process step and end user, so that, for example, faster growth in packaging-related polishing is reflected in the products used in those steps.
Base Year and Forecast Period
The base year of the study is 2025, the most recent full year for which supplier disclosures, industry statistics and primary research inputs were available. Historic data are presented for 2022, 2023 and 2024, a period that includes a cyclical peak in 2022, a downturn in 2023 led by memory and a recovery in 2024. The forecast period covers 2026–2032, and compound annual growth rates are calculated for 2026–2032. All values are expressed in USD Billion in nominal terms. Shares are calculated on 2025 values, and absolute growth is measured between 2025 and 2032. The choice of 2025 as the base year means that the estimates incorporate the recovery in memory demand that began in 2024 and the start of volume production at the first gate-all-around nodes, as well as the early stages of capacity ramp-up at new fabs in the U.S. and Japan. The historic period allows the cyclical behaviour of the market to be observed through a full downturn and recovery, which informs the treatment of cyclicality in the forecast.
The forecast period ends in 2032, by which time the projects currently under construction or announced are expected to have reached volume production and the next node transitions after gate-all-around and backside power are expected to be under way. Values are not adjusted for inflation, and changes in exchange rates between the U.S. dollar and the currencies in which suppliers and customers operate, such as the Japanese yen, the New Taiwan dollar, the Korean won, the Chinese renminbi and the euro, can affect reported values independently of changes in physical consumption.
Assumptions and Limitations
The forecast assumes that announced fab projects proceed broadly in line with current public schedules, allowing for the delays that have historically affected large greenfield projects. It assumes that no major disruption, such as a prolonged conflict affecting a principal manufacturing region, a pandemic-scale shutdown or a sustained interruption of critical raw-material supply, occurs during the forecast period. It assumes that existing export-control regimes remain in place in broadly their current form and that trade measures do not prevent consumables from reaching fabs that have qualified them. It assumes that exchange rates remain within ranges consistent with recent experience and that pricing for mature consumables declines gradually while new chemistries carry a premium.
Base Year
2025
Historical Period
2022 – 2024
Forecast Period
2026 – 2032
Primary Interviews
150+
Historical data (2022–2025) and forecast period (2025–2032)
Our research process spans primary interviews with industry stakeholders combined with comprehensive secondary data analysis, validated through triangulation across multiple independent sources.
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The CMP slurries and pads market is moderately consolidated. A small group of suppliers with global manufacturing networks, broad product portfolios and long qualification histories at leading foundries and memory makers accounts for most of the market's value, while a larger number of regional and specialised suppliers compete in particular chemistries, pad types or customer groups. Concentration is higher in pads than in slurries: the pad market is led by two global suppliers with long-established brands, while the slurry market has more competitors because chemistries are more varied and each process step can be served by a different supplier. Regional structures also differ, with Chinese chipmakers increasingly supplied by domestic companies and Korean memory makers supported by domestic slurry and pad producers alongside international suppliers.
Competition is based mainly on technical performance rather than price. Customers select consumables according to removal rate, selectivity, planarization efficiency, dishing and erosion control, defectivity, pad life and lot-to-lot consistency, and they weigh these factors against the cost of ownership of the CMP step rather than the price per litre or per pad alone. Because a consumable must be qualified for a specific step at a specific fab, competition is concentrated at node transitions and new fab qualifications, when chipmakers evaluate alternatives. Between these points, incumbent suppliers are protected by the cost and risk of requalification, but they face continuous price pressure on mature products.
The competitive landscape has changed significantly since 2022. Entegris completed its acquisition of CMC Materials in July 2022, combining the leading independent CMP slurry and pad supplier with Entegris's filtration, cleaning chemistry and specialty materials businesses. DuPont separated its electronics business, including its CMP pad and slurry franchise, into Qnity Electronics in November 2025. In South Korea, SK enpulse sold its CMP pad business to the private equity firm Hahn & Co. in a transaction completed in April 2025 and agreed later that year to sell its CMP slurry business. In China, Anji Microelectronics and Hubei Dinglong have grown rapidly with support from domestic chipmakers. Across the industry, suppliers have invested in regional production close to new fabs in the U.S., Japan and Europe, and they have sought to secure raw-material supply following China's 2025 export-control actions on rare earths.
Key Player Positioning
The leading suppliers of CMP slurries and pads can be grouped into leaders, challengers and niche players according to the breadth of their portfolios, their presence at major customers and regions, and their technological capabilities.
The leaders are Entegris, Qnity Electronics, Fujifilm, Resonac and Merck KGaA. Entegris holds the broadest portfolio in the market, covering slurries for oxide, tungsten, copper, barrier and wide-bandgap materials, pads, post-CMP cleans, pad conditioners and slurry filtration, with manufacturing in the U.S., Taiwan, South Korea and other locations, including its large Kaohsiung facility. Qnity Electronics is the leading pad supplier, with established brands such as IC1000 and Ikonic, and it also supplies slurries and post-CMP cleans; its long-term supply agreement with SK hynix and its new Newark facility reinforce its position. Fujifilm is a leading supplier of copper and barrier slurries and post-CMP cleaners, with slurry production in the U.S., Taiwan, South Korea and Japan and new capacity in Belgium. Resonac is a leading supplier of ceria slurries for oxide and STI polishing, with deep expertise in ceria particle technology, and Merck KGaA supplies dielectric, tungsten and copper slurries through its Versum Materials heritage and has broad relationships with leading chipmakers.
The challengers are Fujimi Incorporated, AGC, Anji Microelectronics and Hubei Dinglong. Fujimi Incorporated is the leading supplier of silicon wafer polishing slurries and a significant supplier of device CMP slurries, with production in Japan, Taiwan, the U.S. and other locations, and its position in wafer polishing gives it a strong base from which to expand in device applications. AGC supplies ceria-based slurries and draws on its expertise in glass and ceramic materials. Anji Microelectronics is the leading Chinese slurry supplier, with rapidly growing revenue and a broad range of slurries for Chinese foundries and memory makers, and it is developing products for advanced packaging. Hubei Dinglong is the leading Chinese pad supplier, with vertically integrated production of pad raw materials and expanding capacity. Both Chinese companies are challengers because of their strong domestic positions and growth, although their presence outside China remains limited.
The niche players are Soulbrain, KC Tech and Fujibo Holdings. Soulbrain and KC Tech are Korean suppliers of CMP slurries, particularly ceria-based products for memory applications, with strong relationships with Korean memory makers but more limited international presence. Fujibo Holdings is a Japanese producer of polishing pads, particularly soft pads for silicon wafer and specialised polishing, with a strong position in its niche. These companies compete effectively in specific product categories and customer groups but lack the breadth of portfolio or global presence of the leaders.
Competitor Dashboard
The competitor dashboard rates each company on four dimensions: the breadth and depth of its CMP slurry and pad product portfolio, its manufacturing and customer presence across regions, its strategic alliances with customers, equipment makers and partners, and its experience in the CMP consumables industry. The ratings are consistent with the positioning of each company as a leader, challenger or niche player.
Entegris and Qnity Electronics receive the highest ratings for product portfolio and regional presence because of their comprehensive offerings across slurries, pads and related products and their manufacturing and support networks in all major regions. Fujifilm and Merck KGaA have very broad regional presence, with production and technical support close to major customers in Asia, North America and Europe. Resonac and Fujimi Incorporated have strong positions in their core categories and long experience. Anji Microelectronics has a broad slurry portfolio but a regional presence concentrated in China, while Hubei Dinglong's more recent entry into the market is reflected in its medium rating for industry experience. The Korean and Japanese niche players have long experience but narrower portfolios and fewer strategic alliances outside their home markets.
The bargaining power of buyers is rated High. Demand for CMP slurries and pads is concentrated in a small number of large foundries and memory makers, which together account for most leading-edge consumption and negotiate global supply agreements covering many fabs and process steps. These buyers have deep technical knowledge of CMP, run their own qualification programmes and can evaluate competing consumables on their own tools, so they understand the performance and cost structure of each product in detail. They routinely require annual price reductions on mature products, insist on multiple qualified suppliers for critical steps, and expect suppliers to fund local inventory, technical support and quality investigations. Large buyers also influence the direction of product development by sharing roadmaps selectively and by awarding new steps to the supplier whose formulation performs best in their flow. Buyer power is tempered by the importance of consumables to yield, since a buyer will rarely switch a qualified product purely to obtain a lower price if the change risks a yield loss, and by the fact that consumables account for a small share of total wafer cost. Smaller customers, such as specialty fabs, research facilities and outsourced assembly sites, have less bargaining power, but their purchasing volumes are also smaller, so the overall balance remains strongly in favour of buyers.
The power of buyers is also expressed through their influence on technology choices. When a large foundry or memory maker decides to adopt a new architecture, such as gate-all-around transistors, backside power or hybrid bonding, it sets the specifications that consumables must meet and chooses which suppliers to involve in development. Suppliers that are excluded from early development work have little chance of winning the resulting steps, which gives buyers considerable leverage over supplier investment priorities. Buyers also shape the regional footprint of the industry by asking suppliers to build local production close to new fabs, often without committing to volumes in advance. In China, buyer power has an additional dimension, because domestic chipmakers can choose between international suppliers and fast-growing local suppliers that are supported by national policy, and they use that choice to negotiate both price and supply security. The only buyers with limited power are small specialty fabs and research facilities, which depend on suppliers and distributors for technical support and often accept standard products and prices.
The bargaining power of suppliers is rated Medium. Slurry and pad makers depend on a few producers for critical inputs, including ceria abrasives, high-purity colloidal silica, polyurethane prepolymers and curatives, and hollow microspheres, and changing a source requires lengthy customer requalification. The concentration of rare-earth processing in China adds a policy dimension to supplier power, as export-control actions taken in 2025 demonstrated. However, several factors limit the power of raw-material suppliers. Many of the leading consumables makers synthesise their own abrasive particles or have long-term agreements with abrasive producers, and some produce key polymer components in-house. For many additives, such as complexing agents, inhibitors and buffers, multiple sources of electronic-grade material exist. Raw materials also represent only part of the value of a finished slurry or pad, with most value created in formulation and manufacturing. Upstream suppliers therefore hold meaningful leverage only for specific high-purity or specialised inputs, and that leverage is being reduced by diversification programmes launched by slurry makers since 2025.
Supplier power differs between slurry and pad inputs. For slurries, the most powerful upstream suppliers are the producers of ultra-high-purity colloidal silica and of the fine ceria particles used in leading-edge oxide slurries, because their products are difficult to replicate and changing to another source requires lengthy requalification. For pads, the producers of hollow polymer microspheres and of specialised polyurethane components hold a similar position, since there are few alternative sources and pad properties are sensitive to small changes in these inputs. Equipment makers can also be regarded as influential suppliers to the market, because consumables must be designed for their tools and because they control access to new tool platforms during development. Their influence is not exercised through price but through the technical direction of the CMP process, which affects which consumables succeed. Overall, supplier power is real but bounded, and it is expected to decline gradually as slurry and pad makers diversify their sources and integrate backward over the forecast period.
The threat of new entrants is rated Medium. Barriers to entry in this market are substantial. A new entrant must develop formulations or pad structures that meet demanding performance targets, build manufacturing capability with semiconductor-grade purity and consistency, establish application laboratories with production CMP tools, and then pass qualification at customers that are reluctant to change suppliers on established steps. Incumbents hold large patent portfolios on abrasives, additives and pad structures, which makes it difficult to develop competitive products without infringement risk, and they have long records of process-of-record positions that new entrants lack. Despite these barriers, the past decade has shown that entry is possible where policy support and customer willingness coincide. In China, Anji Microelectronics has built a large slurry business and Hubei Dinglong has become a significant pad producer, helped by national policies that encourage domestic chipmakers to qualify local materials and by customers' desire to reduce dependence on imports subject to export-control risk. Similar localisation ambitions in South Korea, India and other countries could support further entrants. The threat is therefore moderate overall: low for leading-edge steps at global chipmakers, but higher for mature-node steps and in markets where governments actively promote domestic supply.
The economics of entry also deter newcomers outside policy-supported markets. Building a slurry plant with semiconductor-grade quality systems and an application laboratory with current-generation CMP tools requires substantial investment before any revenue is earned, and the first revenues usually come from mature steps where prices are lowest. A new entrant must then sustain several years of qualification work before it can compete for advanced steps, during which incumbents continue to develop new products. Customers' preference for suppliers with global manufacturing networks and long track records further favours established companies. Entry by acquisition is more common than greenfield entry, as shown by the purchase of CMP businesses by private equity investors and by smaller chemical companies, which buy existing qualifications and customer relationships rather than building them. In India, where new fabs and assembly plants are being established, local chemical companies may in time seek to supply consumables for mature steps, but the near-term threat to incumbents there is limited.
The threat of substitutes is rated Low. There is no practical alternative to chemical mechanical planarization for achieving the global flatness required by multilayer interconnects, damascene metal patterning, shallow trench isolation and hybrid bonding. Alternative planarization approaches, such as etch-back, spin-on dielectrics with reflow, electrochemical polishing and plasma-based planarization, have been studied and are used in limited applications, but none can replace CMP across the range of films and structures found in modern devices. Within CMP itself, there are variants that change consumable demand rather than eliminate it. Fixed-abrasive pads, in which abrasive particles are embedded in the pad and used with abrasive-free solutions, have found niche use, and abrasive-free or low-abrasive slurries are used for certain copper and barrier steps; both still require CMP pads and chemical formulations supplied by the same companies. Process changes that reduce the number of CMP steps, such as selective deposition or direct patterning approaches, are being researched but are not expected to reduce CMP intensity during the forecast period, since the overall direction of device architecture is toward more planarization rather than less.
The low threat of substitutes is reinforced by the direction of technology. Gate-all-around transistors, backside power delivery, 3D NAND with more layers, bonded memory architectures and hybrid bonding all depend on CMP to create the flat, clean surfaces they require, and none of the alternative techniques under research offers the combination of global planarity, low defectivity and throughput that CMP provides. Even in packaging, where some steps can be performed by grinding or fly-cutting, the move to finer pitches and hybrid bonding is increasing rather than reducing reliance on CMP. Substitution within the market, such as the replacement of one abrasive or pad type by another, is a feature of competition between suppliers rather than a threat to the market itself, since the substitute products are also CMP slurries and pads. The main long-term risk would be a fundamental change in device manufacturing that eliminates the need for planarization, and no such change is expected within the forecast period.
Competitive rivalry is rated High. The leading suppliers compete intensively for process-of-record positions at each node transition, when chipmakers re-evaluate consumables for new steps and occasionally for existing ones. Rivalry is focused on performance, including removal rate, selectivity, dishing and erosion, defectivity and pad life, and on the ability to support customers technically and to supply reliably from local sites. Price competition is strongest in mature categories such as standard oxide slurries, tungsten slurries and conventional hard pads, where several qualified products exist and customers use dual sourcing to obtain concessions. The competitive set is also changing. Portfolio consolidation, notably Entegris's acquisition of CMC Materials in 2022, created a supplier with a complete slurry, pad and cleaning portfolio, while DuPont's separation of its electronics business into Qnity Electronics in November 2025 created a focused electronics materials competitor. In South Korea, SK enpulse sold its CMP pad business to Hahn & Co. in a transaction agreed in December 2024 and completed in April 2025. In China, domestic suppliers are competing aggressively on price and service to displace imported products. Capacity investments by several suppliers in the same regions, such as Japan and the U.S., add further competitive pressure as new plants seek volume to fill their lines.
Rivalry also takes the form of competition for talent, laboratory capacity and customer attention. Leading suppliers maintain application laboratories close to major customers in Taiwan, South Korea, Japan, the U.S. and China, staffed by engineers who work alongside customer teams, and the quality of this support is often decisive in winning new steps. Suppliers compete on speed of response to quality excursions and on the ability to provide consistent product from several sites, which has become more important as customers diversify their own manufacturing footprints. Intellectual property is another field of competition, with suppliers filing patents on abrasives, additives and pad structures and, on occasion, enforcing them through litigation. In China, rivalry is particularly intense because domestic suppliers are expanding rapidly with policy support and are willing to accept lower margins to win qualifications, while international suppliers seek to defend their positions at advanced steps. Rivalry is expected to remain high throughout the forecast period, but it is likely to be most intense at node transitions and in the new applications created by hybrid bonding and backside power.
Taken together, the five forces describe a market in which established suppliers enjoy protection from substitutes and from easy entry at the leading edge, but in which powerful customers and active rivals limit pricing freedom. Profitability depends on maintaining a stream of new formulations and pad designs that win steps at new nodes, because these products carry price premiums that offset the steady erosion of mature product prices. The forces also differ by region, with buyer power and rivalry particularly strong in China, where domestic suppliers and policy support have changed the competitive balance, and with supplier power most visible in ceria-based slurry chemistries. Over the forecast period, the balance of forces is expected to remain broadly stable, with buyer power and rivalry staying high, supplier power easing slightly as raw-material sources diversify, and the threat of new entrants remaining concentrated in policy-supported markets rather than at the leading edge of the global industry.
Bargaining Power of Buyers: High; A few large foundries and memory makers dominate demand, require annual price reductions and dual sourcing.
Bargaining Power of Suppliers: Medium; Ceria, high-purity silica and pad precursors are concentrated, but in-house synthesis and diversification limit leverage.
Threat of New Entrants: Medium; Qualification, purity and patent barriers are high, but policy-backed entrants have succeeded in China.
Threat of Substitutes: Low; No alternative process delivers the global planarity required for interconnects, isolation and hybrid bonding.
Competitive Rivalry: High; Suppliers compete for process-of-record positions at each node, with price pressure on mature products.
Market estimates by geography (2032)
InsightAsia Pacific leads with $4.72B by 2032, while Middle East & Africa is projected to grow fastest at a 7.0% CAGR.
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View Subscription Plans| REGION | 2022 | 2025 | 2032 | CAGR | SHARE |
|---|---|---|---|---|---|
| North America | $510.40M | $667.20M | $992.30M | 6.9% | 15% |
| Europe | $279.80M | $357.20M | $520.60M | 6.4% | 8% |
| Asia Pacific | $2.51B | $3.31B | $4.72B | 6.5% | 73% |
| Latin America | $31.70M | $40.40M | $58.10M | 6.2% | 1% |
| Middle East & Africa | $83.90M | $110.30M | $165.60M | 7.0% | 3% |
| Total | $3.41B | $4.49B | $6.45B | 6.6% | 100% |
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View Subscription PlansTotal Market Size
$6.45B
| APPLICATION | REVENUE ($B) | GROWTH RATE | MARKET PENETRATION |
|---|---|---|---|
| Oxide & STI Slurries (Ceria / Colloidal Silica) | $1.67B | 5.9% | 26% |
| Hard Polyurethane CMP Pads | $1.45B | 6.4% | 22% |
| Copper & Barrier Slurries | $1.14B | 6.9% | 18% |
| Tungsten, Cobalt & Other Metal Slurries | $786.80M | 4.9% | 12% |
| Soft & Specialty CMP Pads | $772.60M | 7.7% | 12% |
| Specialty Slurries (Poly-Si, Nitride, SiC / GaN) | $639.80M | 9.8% | 10% |
* Revenue projections based on 2025 estimates. Growth rates represent CAGR 2024–2030. Market penetration indicates current adoption rate within addressable market segments.
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Analytical insights on CMP Slurries and Pads Market covering market dynamics, competitive landscape, and strategic outlook.
The CMP Slurries and Pads Market market is projected to reach $6.45B by 2032, growing at 6.6% CAGR. The Oxide & STI Slurries (Ceria / Colloidal Silica) segment holds the largest share.
Demand for CMP slurries and pads is shaped by three layers of influence. The first is the volume of wafers processed worldwide, which follows end-market demand for semiconductors and the capacity decisions of chipmakers. The second is CMP intensity, meaning the number of planarization steps per wafer and the quantity and value of consumables used in each step, which rises as device architectures become more three-dimensional and as new materials enter the process flow. The third is the supply environment, including access to abrasives and polymer precursors, trade and export-control regimes, chemical regulation and the competitive behaviour of suppliers and customers.
These layers do not move together. In 2023, wafer volume fell sharply while CMP intensity at leading-edge nodes continued to rise, and supplier revenues fell with volume. Since 2024, both volume and intensity have contributed to growth, but supply-side conditions have become more uncertain as export controls on critical minerals and chemical regulation have tightened. The analysis that follows first scores the main growth factors over three forecast windows and then examines the drivers, restraints, opportunities and trends that will determine how the market develops through 2032. Each factor is assessed on its own terms, with reference to the product types, process steps and customer groups it affects most.
Market Growth Factor Analysis
The growth factors considered in this assessment comprise five macro factors, which arise from the wider economic, policy and resource environment, and five micro factors, which arise from technology, customer and supplier behaviour within the semiconductor industry. Each factor is classified by the direction of its impact on the market and is given a score from 0 to 10 for three forecast windows, 2026–2027, 2028–2030 and 2031–2032, where a higher score indicates a stronger influence on market development in that window. The scores are analyst assessments based on the secondary and primary research conducted for this study and are intended to show the relative strength and timing of each factor rather than a quantified contribution to market value.
Among the macro factors, AI and data-centre demand carries the highest scores in the early forecast windows. Accelerators, high-bandwidth memory and the networking and power devices around them are produced on the most CMP-intensive processes available, and their volumes are setting the pace of capacity additions at leading foundries and memory makers. The score eases slightly in 2031–2032 because the investment cycle is expected to mature and because other end markets, such as automotive and industrial electronics, will account for a larger share of incremental wafer demand by then. Government incentives score highly through 2030 because projects funded under the U.S. CHIPS and Science Act, the European Chips Act, Japan's support for TSMC's Kumamoto fabs and Rapidus, and the India Semiconductor Mission are scheduled to enter production during that window, after which their effect on new demand tapers.
The two inhibiting macro factors, export controls and critical-mineral concentration, are scored highest in 2026–2027, when the suspension of China's October 2025 rare-earth measures expires in November 2026 and when the scope of U.S. Section 232 semiconductor tariffs is expected to be clarified. Their scores decline later as suppliers complete the qualification of alternative abrasive sources and as regional supply chains for consumables mature. Chemical and environmental regulation is classified as steady because it is more likely to change formulations and compliance costs than to reduce consumption, but its score rises over time as the European Union's PFAS restriction is expected to move from proposal to application and as water reuse requirements tighten around large fab clusters.
Among the micro factors, CMP step count at advanced logic nodes and memory layer counts are the most durable promoting influences, since each new node or memory generation adds polishing operations. Hybrid bonding and advanced packaging adoption is scored lower in 2026–2027 because high-bandwidth memory makers have deferred hybrid bonding to later stack generations, but it rises to the highest micro score in 2031–2032 as logic chiplet stacking and memory bonding reach volume. Customer concentration exerts a constant inhibiting influence on pricing throughout the period. Domestic supplier substitution in China is classified as steady because it shifts share between suppliers rather than changing total demand, although it intensifies price competition in the Chinese market.
Rising CMP Intensity at Gate-All-Around and Backside Power Nodes
The most direct driver of consumable demand is the increase in the number and complexity of polishing steps that each advanced logic wafer passes through. Moving from FinFET transistors to gate-all-around nanosheet transistors changes the front end of the process substantially. A nanosheet flow builds a stack of alternating silicon and silicon-germanium layers, patterns it into fins, forms a sacrificial polysilicon gate, adds inner spacers, replaces the sacrificial gate with a metal gate after the channels are released, and then caps the gate with a dielectric so that contacts can be self-aligned. Several of these stages require a planarization step that must stop on a thin layer with very little margin, such as removing polysilicon overburden while stopping on a nitride hard mask, opening the top of the dummy gate without damaging the surrounding spacer, or planarizing the replacement metal gate without dishing the gate recess. Compared with the FinFET nodes they replace, these flows add front-end and middle-of-line CMP operations, and they demand slurries whose selectivity between polysilicon, nitride, oxide and metal films is tuned more tightly than before.
TSMC moved its N2 node, its first nanosheet process, into volume production in late 2025, and Samsung began mass production of its first-generation SF2 process in the same year. Intel's 18A process, which combines nanosheet transistors with backside power delivery, began high-volume output in Arizona in 2025 and supplied the Core Ultra processors that Intel launched in January 2026. Rapidus is preparing its own 2 nm nanosheet process in Hokkaido. With every leading logic producer now on, or moving to, a gate-all-around architecture, the additional steps are being written into the process of record at the fabs that consume the largest volumes of advanced consumables, and they will be carried forward into the A16, A14 and equivalent nodes that follow.
Backside power delivery is a further structural change, and it may prove to be the largest single addition to CMP demand at the leading edge during the forecast period. In a conventional chip, power and signal wiring share the same interconnect stack above the transistors, and the power lines take up routing space and cause voltage losses as current travels down through many layers. With backside power, the device wafer is bonded face down to a carrier wafer, the original silicon substrate is thinned away until the transistors' contacts are within reach, and a separate power network is built on the newly exposed back surface. The thinning sequence relies on grinding followed by one or more CMP steps that must end precisely at an etch stop layer or at the bottom of nano-scale through-silicon vias, with uniformity across the full 300 mm wafer measured in nanometres. The backside network itself consists of copper or other metal layers, each of which needs bulk metal, barrier and dielectric polishing in the same way as a front-side interconnect level.
The wafer-to-wafer bonding step that attaches the device wafer to the carrier also depends on flat, clean dielectric surfaces, so a planarization step is required before bonding as well as after thinning. In effect, backside power adds a bonding interface, a substrate removal sequence and a second, shorter interconnect stack to every wafer that uses it. Intel's PowerVia implementation is already in production on 18A, TSMC has scheduled its A16 node with its Super Power Rail backside contact scheme for production in the second half of 2026, and Samsung has disclosed backside power plans for its own 2 nm-class roadmap. As these nodes ramp, the number of CMP steps per wafer at the leading edge will rise by a margin that front-end changes alone have not produced in recent node transitions.
Above the transistors, the interconnect stack of high-performance processors is also becoming taller and more varied in its materials. AI accelerators and server processors use more metal layers than mobile system-on-chip designs because they must route very wide data buses between compute units, cache and memory interfaces, and because they must distribute large currents with limited voltage drop. Each additional copper level adds a set of copper, barrier and dielectric CMP steps, so a shift in a foundry's output toward large AI and data-centre chips raises the consumable content of an average wafer even if the node stays the same. At the tightest pitches, chipmakers are introducing alternative conductors. Molybdenum and ruthenium are being adopted or evaluated for contacts and lower-level vias because they maintain lower resistance than copper or tungsten in very narrow features and can be deposited without thick barrier layers. Their introduction requires new slurry chemistries, since molybdenum is easily oxidised and dissolved and needs strong corrosion control, while ruthenium is chemically inert and needs aggressive oxidisers to achieve a useful removal rate.
Equipment makers have prepared the ground for this change; Lam Research introduced a molybdenum atomic layer deposition system aimed at advanced contacts and memory wordlines in February 2025. Every new metal adds a qualification cycle and, usually, a period in which both legacy and new chemistries are consumed in parallel while customers validate the new process across product lines. Barrier and liner materials are changing at the same time, with thinner tantalum-based barriers and cobalt or ruthenium liners replacing thicker legacy films, which requires barrier slurries to be reformulated to remove the new stacks without attacking copper or fragile low-k dielectrics. Taken together, the front-side and backside changes mean that the interconnect is no longer a single stack polished in a repeated sequence, but a set of distinct structures with different materials and tolerances, each requiring its own consumable set. This multiplies the number of slurry and pad products that a leading-edge fab must qualify and keep in stock.
The effect of these changes is already visible in supplier results and statements. Entegris reported that sales of its CMP slurries and pads rose by almost 20% year on year in the first quarter of 2025, a period in which its total company sales were broadly flat, and it attributed that growth to demand from advanced logic and packaging. When Qnity opened its Newark, Delaware facility in March 2026, it explained the investment by noting that AI chip fabrication requires more CMP steps per wafer at the most advanced nodes, describing this as a source of major growth potential for CMP materials. The product types most affected are Copper & Barrier Slurries, which gain from taller front-side stacks and new backside levels, and the Specialty Slurries used for polysilicon and nitride steps in gate-all-around flows, together with the Hard Polyurethane CMP Pads used for most bulk removal and the soft pads used for the final polish before bonding. By process step, the change raises demand in FEOL, MOL and BEOL polishing at the same time, and through the carrier bonding step it also draws on techniques normally associated with advanced packaging.
By customer group, demand is concentrated in Foundries and in the leading-edge logic operations of integrated device manufacturers. Because consumable use per wafer rises at each node rather than staying constant, this driver adds to market value even in years when total wafer starts grow slowly, and it shifts the market mix toward higher-value formulations whose prices reflect the difficulty of meeting nanometre-level stop and dishing requirements. Mature nodes are not affected in the same way, but they continue to supply a stable base of demand on which the leading-edge increments are layered, so the overall effect is a gradual rise in average consumable value per wafer across the industry.
Memory Capacity Additions for AI Workloads in HBM, DRAM and 3D NAND
Memory has become the second engine of CMP demand, and its contribution is closely linked to the build-out of AI infrastructure. Large AI models require very high memory bandwidth close to the processor, which is supplied by high-bandwidth memory stacks placed alongside accelerators on a silicon interposer, and they also increase demand for high-capacity server DRAM and for solid-state storage in data centres, where training data, model checkpoints and inference caches are held. The financial scale of this shift is evident in industry statistics. In its forecast published on 2 June 2026, the World Semiconductor Trade Statistics organisation projected that the global semiconductor market would reach about USD 1.51 trillion in 2026, almost double the 2025 level, with memory sales more than tripling and memory becoming the dominant source of growth. Much of that increase reflects higher memory prices rather than higher wafer volume, which is an important distinction for CMP consumables, since slurries and pads are consumed per wafer polished rather than per dollar of chip revenue. A sharp rise in memory prices therefore overstates the immediate effect on consumable demand.
Even so, the price environment has given memory makers the cash flow and the confidence to add wafer capacity, to accelerate their move to denser process generations and to convert existing DRAM lines to HBM production, and all three of these responses raise CMP consumption. Memory makers are also building new fabs and expanding existing ones in South Korea, the U.S., Japan and Singapore, which will add to wafer starts as they come online during the forecast period. The combination of more wafers and more polishing steps per wafer makes memory the customer group whose consumable purchases are most sensitive to the AI investment cycle. The timing of memory capacity additions also matters. Memory makers held back new fab construction during the 2023 downturn and resumed it as prices recovered, so a substantial part of the capacity under construction in 2025 and 2026 will start production during the early and middle years of the forecast period, when the consumable demand associated with qualification and ramp-up is highest.
High-bandwidth memory is particularly CMP-intensive because of the way it is built. Each HBM stack contains a logic base die and up to twelve or sixteen DRAM core dies, all connected vertically by thousands of through-silicon vias. Producing these dies requires etching and filling the vias with copper, polishing the front-side overburden, thinning each wafer from the back until the via tips are exposed, and polishing the back surface so that the via ends are clean, level and free of copper contamination. The dies are then stacked and bonded, and the bonding surfaces must meet tight flatness requirements whether thermo-compression bonding or hybrid bonding is used. In March 2026, industry discussions reported by TrendForce indicated that the HBM package thickness limit, set at 775 micrometres for HBM4, could be relaxed to roughly 825 to 900 micrometres for future 20-high stacks, a change that would allow thermo-compression bonding to remain in use for longer before hybrid bonding becomes necessary. Either path, however, requires backside via reveal polishing on every DRAM die in the stack, so taller stacks translate directly into more CMP passes per finished memory product.
In addition, HBM consumes considerably more wafer area than conventional DRAM for the same number of bits, because its dies are larger and include the via arrays and test structures needed for stacking, and because stacking yields reduce the number of usable dies per wafer. For a given volume of memory bits supplied to AI systems, therefore, more wafers must be processed and more of them must be polished on both sides. The transition from HBM3E to HBM4, which uses a base die manufactured on a foundry logic process, also links memory demand to foundry CMP demand, since the base dies are produced with logic-style front-end and interconnect polishing.
Conventional DRAM is adding CMP steps as it moves to finer nodes. Shallow trench isolation, buried word lines, bit line contacts, bit lines and the tall cylindrical capacitors of DRAM cells each require planarization, and the oxide, nitride and polysilicon films involved are among the largest consumers of ceria and silica slurries in the industry. As DRAM makers move through successive generations of the 10 nm class, cell dimensions shrink and aspect ratios rise, which tightens the uniformity and defect requirements for each polishing step and encourages a shift to higher-performance formulations. Looking further ahead, memory makers are developing vertical channel transistor and three-dimensional DRAM architectures for introduction toward the end of the decade. These designs borrow many of the stacking and bonding techniques used in 3D NAND and in HBM, including separate wafers for the memory array and the peripheral circuitry, and process engineers expect them to increase planarization requirements further. The DRAM market is also affected by the conversion of capacity to HBM: each wafer diverted to HBM production goes through more CMP steps than a standard DRAM wafer, so the mix shift within DRAM fabs raises consumable use even when total DRAM wafer starts are stable.
Server DRAM modules with higher capacities, driven by AI inference and general-purpose computing, add to wafer demand at the same time. DRAM fabs are also a setting in which ceria and silica slurry consumption is heavily concentrated, since cell isolation and capacitor support structures involve thick oxide and nitride films that are removed and planarized several times in each flow. Because memory makers typically qualify consumables across all of their fabs at once, a change in DRAM process generation tends to shift purchases for a whole company within a short period, so memory demand for new formulations arrives in steps rather than gradually.
Hybrid Bonding and Advanced Packaging Planarization
Hybrid bonding joins two chips or wafers by bringing copper pads and the surrounding dielectric into direct contact and then annealing the pair, so that the dielectric surfaces bond first at room temperature and the copper pads then expand and fuse during the anneal. It removes the solder micro-bumps used in conventional die stacking and allows interconnect pitches of a few micrometres, with far higher connection density, shorter signal paths, lower power consumption and better heat transfer than bump-based stacking. The technique depends entirely on surface preparation. The dielectric, usually silicon oxide or silicon carbon nitride, must be flat and smooth at the sub-nanometre level so that the two surfaces can bond across the whole interface. The copper pads must be recessed below the dielectric by a precisely controlled few nanometres, enough to avoid preventing dielectric contact but not so much that the copper fails to close the gap during annealing. The surface must also be essentially free of particles and contamination, because a single particle can create a void that prevents bonding over an area many times its own size.
CMP is the process that produces this surface, and industry analyses published in 2025 and 2026, including work by Counterpoint Research, have described it as the step that most directly determines hybrid bonding yield, interconnect resistance and reliability. This elevates the value of the consumables used in bonding preparation well above that of conventional packaging consumables, and it changes the profile of the customers who buy them, since bonding is performed in foundry packaging operations, at outsourced assembly companies and increasingly in memory fabs. The requirements also extend to the dielectric itself, since some bonding schemes use silicon carbon nitride or other films chosen for their bonding strength and diffusion barrier properties, and these films polish differently from conventional oxides. Consumable suppliers must therefore understand the full bonding process, not only the polishing step.
Adoption is advancing in logic first, where the benefits for chiplet-based processors are clearest. At its 2026 North American Technology Symposium, TSMC described a roadmap for its SoIC hybrid bonding platform that moved from a 9 micrometre bond pitch in 2023 to 6 micrometres in 2025 and targets 4.5 micrometres by 2029, with a second-generation platform adding face-to-face bonding. Intel began shipping Foveros Direct hybrid bonding in its Clearwater Forest server processor in the first half of 2026, and AMD has used hybrid bonding in volume since its first 3D V-Cache products. TSMC is building out its advanced packaging campus in Chiayi as its largest packaging site, and both NVIDIA and Amazon Web Services were reported in 2026 to be planning to use SoIC in future products. Memory adoption is slower and less certain. In July 2026, TrendForce reported that Samsung and SK hynix were reconsidering their hybrid bonding timelines for HBM, that both had continued to use thermo-compression bonding for HBM4, and that a 16-high HBM4E product was the earliest likely adoption point, partly because relaxed package thickness limits and new thermal solutions have reduced the urgency of the transition.
SK hynix has nevertheless purchased an integrated hybrid bonding system that combines Applied Materials' CMP and plasma treatment with Besi's die bonder, which signals that memory makers are building production capability so that they can move when their product roadmaps require it. Wafer-to-wafer hybrid bonding is already in high-volume use in image sensors, where the pixel array and logic wafers are bonded, and in bonded 3D NAND architectures. The pace of adoption will therefore differ between product classes: logic stacking is already in volume at several companies, wafer-to-wafer bonding is established in image sensors and NAND, and memory die stacking is likely to follow later. Each wave adds a new set of customers and a new set of consumable qualifications.
For CMP consumables, hybrid bonding creates demand that is different in kind from front-end polishing. The copper and barrier slurries used for bonding preparation must deliver a controlled copper recess with very tight within-wafer and wafer-to-wafer uniformity, rather than simply removing copper to a plane, and they must leave dielectric materials such as silicon carbon nitride with very low roughness and without residues that would interfere with bonding. Selectivity between copper, barrier and dielectric must be tuned for the specific recess target of each product. Soft and specialty pads are often used for the final steps to minimise scratching, and the number of wafers processed per pad can be lower than in front-end steps because of the stringent defect requirements. Post-CMP cleaning becomes more demanding as well, and suppliers that can co-optimise slurry, pad and cleaning chemistry have an advantage. Die-to-wafer bonding for chiplets adds steps on both the receiving wafer and the dies being placed, and the dies may need to be polished after thinning and singulation, which introduces new handling and contamination challenges.
In parallel, through-silicon via reveal, redistribution layer polishing and the planarization of thick dielectric and mould layers in fan-out wafer-level and panel-level packaging add steps that did not exist in conventional packaging lines. Panel-level packaging, which uses large rectangular substrates instead of round wafers, may require new pad and tool formats, offering further scope for product development. In addition, the material stacks used in packaging are often more varied than in front-end processing, combining copper, polymers, mould compounds and dielectrics on the same wafer, and slurries must polish these combinations without delamination or contamination. Wafers in packaging lines may also be thinned and bonded to temporary carriers, so pads and slurries must work at lower pressures and with greater sensitivity to wafer bow.
This opportunity is most relevant to the Advanced Packaging & Hybrid Bonding (TSV, RDL) process step and, by product, to Copper & Barrier Slurries, dielectric-selective Specialty Slurries and Soft & Specialty CMP Pads. Because hybrid bonding is being implemented by foundries within their advanced packaging operations, by memory makers for HBM and bonded NAND, and by outsourced assembly and test companies building their own capability, it broadens the customer base for high-value CMP consumables beyond the front-end fab and brings new buyers into the market. The geographic footprint of demand is also widening, since advanced packaging capacity is being built in Taiwan, South Korea, Japan, the U.S., Singapore, Malaysia and India, often in locations separate from the front-end fabs. Suppliers that can co-develop slurries, pads and post-CMP cleaning chemistries with equipment makers and customers at the pilot stage are positioned to become the process of record when volumes rise, and because the consumable value per packaged unit is high relative to the area polished, even modest increases in hybrid bonding volume can produce a meaningful increase in market value.
Over the forecast period, the opportunity is expected to grow in importance as logic chiplet stacking moves to finer pitches and as memory makers adopt hybrid bonding for taller HBM stacks. For suppliers, the opportunity also carries risk, since hybrid bonding processes are still evolving and a formulation qualified for one pitch or bonding scheme may need to be revised for the next generation. Close collaboration with customers and equipment makers during development, and the ability to supply consistent product from several regions, will determine which suppliers capture the largest share of this expanding application. Because the consumables involved are used at the final stage before chips are joined, a defect introduced here destroys the value of two or more finished dies, which is why customers accept higher prices for products that lower that risk.
Wide-Bandgap Substrates and Power Device Polishing
Silicon carbide and gallium nitride are wide-bandgap semiconductors used in power devices that switch higher voltages and operate at higher temperatures with lower energy losses than silicon. Silicon carbide is used mainly in electric vehicle traction inverters, onboard chargers, fast-charging stations, solar and storage inverters, rail traction and industrial motor drives, while gallium nitride is used in compact fast chargers for consumer electronics, data-centre power supplies, telecom infrastructure and radio-frequency devices for radar and wireless networks. Both materials are extremely hard and chemically resistant, which makes them difficult and slow to polish. Silicon carbide, which is close to diamond in hardness, must be sliced from a boule, lapped or ground, mechanically polished and then chemically mechanically polished to an epitaxy-ready finish that is free of scratches and subsurface damage, because any residual damage propagates into defects in the epitaxial layers grown on top and reduces device yield. The removal rates achievable with conventional silica slurries on silicon carbide are very low, so polishing can take hours per wafer. Specialised slurries that use strong oxidisers, such as permanganate-based chemistries, together with selected abrasives and dedicated pads, have been developed to raise removal rates and reduce polishing time while maintaining surface quality.
Because polishing times are long and the materials are expensive, consumable value per wafer is high, and the process is a significant element of substrate production cost. Gallium nitride substrates, where used, present similar challenges, and device-level processing of both materials includes planarization steps for which standard silicon chemistries are not suitable. Polishing is therefore one of the bottlenecks in silicon carbide substrate production, and improvements in consumables can directly increase the output of existing polishing tools. Substrate makers evaluate consumables on removal rate, surface roughness, the absence of scratches and subsurface damage, and the yield of epitaxial layers grown on the polished surface, each of which depends on the combination of slurry, pad and process conditions.
The silicon carbide industry is in the middle of a transition from 150 mm to 200 mm wafers, which changes polishing requirements and creates an opening for new consumables. Larger wafers are more prone to bow and warp, which makes uniform polishing harder, and new fabs built for 200 mm production are qualifying consumables from scratch. STMicroelectronics is building an integrated silicon carbide campus in Catania, Italy, covering substrate production through device manufacturing, for which the European Commission approved Italian state aid in May 2024. onsemi announced an investment of up to USD 2 billion in silicon carbide production in the Czech Republic in June 2024, and Infineon opened the first phase of its 200 mm silicon carbide fab in Kulim, Malaysia, in August 2024. Chinese substrate makers have expanded capacity rapidly, including at 200 mm, which lowered substrate prices during 2024 and 2025 and placed heavy pressure on Western producers; Wolfspeed entered Chapter 11 reorganisation in June 2025 and emerged in September 2025 with a reduced debt load.
Lower substrate prices and slower electric vehicle growth in some markets in 2024 and 2025 led several device makers to adjust their expansion schedules, but lower prices are also widening the range of applications where silicon carbide is economic, increasing the volume of substrates and epitaxial wafers that must be polished. For consumable suppliers, the expansion of Chinese substrate production has created a large new customer base, much of which is served by domestic slurry and pad makers, while Western and Japanese substrate and device makers continue to rely on established global suppliers. The transition to 200 mm also concentrates demand in fewer, larger customers, as smaller substrate producers without the resources to make the change consolidate or exit, which gives the leading substrate makers greater influence over consumable specifications and pricing. Equipment for silicon carbide polishing is evolving as well, with tools designed for higher pressures and longer polishing times, and consumables must be matched to these tools.
Gallium nitride is also gaining new applications, particularly in data-centre power. In May 2025, NVIDIA announced plans for 800-volt direct-current power architectures in AI data centres, working with power semiconductor companies including Infineon and Navitas, and both gallium nitride and silicon carbide devices are central to these designs because they allow efficient conversion at high voltage and high power density. Most gallium nitride power devices are built as epitaxial layers on silicon wafers, which are polished with established silicon processes before epitaxy, but bulk gallium nitride and gallium-nitride-on-silicon-carbide substrates for radio-frequency and high-voltage devices require dedicated polishing, and device processing includes planarization of dielectric and metal layers over unusual topography. The supply base for gallium nitride devices is shifting: in July 2025, TSMC confirmed that it would exit gallium nitride foundry services by 2027, and its customers began moving production to other foundries, each of which must qualify its own process flow, including any polishing steps. Gallium nitride's use in high-frequency front-end modules for wireless infrastructure and in defence radar provides a further, steadier source of demand.
Beyond silicon carbide and gallium nitride, research into gallium oxide and diamond as power semiconductors could, in the longer term, add further hard-material polishing requirements. The growth of data-centre power demand also benefits silicon carbide, which is used in higher-power conversion stages, and both materials are being designed into the power supplies, intermediate bus converters and battery backup units of AI server racks. These applications have stringent reliability requirements, which raise the quality standards for the substrates and epitaxial wafers on which the devices are built, and therefore for the polishing processes that prepare them.
Concentrated Supply of Abrasives and Pad Precursors
CMP consumables depend on a short list of specialised raw materials, several of which come from concentrated sources, and this concentration is the most significant supply-side constraint on the market. Cerium oxide, the abrasive that gives ceria slurries their high oxide removal rates and their selectivity to silicon nitride, is produced from rare-earth ores, and the separation of cerium from the other rare earths and its refining to high purity is dominated by Chinese processors. High-purity colloidal silica, which is the abrasive base for most copper, barrier and many oxide slurries, is made by a limited number of producers, with Japanese suppliers such as Fuso Chemical holding a leading position in the ultra-high-purity grades used for semiconductor polishing. Fumed silica, hydrogen peroxide and the organic additives used in slurries are more widely available, but electronic-grade versions with controlled trace metals are produced by fewer plants than industrial grades. On the pad side, cast polyurethane pads rely on isocyanate-terminated prepolymers, aromatic diamine curatives and expandable hollow polymer microspheres that create the pad's pore structure, and only a few chemical companies produce these inputs to the consistency that pad makers require.
For each of these materials, a change of source is not a simple purchasing decision. Particle size distribution, particle shape, surface chemistry, residual ions and trace impurities all affect removal rate, selectivity and defectivity, and the reactivity and molecular weight distribution of polymer precursors affect pad hardness, porosity and wear. Any change must therefore pass through the supplier's own validation and then through customer requalification, which can take several quarters and requires wafer time at fabs that are often running at full capacity. In practice, this means that slurry and pad makers cannot quickly replace an input when a supplier is disrupted, and that a disruption at one raw-material plant can affect several consumable makers at once.
The concentration risk became more visible in 2025 as China expanded its use of export controls on critical minerals. In April 2025, China introduced export licensing for seven medium and heavy rare-earth elements, including samarium, gadolinium, terbium, dysprosium, lutetium, scandium and yttrium. On 9 October 2025, its Ministry of Commerce announced a much broader set of controls covering five additional rare-earth elements, rare-earth processing equipment and raw and auxiliary materials, rare-earth technologies, and certain items produced abroad that contain Chinese-origin rare-earth content or were made with Chinese technology. Following trade talks between the U.S. and Chinese leaders, China suspended the October measures on 7 November 2025 until 10 November 2026, while the April licensing regime remained in force. Cerium is a light rare earth and was not among the elements named in the April list, and cerium oxide is produced in larger quantities than the heavy rare earths that were targeted.
Nevertheless, the breadth of the October announcements, which reached into processing equipment, technologies and extraterritorial content, showed that the rare-earth supply chain as a whole can be subject to sudden policy change, and that the controls could in future be extended to products or processes that slurry makers depend on. For slurry makers, the relevant risk extends beyond the availability of cerium oxide as a commodity to the processing know-how, intermediates and equipment involved in producing the very fine, uniform and pure ceria particles used in advanced slurries. The scheduled expiry of the suspension in November 2026 has added a fixed point of uncertainty to procurement planning, since suppliers and their customers cannot be sure whether the suspension will be extended, allowed to lapse or replaced by a different regime. For chipmakers outside China, the episode turned raw-material traceability from a quality issue into a supply-security issue, increasing requests to consumable suppliers for information on the origin of abrasives and on contingency arrangements in the event of renewed controls.
Suppliers have responded by seeking alternative sources, but this takes time and money. In December 2025, Resonac's chief executive said the company was diversifying procurement to reduce its reliance on Chinese rare earths and was working to develop second and third sources for raw materials used in its slurry, with possible alternatives including companies in Australia and Europe. Similar programmes are under way at other slurry makers, some of which are increasing in-house synthesis of ceria and silica particles to gain greater control over particle properties and to be able to work with a wider range of precursor sources. These efforts add cost, because rare-earth separation and refining capacity outside China is limited, more expensive to operate and in several cases still being built, and because each new source must be run in parallel with the incumbent until customers have qualified it. Pad makers face a comparable challenge with polyurethane inputs. Some aromatic amine curatives traditionally used in pad casting are regulated as substances of very high concern in Europe and require authorisation for continued use, which narrows the pool of acceptable suppliers and encourages formulation changes that must themselves be qualified.
Microsphere supply is concentrated in a very small number of producers, and an interruption at a single plant would affect most pad makers. In addition, the polymer and specialty chemical industries have been rationalising capacity in Europe in response to high energy costs, which could further reduce the number of qualified sources for some inputs. Chipmakers, for their part, have increased their scrutiny of sub-tier suppliers, asking slurry and pad makers to disclose raw-material origins and to maintain contingency stocks, which adds working capital requirements to suppliers' operations. The cost of this resilience is ultimately reflected in product pricing, although competitive pressure limits how much of it can be passed on.
The restraint affects the market in several ways. First, it raises the cost base of the most widely used slurry and pad categories at a time when customers resist price increases, which compresses supplier margins and can slow investment in new capacity or new product development. Second, it increases the risk of short-term supply interruptions, which encourages chipmakers to hold larger inventories and to dual-source critical consumables; while this can temporarily increase orders, it also ties up working capital and may delay the adoption of new formulations whose raw materials are less secure or less well understood. Third, it shapes product development choices, as suppliers favour abrasives and polymer systems with diversified supply and avoid introducing new dependencies on single sources. The segments most exposed are Oxide & STI Slurries (Ceria / Colloidal Silica), because of their reliance on ceria and on high-purity silica, and Hard Polyurethane CMP Pads, because of their dependence on specialised prepolymers, curatives and microspheres. By process step, FEOL polishing and the oxide-intensive steps of memory production are most sensitive, since these steps account for the largest volumes of ceria-based slurry.
The effect is felt across all regions, but suppliers serving fabs outside China face the greatest uncertainty because they cannot always source equivalent materials domestically, while Chinese slurry makers have easier access to domestic rare-earth supply but face their own constraints on imported high-purity silica and additives. Memory manufacturers, as the largest consumers of oxide slurries, are the end users most exposed to any disruption, followed by foundries with large isolation and dielectric polishing requirements. Over the longer term, the restraint is likely to ease as alternative sources are qualified and as regional processing capacity grows, but during the early forecast years it acts as a brake on the pace at which suppliers can expand ceria-based product lines and as a source of cost pressure that customers are reluctant to share.
Customer Concentration, Qualification Lock-In and Pricing Pressure
The customer base for CMP consumables is highly concentrated, and this concentration limits how much of the growth in physical consumption translates into growth in supplier revenue and margins. A handful of foundries and memory makers account for a large share of global wafer output at advanced nodes, and their purchasing teams negotiate prices and supply terms globally, covering many fabs and process steps in a single agreement. SEMI's materials data for 2025 illustrate the geographic side of this concentration: Taiwan remained the largest consumer of semiconductor materials for the sixteenth consecutive year, at USD 21.7 billion, followed by China at USD 15.6 billion and South Korea at USD 11.2 billion, with Japan, North America and Europe each considerably smaller. Within those economies, a small number of companies account for most leading-edge demand, and in some cases a single company accounts for most of a country's consumption. This gives major customers substantial bargaining power.
They typically require annual price reductions on mature products, insist on at least two qualified suppliers for critical steps, ask suppliers to hold consignment inventory at or near their fabs, and expect suppliers to fund dedicated technical support teams, local quality laboratories and rapid response to any excursion. They also control access to the information suppliers need to develop products for future nodes, sharing roadmaps and test structures selectively and using early engagement as a lever in commercial negotiations. A supplier that loses favour with one of these customers can lose access not only to current business but also to the development programmes that determine future process-of-record positions. Customer concentration also creates revenue concentration on the supplier side: for several leading slurry and pad makers, a few customers account for a large proportion of CMP sales, so the loss or gain of a single step at one customer can move results noticeably. This dependence encourages suppliers to accept demanding commercial terms rather than risk their position.
Qualification practices reinforce this imbalance in ways that cut in both directions. A slurry or pad must pass laboratory screening, tool-level tests, short-loop wafer runs, full-flow yield validation and reliability testing before it becomes the process of record for a given step, and the full sequence can extend over several quarters. Once qualified, a consumable is protected against displacement, which benefits the incumbent, but it also means that a supplier's revenue is tied to the production plans of specific fabs and nodes over which it has no control. When a customer cuts wafer starts, consumable orders fall almost immediately, as the 2023 memory downturn showed when several memory makers reduced output sharply and consumable suppliers' revenues fell in step. When a customer migrates to a new node, an incumbent can lose a step if a competitor's formulation performs better in the new flow, and the investment made in the previous qualification cannot be recovered. The same lock-in makes it difficult for suppliers to pass on raw-material cost increases, because customers are reluctant to accept price changes on a qualified product and can respond by accelerating the qualification of a second source.
Change control requirements, under which any change in raw-material source, production site or process must be notified in advance and may trigger requalification, add to the cost of responding to supply disruptions or regulatory changes, and they slow the rate at which suppliers can introduce cost reductions into qualified products. The qualification burden also falls unevenly. Large suppliers can spread the cost of supporting qualifications across many products and customers, while smaller suppliers may need to concentrate their resources on a few opportunities, which limits their ability to compete for new steps at several customers at the same time. Customers can use the timing and scope of qualification opportunities to influence supplier behaviour.
Recent supplier results illustrate the pressure. Entegris reported that its second-quarter 2025 revenue declined by 2.5% year on year even though its CMP slurries and pads business was growing strongly, citing softness in semiconductor capital spending and the effect of tariffs, and its profitability measures contracted in parts of its business during that period. In China, the rise of domestic suppliers has intensified price competition, since local chipmakers have been encouraged by national policy to qualify domestic slurries and pads and can use that capability to negotiate harder with international suppliers on the remaining steps. Domestic suppliers in China have grown rapidly; Anji Microelectronics reported revenue growth of about 36% in 2025, with CMP slurries accounting for most of its sales. Mature-node foundries in China and elsewhere, which operate with thinner margins than leading-edge producers and which faced utilisation pressure in 2024 and 2025, are particularly price-sensitive and have pushed for lower prices on oxide, tungsten and pad products that are regarded as more interchangeable. In memory, price negotiations follow the memory cycle, with memory makers seeking concessions during downturns and accepting stable pricing only when their own margins are high.
Suppliers have also had to absorb the cost of regional duplication, since customers increasingly ask for local production as a condition of continued business but do not necessarily pay a premium for locally produced material. Pricing pressure also varies through the year and the cycle; it tends to intensify during annual contract negotiations and during inventory corrections, when customers reduce orders and ask suppliers to share the burden of lower utilisation through price concessions or extended payment terms. In such periods, suppliers have limited ability to resist, since their fixed costs for plants, laboratories and field engineers continue regardless of volume.
Selectivity-Driven Changes in Abrasives and Metal Chemistries
The composition of CMP slurries is changing as device structures demand higher selectivity and lower defectivity, and this is reshaping the product mix within each slurry category. In oxide and shallow trench isolation polishing, ceria has been displacing silica for more than a decade because cerium oxide reacts chemically with silicon dioxide, forming bonds at the particle-surface interface that allow material to be removed at high rates with a much lower abrasive loading than silica requires. When combined with additives that adsorb on silicon nitride and suppress its removal, ceria slurries can achieve very high oxide-to-nitride selectivity, which allows a polishing step to stop precisely on a thin nitride layer. The current phase of this trend is a move toward smaller and more uniform ceria particles produced by wet chemical synthesis, often described as colloidal ceria, in place of the larger calcined and milled particles used in earlier generations. Smaller particles with narrow size distributions reduce scratches and residual particle defects, which is critical for gate-all-around and 3D NAND structures where stop layers are only a few nanometres thick and where a single scratch can short adjacent features.
Suppliers are also developing composite abrasives, such as silica particles coated with ceria, and surface-modified particles whose interaction with the wafer can be tuned by the additive package, combining the chemical activity of ceria with the dispersion stability and low defectivity of colloidal silica. Some suppliers produce their own ceria particles to control morphology and impurity levels, which is becoming a point of differentiation as customers tighten specifications on large particle counts and trace metals. The result is a steady rise in the value of oxide and isolation slurries per litre, even where volumes are growing modestly, and an increasing technical gap between leading-edge formulations and the commodity slurries used in mature processes.
In parallel, slurry makers are using additive chemistry to control selectivity more precisely across a growing range of film pairs. Passivating agents that adsorb preferentially on nitride or polysilicon surfaces, pH regimes chosen to exploit differences in surface charge between films, polymer additives that change the local pressure distribution under the pad, and surfactants that control how abrasive particles interact with patterned surfaces are being combined to achieve stop-on-layer performance that earlier generations of slurries could not reach. For gate-all-around transistors, chipmakers need slurries that remove polysilicon while stopping on nitride, remove oxide while stopping on polysilicon, polish nitride without damaging silicon-germanium layers, and planarize metal gate stacks without attacking high-k dielectrics or work function metals. Each of these requirements has led to new formulations within the Specialty Slurries category, and some steps now use two or three slurries in sequence to balance removal rate with final-stage selectivity. As a result, the number of distinct slurry products used in a single advanced fab is increasing, and suppliers are managing larger portfolios of lower-volume, higher-value products.
This trend raises barriers to entry, since each formulation embodies specific know-how and must be developed in close collaboration with the customer, but it also increases suppliers' development costs and the complexity of their manufacturing and quality systems. It favours suppliers with strong application laboratories near major customers, broad intellectual property in additive chemistry and the ability to scale small-volume products economically. For customers, the proliferation of specialised slurries adds to supply chain complexity and to the number of qualifications they must manage, which reinforces the interest in integrated consumable sets from fewer suppliers. It also raises the importance of consistent raw materials, since small variations in additive purity can alter selectivity.
The metal side of the market is undergoing a parallel shift. Tungsten has long been the standard contact and plug metal, deposited by chemical vapour deposition into contact holes and polished back to leave isolated plugs, and its slurries, based on iron catalysts or other oxidising systems with silica or alumina abrasives, are mature and widely produced. Cobalt was introduced for contacts and local interconnects at some nodes in the late 2010s because of its lower resistance in narrow features, and it required new slurries designed to control galvanic corrosion and recess. At the most advanced nodes, molybdenum and ruthenium are now being introduced because they offer lower resistance in very narrow features, have shorter electron mean free paths that reduce resistivity increases at small dimensions, and can be deposited without thick barrier layers that take up space in the feature. Their chemistries differ markedly from tungsten. Molybdenum dissolves readily in oxidising, alkaline environments and requires effective corrosion inhibition to prevent excessive recess and pitting, while ruthenium is chemically resistant and requires stronger oxidisers or specific complexing agents to achieve useful removal rates without damaging surrounding films.
In memory, molybdenum is being evaluated as a replacement for tungsten in 3D NAND word lines, where its lower resistance could support further layer count increases, which would change the metal polishing requirements of NAND fabs if adopted at scale. Copper interconnects remain in use above the lowest levels, but barrier and liner materials are changing as thinner barriers and alternative liners are adopted, requiring barrier slurries to be reformulated to remove the new stacks cleanly. Because new metals are introduced first in a limited number of layers at a few fabs, their slurries are produced in small volumes at high prices, and the suppliers that develop them early gain experience that can be applied as adoption spreads to further layers and customers.
This trend reshapes demand within the product categories rather than adding a new category, and it explains part of the difference in growth rates between them. It increases the value of Specialty Slurries, sustains demand for engineered ceria within Oxide & STI Slurries, and changes the mix within Tungsten, Cobalt & Other Metal Slurries as new metals replace tungsten in some applications at the leading edge and as volumes of conventional tungsten slurry grow more slowly. By process step, the shift is most visible in FEOL and MOL / Contact (W, Co) polishing at leading foundries and in the word line and contact steps of memory fabs, while BEOL polishing is affected mainly through barrier and liner changes. Pads are adapting too, with designs that use engineered pore sizes, controlled hardness and specific groove patterns to support low-abrasive and highly selective slurries, since a slurry designed for high selectivity can lose that selectivity if the pad generates excessive local pressure or poor slurry transport.
By end user, Foundries are the earliest adopters of new abrasive and metal chemistries, followed by Memory Manufacturers, while Logic & Analog / Power IDMs operating mature processes continue to rely on established silica, calcined ceria and tungsten products. Regionally, demand for the newest formulations is concentrated in Taiwan, South Korea and the U.S., where leading-edge logic and memory are produced, while China's domestic suppliers are working to close the gap in ceria and specialty formulations for local fabs. Over the forecast period, this trend is expected to continue to raise the share of advanced formulations in market value. It also increases the importance of supplier intellectual property, since many selectivity mechanisms and new metal chemistries are protected by patents, and customers increasingly evaluate suppliers on their ability to deliver solutions for future process changes rather than only on the performance of current products.
Chemical Stewardship, Water Use and Waste Reduction
Sustainability requirements are increasingly shaping how CMP consumables are formulated, delivered, used and disposed of, and this influence is growing from regulation, from chipmakers' own environmental commitments and from the practical constraints of operating fabs in water-stressed locations. Chemical regulation is the most immediate influence on formulation. The European Union's proposal for a universal restriction on per- and polyfluoroalkyl substances, submitted to the European Chemicals Agency in January 2023 by authorities in Germany, the Netherlands, Denmark, Norway and Sweden, was revised and republished in August 2025. ECHA's Risk Assessment Committee adopted its final opinion in support of a restriction on 2 March 2026, and its Committee for Socio-Economic Analysis agreed a draft opinion on 10 March 2026 that supports targeted derogations where alternatives are not yet available. A public consultation on that draft ran from 26 March to 25 May 2026, and the electronics and semiconductor sector was among the most active respondents. The final opinions are expected to reach the European Commission by the end of 2026, after which the Commission must prepare a draft restriction for a vote by member states.
Fluorinated surfactants and additives are used in some slurry formulations, and fluoropolymers are widely used in slurry containers, tubing, valves and filters in the delivery chain, so suppliers are reviewing formulations, preparing documentation for possible derogations and developing non-fluorinated alternatives where performance allows. In the U.K., the government published a PFAS plan on 3 February 2026 that includes an indicative action to align U.K. chemical regulation with that of its closest trading partners by December 2028. Customers in Europe and elsewhere are already asking suppliers to declare PFAS content and to present substitution plans. Even where no restriction yet applies, commercial pressure from customers is encouraging suppliers to treat PFAS substitution as a development priority.
Water use is a second focus, and it links CMP consumables directly to the operating constraints of fabs. CMP and post-CMP cleaning are among the most water-intensive steps in semiconductor manufacturing, because slurries are diluted with ultrapure water at the point of use, pads are rinsed during and between polishing cycles, and wafers are cleaned extensively after polishing to remove particles and residues. Chipmakers in Taiwan, Arizona and other water-stressed locations have committed to high levels of water reclamation, and some have built dedicated reclamation plants. CMP wastewater is one of the more difficult streams to treat and recycle, because it contains finely dispersed abrasive particles that do not settle easily, dissolved metals such as copper, residual oxidisers and organic additives, and it often requires coagulation, membrane filtration and ion exchange before reuse. Slurry suppliers are responding with formulations that work at lower abrasive concentrations, concentrates that reduce transport volumes and packaging waste, and support for slurry and abrasive recovery programmes that remove particles from wastewater and, in some cases, recover silica or ceria for other uses.
Their own operations are also under scrutiny; Entegris designed its Kaohsiung facility, opened in 2023, to recycle more than 85% of process water and to generate part of its electricity from on-site solar panels. Water availability is now a factor in where new fabs are located and in the permitting process for new capacity, and consumable suppliers that can help customers reduce water use per wafer gain an advantage in supplier evaluations. In some locations, permits for fab expansion are linked to commitments on water reuse, which makes the water performance of consumables a factor in capacity planning as well as in daily operations. Suppliers that can provide data on the rinse and cleaning water required after polishing with their products are better placed in these discussions.
Waste and emissions are a third dimension. Used CMP pads are made of cross-linked polyurethane bonded to sub-pads with adhesives, and they cannot easily be recycled, so large fabs dispose of significant volumes of pad waste each year. Pad suppliers are working on longer-lasting pads, pads with components that can be separated more easily, and conditioning strategies that extend pad life without increasing defects, all of which reduce waste per wafer. Slurry packaging is shifting toward returnable and larger containers where customers' delivery systems allow it. Chipmakers have set long-term greenhouse gas reduction and net-zero targets that include indirect emissions from purchased materials, and they increasingly ask suppliers to report product carbon footprints, to source renewable electricity and to set their own reduction targets. For CMP consumables, the main emission sources lie in the energy used to produce abrasives and polymers, in the production of hydrogen peroxide and other chemicals, and in transport, which favours regional production and concentrated products. Suppliers that can document lower emissions per litre of slurry or per pad, and that can show credible reduction plans, are gaining an advantage in supplier evaluations, even though price, performance and supply security remain the primary criteria.
Hydrogen peroxide, the most common oxidiser in metal slurries, is typically added at the fab, and its production and transport also contribute to the footprint of the CMP step, so the total environmental effect of polishing depends on the full set of chemicals used rather than on the slurry concentrate alone. Reducing the number of wafers that must be reworked because of CMP defects is another indirect route to lower waste and emissions, which links sustainability objectives to the yield performance of consumables. Some pad makers are also evaluating alternative polyols and curatives to reduce the environmental footprint of pad materials, although these must match the performance of established formulations before they can be adopted.
The value chain for CMP slurries and pads runs from specialised mineral and chemical inputs, through formulation and manufacturing by a limited number of qualified suppliers, through a distribution system shaped by the physical properties of the products, to the CMP tools of fabs and wafer plants where the consumables are used. It is a short chain in terms of the number of hand-offs, since most consumables move directly from the manufacturer to the fab, but it is a demanding one, because every stage must meet purity and consistency requirements that are far tighter than those of conventional industrial chemicals. Value is created mainly at the formulation and manufacturing stage, where proprietary chemistry, particle engineering and process know-how are converted into products that pass customer qualification, and the strongest dependencies run both upstream to a few raw-material producers and downstream to a few large chipmakers.
The first stage comprises raw materials and inputs. For slurries, the critical inputs are abrasive particles and chemical additives. Ceria abrasives begin with rare-earth ore that is mined, separated into individual rare-earth oxides and refined to high-purity cerium compounds, which are then converted into fine particles either by calcination and milling or by wet precipitation and hydrothermal growth. Silica abrasives come in two main forms: fumed silica, made by burning silicon tetrachloride in a hydrogen-oxygen flame, and colloidal silica, grown in solution from silicate or alkoxide precursors, with the highest-purity grades produced from tetraethyl orthosilicate. Alumina is used in some metal and hard-material slurries. Chemical additives include oxidisers such as hydrogen peroxide, potassium permanganate and periodates, complexing agents such as glycine and other amino or carboxylic acids, corrosion inhibitors such as benzotriazole and its derivatives, pH buffers, biocides, surfactants and polymeric selectivity modifiers, all supplied in electronic or high-purity grades. Ultrapure water is the largest component by volume. For pads, the inputs are polyether or polyester polyols and isocyanate-terminated prepolymers, aromatic diamine curatives, expandable hollow polymer microspheres that create the pore structure, foams, felts and non-woven materials for soft pads and sub-pads, pressure-sensitive adhesives and backing films.
Value added at this stage lies in achieving tight control of particle size, shape and impurity levels for abrasives and consistent molecular weight and reactivity for polymer precursors. The participants include rare-earth processors concentrated in China, colloidal silica producers concentrated in Japan, global chemical companies supplying fumed silica, peroxide and polyurethane systems, and a small number of microsphere producers. The main dependency is the concentration of critical inputs in a few companies and countries, which limits the ability of slurry and pad makers to switch sources quickly.
Pricing power at this stage varies by material. Producers of ultra-high-purity colloidal silica and of fine, uniform ceria particles can command premium prices because their products are difficult to replicate and are written into customers' qualified bills of materials, whereas producers of commodity additives compete mainly on price and consistency. The value captured upstream also depends on how far slurry makers have integrated backward. Several leading slurry makers synthesise or modify abrasive particles in-house, capturing value that would otherwise sit with abrasive producers and gaining control over the particle properties that most affect performance, while others buy finished abrasive dispersions and focus on additive chemistry. Pad makers vary in the same way, with some casting their own polyurethane from purchased prepolymers and others producing prepolymers or microspheres internally. Backward integration has become more attractive since 2025, when export controls on rare-earth items and growing customer scrutiny of raw-material origins highlighted the risks of relying on a single external source.
The second stage is manufacturing, which divides into slurry formulation and pad production. Leading slurry makers increasingly synthesise or modify their own abrasive particles to control the properties that determine removal rate and defectivity, and they classify particles to remove oversized agglomerates. Formulation combines abrasive dispersions with the additive package under controlled conditions, followed by multi-stage filtration, in-line measurement of particle size distribution and large particle counts, analysis of trace metals at parts-per-billion levels, and filling into clean, certified containers. Slurries are typically supplied as concentrates that are diluted and mixed with oxidiser at the fab, and suppliers often operate blending sites close to major customers. Pad production starts with casting or moulding polyurethane, either as large cakes that are cured and then skived into sheets or as individual moulded pads. The sheets are machined to precise thickness, grooved with patterns designed to distribute slurry and remove debris, laminated to sub-pads and adhesive layers, inspected for density, hardness and defects, and packaged in clean conditions. Some pads incorporate transparent windows for optical endpoint detection.
Value added at this stage is the highest in the chain because it embodies the supplier's intellectual property in formulations, particle engineering, polymer chemistry and pad microstructure, as well as the quality systems that ensure lot-to-lot consistency. The main participants are Entegris, Qnity Electronics, Fujifilm, Resonac, Merck KGaA, Fujimi Incorporated, AGC, Anji Microelectronics and Hubei Dinglong, together with a group of regional and specialised producers in Japan, South Korea, Taiwan and China. Pad makers depend on CMP tool manufacturers such as Applied Materials and Ebara, because pad dimensions, groove designs and endpoint windows must be compatible with specific polisher platforms, and slurry makers depend on equipment makers for tool access during development.
China provides a clear example of how the manufacturing stage is being reorganised around domestic supply. Anji Microelectronics has grown into the country's leading slurry maker, reporting revenue of about RMB 2.5 billion in 2025, of which CMP slurries accounted for the large majority, and it has pursued the development of its own raw materials alongside its formulations. Hubei Dinglong has built a vertically integrated pad business, producing the core raw materials of its pads, including microspheres, internally and expanding pad capacity at its Wuhan and Qianjiang sites; in June 2026 it announced a third pad production line in Qianjiang. Dinglong has also built abrasive particle capacity to support its own slurry products. These companies benefit from proximity to domestic fabs and from national policy that encourages local sourcing, and they are reducing the dependence of Chinese fabs on imported consumables at the manufacturing stage of the chain.
Research and development is an integral part of this stage and a key source of value. New slurries and pads are developed in close collaboration with chipmakers and equipment makers, often two or three years before a node enters production. Suppliers maintain application laboratories with production-grade CMP tools and metrology near major customer sites, run designed experiments on customer film stacks and support customers through qualification. Patents on abrasive compositions, additive packages and pad structures are an important barrier, and leading suppliers hold large portfolios in each area.
Equipment makers and adjacent consumable suppliers play an important supporting role in the chain even though their products fall outside the market. CMP tool makers, principally Applied Materials and Ebara in the global market, define the platforms on which slurries and pads must perform, including platen size, carrier head design, slurry dispense method, pad conditioning system and endpoint detection technology, and they work with consumable suppliers during the development of new tools and processes. Pad conditioner makers supply the diamond discs that maintain pad texture, and their products strongly influence pad life and slurry performance. Filtration suppliers provide the point-of-use and loop filters that remove oversized particles from slurries before they reach the wafer, and post-CMP cleaning chemistry suppliers provide the solutions that remove residues after polishing. Companies such as Entegris that operate across several of these categories can coordinate development across the step, while specialists in a single category must work through the customer or form partnerships to achieve the same coordination.
The third stage is distribution and channels. Because slurries are heavy, mostly water and sensitive to freezing, heat and long storage, and because pads are bulky and must be kept clean, logistics strongly shape the structure of the chain. Most sales to large chipmakers are direct, managed through global account teams that negotiate supply agreements and local teams that handle daily ordering, inventory and technical support. Suppliers commonly hold consignment or vendor-managed inventories at or near customer sites, and some operate dedicated blending and packaging facilities next to large fab clusters, such as those in Hsinchu, Tainan, Kaohsiung, Pyeongtaek, Kumamoto and Arizona. In smaller markets, including parts of Southeast Asia, Europe, Latin America and the Middle East, specialised distributors handle importation, storage and delivery for research fabs, specialty device makers and assembly sites. Value added at this stage comes from reliable supply, temperature-controlled logistics, traceability of each lot to its raw-material sources, rapid response to quality excursions and the presence of field engineers who can troubleshoot problems at the tool. The main dependencies are on specialised logistics providers for chemical transport and on customs and trade regimes that allow consumables to cross borders quickly, which is why export controls and tariff changes are closely watched by suppliers.
The fourth stage comprises the end users, where consumables are converted into process outcomes. At a fab, slurry concentrates are received into a slurry distribution system that dilutes, mixes, filters and recirculates them, while monitoring parameters such as density, pH and particle size, before delivery to the polishers. Pads are installed on the platen, broken in by conditioning and replaced after a defined number of wafers or when performance drifts. Process engineers own the recipe for each CMP step, including pressure, platen and carrier speeds, slurry flow and conditioning, and they decide which consumables are qualified. Foundries, memory makers and integrated device manufacturers are the largest users, followed by outsourced assembly and test companies that perform packaging-related polishing, and by silicon, silicon carbide and gallium nitride wafer producers that polish substrates before shipment. Value added at this stage is the yield and performance of the finished devices, which is why end users place so much weight on consumable consistency and defectivity. Used slurry and rinse water are sent to wastewater treatment, where abrasives and metals are removed, and used pads are disposed of as industrial waste.
Value is distributed unevenly along the chain. Raw-material producers capture a modest share of the final value of most slurries and pads, with the exception of high-purity abrasives and specialised polymer inputs. Consumable manufacturers capture the largest share, reflecting the intellectual property, qualification history and quality systems embedded in their products, and their margins are highest on new formulations for advanced steps and lowest on mature, multi-sourced products. Distribution adds relatively little value in direct sales to large chipmakers, where suppliers manage logistics themselves, but more in fragmented markets served by distributors. For end users, consumables represent a small share of total wafer cost but a large share of CMP process risk, which is why they are willing to pay for performance and consistency while pressing hard on the price of products they regard as interchangeable. The chain also has a reverse flow: spent slurry and rinse water pass to wastewater treatment, where abrasives and metals are removed and some water is reclaimed, and used pads are collected for disposal, with growing interest in recovery and recycling as fabs pursue sustainability targets.
Several cross-cutting dependencies define how the chain behaves. Demand flows almost directly from wafer starts at the end user to orders at the manufacturer, so changes in fab utilisation propagate up the chain within weeks. Qualification ties each consumable to a specific step at a specific fab, which gives incumbent suppliers stability but also binds them to their customers' technology choices. Raw-material concentration upstream means that a disruption at a single rare-earth processor, silica producer or microsphere maker can affect several slurry or pad makers at once. Finally, the chain is being regionalised: suppliers are adding blending and pad production close to new fabs in the U.S., Japan, Europe and India, while Chinese chipmakers are building domestic supply chains that run from local abrasive and polymer producers through domestic slurry and pad makers. As a result, the chain is gradually splitting into a globally integrated network serving most of the industry and a parallel, increasingly self-contained network serving China.
CMP slurries and pads are regulated as chemical products and articles, and their manufacture and use are governed by chemical control, worker safety, environmental and trade regulations in each major region. The industry also relies on voluntary standards that define the purity, packaging and handling of semiconductor chemicals and the quality systems of suppliers. Regulation rarely prevents the use of CMP consumables outright, but it influences which raw materials can be used, how products are labelled and transported, how wastewater from polishing is treated, and whether consumables and their inputs can move freely between countries.
In the United States, the Toxic Substances Control Act, administered by the Environmental Protection Agency, requires that chemical substances in slurries be listed on the TSCA Inventory or cleared through new chemical review before they are manufactured or imported. In October 2023, the EPA finalised a rule under section 8(a)(7) of the Act requiring one-time reporting on PFAS manufactured or imported since 2011, including PFAS contained in imported articles; the agency has since postponed the start of the reporting window and in 2025 proposed changes to narrow its scope, so the rule remains in force but its final reporting obligations are still being settled. Wastewater from semiconductor fabs, including CMP effluent, is subject to permits under the Clean Water Act and to the effluent guidelines for electrical and electronic components, while worker exposure to slurry chemicals and pad precursors is governed by Occupational Safety and Health Administration standards, including the Hazard Communication Standard.
Trade regulation is equally relevant: the Export Administration Regulations control the export of certain semiconductor manufacturing items and technologies to China and other destinations, and in January 2026 the President imposed a 25% tariff under Section 232 of the Trade Expansion Act on a narrow set of advanced computing chips, with broader measures on semiconductors and related products reserved for later decision. The CHIPS and Science Act of 2022 provides grants and an investment tax credit for semiconductor manufacturing, including materials facilities, and Entegris was the first supplier to semiconductor manufacturers to finalise a CHIPS award agreement, in December 2024. Federal agencies also influence the market through research programmes; the CHIPS for America research and development initiatives, including programmes on advanced packaging, fund work on processes such as hybrid bonding in which CMP consumables are used, and suppliers participate in these programmes alongside chipmakers and universities.
In the European Union, the REACH Regulation requires registration of substances manufactured or imported in quantities of one tonne or more per year, and it restricts or requires authorisation for substances of very high concern. Several aromatic amines used as curatives in polyurethane production, including 4,4'-methylenebis(2-chloroaniline), are on the REACH Authorisation List, which affects pad manufacturing in Europe and the sourcing of pad components. Since August 2023, REACH has required industrial and professional users of diisocyanates above a set concentration to complete training, which applies to polyurethane processing. The most significant pending measure is the proposed universal PFAS restriction: following the revised proposal published in August 2025, ECHA's Risk Assessment Committee adopted its final opinion in March 2026, its Committee for Socio-Economic Analysis agreed a draft opinion the same month, and the final opinions are expected to be sent to the European Commission by the end of 2026, after which the Commission must prepare a draft restriction for a vote by member states. The Classification, Labelling and Packaging Regulation governs hazard labelling of slurries, and the revised Industrial Emissions Directive, adopted in 2024, tightens permit and emission conditions for large industrial installations.
On the industrial policy side, the European Chips Act entered into force in September 2023, and on 3 June 2026 the Commission proposed a Chips Act 2.0 that would replace it, with provisions on supply security, faster permitting and support for strategic projects; the proposal is now in the ordinary legislative procedure. Member states also apply national rules on industrial wastewater and on the handling of hazardous substances, and fabs in Germany, Ireland, France and Italy operate under permits that set discharge limits for metals and suspended solids from CMP effluent.
In China, new chemical substances must be registered with the Ministry of Ecology and Environment under the Measures for Environmental Management Registration of New Chemical Substances, in force since January 2021, and hazardous chemicals are subject to safety management regulations covering production, storage and transport. China's Export Control Law, in force since December 2020, provides the legal basis for the controls on rare earths and related technologies that the Ministry of Commerce announced in April and October 2025. The October 2025 measures were suspended on 7 November 2025 until 10 November 2026, while the April 2025 licensing requirements for medium and heavy rare earths remained in place. China's industrial policies, including the third phase of the National Integrated Circuit Industry Investment Fund registered in May 2024, support domestic semiconductor manufacturing and materials development, which encourages chipmakers to qualify local consumables.
The experience of the industry with materials-related trade measures shows why these regimes matter for CMP consumables. In July 2019, Japan tightened export procedures for fluorinated polyimide, photoresists and hydrogen fluoride to South Korea, prompting Korean chipmakers and the Korean government to accelerate the localisation of semiconductor materials, including CMP slurries and pads; Japan restored South Korea to its preferential export list in 2023. The episode demonstrated that even a measure that did not target CMP products directly could change sourcing strategies for a broad range of materials, and it contributed to the growth of Korean consumable suppliers. China's 2025 rare-earth measures have had a similar effect on supplier strategies outside China, encouraging diversification of abrasive sources and regional production of consumables.
In Southeast Asia, where a growing share of assembly, test and specialty wafer capacity is located, regulation is shaped by national industrial strategies and environmental rules. Malaysia launched its National Semiconductor Strategy in May 2024 to move its industry toward front-end manufacturing and advanced packaging, and Singapore continues to attract wafer fabrication and packaging investment under strict trade effluent controls administered by its national environmental authority. Fabs and assembly plants in these countries operate under discharge limits for metals and suspended solids that apply to CMP wastewater, and suppliers serving them must comply with local chemical registration and import requirements. As packaging-related polishing expands in the region, these rules will become more relevant to consumable suppliers, particularly for slurries used in through-silicon via and redistribution layer steps.
In Japan, the Chemical Substances Control Law requires notification and evaluation of new chemical substances, and the Industrial Safety and Health Act governs workplace exposure. Japan's Economic Security Promotion Act of 2022 designated semiconductors, including key materials, as specified critical products, enabling government support for stable supply, and the government has funded TSMC's Kumamoto fabs and Rapidus. In South Korea, the Act on Registration and Evaluation of Chemicals and the Chemicals Control Act regulate chemical substances and hazardous chemicals, while the Restriction of Special Taxation Act, as amended under the label of the K-Chips Act, provides tax credits for semiconductor investment. In Taiwan, the Toxic and Concerned Chemical Substances Control Act and the Occupational Safety and Health Act apply to slurry chemicals, and fabs operate under strict water discharge and reuse requirements in science parks. In India, the India Semiconductor Mission, operating since December 2021, provides fiscal support for fabs and assembly units, and chemical handling falls under the Manufacture, Storage and Import of Hazardous Chemical Rules.
Industry standards complement these laws. SEMI standards define specifications for process chemicals, guidelines for chemical packaging and delivery, and safety guidelines for semiconductor equipment, and many customers reference them in supply agreements. Suppliers are generally certified to ISO 9001 for quality management and ISO 14001 for environmental management, and those serving automotive device makers often follow IATF 16949 practices. Customers also impose their own requirements on supplier change notification, under which any change in raw-material source, manufacturing site or process must be notified in advance and may trigger requalification. In practice, these customer-driven change control rules are among the most influential regulatory constraints on CMP consumables, because they determine how quickly suppliers can respond to raw-material disruptions or regulatory changes.
Transport and storage regulations also apply to CMP consumables. Most slurry concentrates are classified as non-hazardous or of low hazard for transport, but oxidisers such as hydrogen peroxide, which are added at the fab, and some slurries containing oxidising or corrosive components are regulated as dangerous goods under the United Nations recommendations on the transport of dangerous goods and the national and modal rules based on them. Slurries must also be protected from freezing and extreme temperatures, which is a quality rather than a legal requirement but one that shapes storage and shipping practices. Within fabs, the storage and handling of slurries and oxidisers is subject to fire codes, building codes and the fab's own environmental, health and safety systems, and slurry distribution systems are designed to contain leaks and to segregate incompatible chemicals.
06 Jul 2022: Entegris; Acquisition; Completed the acquisition of CMC Materials, adding its CMP slurry and pad businesses to Entegris's portfolio.
10 May 2023: Entegris; Expansion; Opened its largest manufacturing facility in Kaohsiung, Taiwan, with production that includes CMP pads and slurries.
05 Dec 2024: Fujifilm; Expansion; Announced an investment of about JPY 2 billion to expand CMP slurry capacity at its Kumamoto site by about 30%, with operation from January 2025.
07 Feb 2025: Fujifilm; Expansion; Announced an investment of about JPY 4 billion to install CMP slurry production at its site in Zwijndrecht, Belgium, scheduled to start in spring 2026.
07 Oct 2025: Qnity Electronics; Partnership; Signed a long-term CMP pad supply agreement with SK hynix at SEMICON West in Phoenix.
01 Nov 2025: Qnity Electronics; Spin-off; Completed its separation from DuPont as an independent company supplying CMP pads, slurries and post-CMP cleans.
06 Mar 2026: Qnity Electronics; Acquisition; Announced the acquisition of a semiconductor facility in Taiwan for about USD 61.5 million to support advanced chip manufacturing applications.
11 Mar 2026: Qnity Electronics; Expansion; Opened a 385,000 square foot facility in Newark, Delaware, whose first line produces CMP pad components.
08 Jun 2026: Hubei Dinglong; Expansion; Announced a third CMP pad production line in Qianjiang, Hubei, with an investment of about CNY 30 million.
The developments show three strategic themes. First, portfolio restructuring has created more focused competitors, as shown by Entegris's acquisition of CMC Materials and DuPont's separation of Qnity Electronics, while smaller suppliers have exited or sold CMP businesses. Second, suppliers are investing in regional capacity close to customers, with new or expanded facilities in Taiwan, Japan, Belgium and the U.S., in response to the geographic diversification of fabs and customers' demands for supply security. Third, long-term supply agreements and capacity expansions reflect the growth in demand driven by AI-related logic and memory production, with memory makers seeking to secure consumable supply and Chinese suppliers expanding to meet domestic demand.
Political factors are central to the market's development. Governments in the U.S., the European Union, Japan, South Korea, Taiwan, China and India treat semiconductor manufacturing as a strategic capability and are subsidising new fabs, which creates demand for consumables in locations that had little or no leading-edge production a few years ago. At the same time, geopolitical rivalry between the U.S. and China has produced export controls on chips, equipment and critical minerals, and trade measures such as the U.S. Section 232 semiconductor tariffs announced in January 2026. For CMP consumables, the political environment encourages localisation of supply, adds uncertainty to cross-border sourcing of abrasives and chemicals, and pushes Chinese chipmakers to qualify domestic slurries and pads. Policy also shapes the location of new consumables capacity, since several governments offer incentives to materials suppliers as well as to chipmakers, and local content considerations are becoming more visible in incentive programmes. The scheduled expiry in November 2026 of China's suspension of its October 2025 rare-earth measures is a specific political event that suppliers and customers are monitoring closely.
Economic factors operate mainly through the semiconductor cycle. Consumable demand follows wafer starts closely, so memory price cycles, inventory corrections and changes in end-market demand for smartphones, personal computers, data-centre equipment, vehicles and industrial products translate quickly into slurry and pad orders. The strength of AI-related demand in 2025 and 2026, which led the World Semiconductor Trade Statistics organisation to forecast in June 2026 that the global semiconductor market would exceed USD 1.5 trillion in 2026, supports capacity additions, although much of that growth reflects memory pricing rather than wafer volume. Inflation in energy, logistics and chemical inputs, together with currency movements, affects supplier costs, while customers' annual price reduction demands limit the ability to pass those costs on. Economic conditions also differ by region. Japan's weak yen in 2024 and 2025 improved the export competitiveness of Japanese slurry and pad makers, while European suppliers faced higher energy costs than competitors in Asia and North America. Interest rates influence the pace of fab construction, since large projects are financed partly with debt, and changes in financing conditions can delay or accelerate capacity additions and therefore consumable demand. For suppliers, the net economic effect is a market whose volume grows with semiconductor output but whose prices remain under steady pressure.
Social factors are less direct but still important. The semiconductor industry faces shortages of skilled process engineers and technicians in several regions, particularly in the U.S., Europe and India, where new fabs are being built faster than local talent pools can grow. This raises the importance of supplier field engineers and application support, since new fabs rely on consumable suppliers to help them reach target yields. Public attention to chemical safety, water use and local environmental effects of large fabs also shapes permitting and community acceptance, which can influence the timing of new capacity and therefore of consumable demand. Workforce constraints also affect suppliers directly, since they must recruit chemists, materials scientists and application engineers in the same labour markets as chipmakers, and competition for experienced staff in Taiwan, Arizona and other fab clusters has intensified. Community expectations regarding environmental performance increasingly influence where suppliers locate new plants.
Technological factors are the principal source of growth in CMP intensity. Gate-all-around transistors, backside power delivery, new contact and interconnect metals, 3D NAND with more than 300 layers, high-bandwidth memory with taller stacks and hybrid bonding all add or change polishing steps. Each change requires new slurry chemistries and pad designs and creates opportunities for suppliers that can develop them quickly. Advances in particle synthesis, additive chemistry, pad microstructure and in-situ process monitoring are allowing suppliers to deliver higher selectivity and lower defectivity, while digital tools that combine tool sensor data with consumable lot data are improving process control. Technology also changes how consumables are manufactured and qualified. Suppliers are using advanced analytical methods to characterise particles and polymers, machine learning to relate formulation variables to polishing outcomes, and more automated production lines to reduce variability. These capabilities shorten development cycles and help suppliers respond to customers' requests for new formulations within the tight timelines of node development.
Environmental factors include water scarcity, wastewater treatment and waste reduction. CMP is one of the most water-intensive steps in semiconductor manufacturing, and fabs in Taiwan, Arizona and other water-stressed locations are investing in reclamation systems that must handle slurry-laden wastewater. Used pads are difficult to recycle, and chipmakers' emissions reduction targets increasingly extend to purchased materials, prompting requests for product carbon footprints and renewable energy use by suppliers. These pressures are encouraging low-abrasive formulations, concentrated products that reduce transport, longer-life pads and slurry recovery programmes. Climate-related risks also affect the chain, since extreme weather events, droughts and floods can disrupt raw-material production, logistics and fab operations, as several manufacturing regions experienced in recent years. Suppliers are responding by holding inventory in several locations and qualifying production at more than one site.
Legal factors encompass chemical regulation, intellectual property and trade law. The proposed EU universal PFAS restriction, which advanced through ECHA's scientific committees in 2026, and existing REACH authorisation requirements for certain polyurethane curatives affect formulation and sourcing decisions. In the U.S., TSCA requirements, including PFAS reporting, apply to slurry ingredients and imported articles. Intellectual property is a defining legal factor in this market, since patents on abrasives, additives and pad structures shape competition and have been the subject of litigation between suppliers. Export-control laws in the U.S. and China, and the potential for further trade measures, require suppliers to manage compliance across their global manufacturing and distribution networks. Product liability and contractual obligations are an additional legal consideration, since supply agreements typically specify quality requirements, change notification obligations and liability for yield losses caused by defective consumables, and the allocation of these risks is an important element of negotiations between suppliers and chipmakers.
Taken together, the PESTEL factors indicate that the external environment for CMP consumables is becoming more demanding in every dimension except technology demand, which remains strongly supportive. Political and legal factors are increasing the cost and complexity of serving a global customer base from a limited number of plants, environmental and social factors are adding new requirements to supplier selection, and economic factors continue to expose the market to the semiconductor cycle. Suppliers that combine technical leadership with regional manufacturing, diversified raw-material sourcing and strong regulatory capabilities are best placed to operate successfully in this environment, while smaller suppliers may find it harder to meet the full range of requirements without partnerships or consolidation.
Profiles of 33 companies operating in the CMP Slurries and Pads Market market, including revenue, employee count, and market positioning where available.
Showing 33 of 33 companies
KCTECH is the only Korean company that develops and mass-produces both chemical-mechanical planarization (CMP) equipment and the CMP slurries those tools consume. That combination gives it a hardware-plus-consumables model closer to the global equipment leaders than to most single-product Korean suppliers. In FY2025 the semiconductor business supplied about 90% of revenue: CMP polishers, wafer wet-cleaning systems, and dielectric (ceria/silica) and metal slurries. Its core customers are Samsung Electronics and SK hynix. Display equipment (wet stations, coaters, track systems) is now a shrinking legacy business. The company is debt-free with a net cash balance sheet. It is run under the control of the founding Ko family through KC Co., Ltd. Its growth case rests on more CMP steps per wafer in advanced DRAM, HBM and 3D NAND; on Korean chipmakers localising imported slurry; and on new uses for planarization in advanced packaging (hybrid bonding, glass-core substrates, build-up films). Its main exposures are the memory-capex cycle and heavy dependence on two customers. --- ### What the company does KCTECH designs, manufactures and sells front-end process equipment and process consumables for semiconductor and flat-panel-display fabs. The FY2025 business report groups its activities into two reportable segments: a Semiconductor segment (CMP equipment, wet-cleaning equipment and CMP slurry/nano-dispersion materials) and a Display segment (wet stations, coaters, track systems and related materials for OLED/LCD lines). The company describes its offering in three product families: **Semiconductor equipment:** CMP systems and wet-cleaning systems. **Display equipment:** wet stations, coaters and track systems. **Materials:** CMP slurries (dielectric slurry and additives, metal slurry) and nano-dispersions. ### Business and revenue model | Revenue stream | Nature | Characteristics | |---|---|---| | CMP equipment | Capital equipment, one-time sale per tool | Lumpy and tied to Samsung/SK hynix fab build-outs; recognised on delivery and acceptance; large single orders (e.g. KRW 69.8 bn from SK hynix in March 2026) | | Wet-cleaning equipment | Capital equipment | Same timing as fab expansions; a new family of cleaning tools is a 2026–27 growth lever | | CMP slurry and nano-dispersion | Consumable, recurring | Volume moves with wafer starts and fab utilisation rather than capex; higher-margin and more stable | | Display equipment | Capital equipment | Tied to OLED/LCD capex in Korea and China; in structural decline | | Parts, service and upgrades | Aftermarket | Not reported separately | **CMP equipment:** Nature: Capital equipment, one-time sale per tool; Characteristics: Lumpy and tied to Samsung/SK hynix fab build-outs; recognised on delivery and acceptance; large single orders (e.g. KRW 69.8 bn from SK hynix in March 2026) **Wet-cleaning equipment:** Nature: Capital equipment; Characteristics: Same timing as fab expansions; a new family of cleaning tools is a 2026–27 growth lever **CMP slurry and nano-dispersion:** Nature: Consumable, recurring; Characteristics: Volume moves with wafer starts and fab utilisation rather than capex; higher-margin and more stable **Display equipment:** Nature: Capital equipment; Characteristics: Tied to OLED/LCD capex in Korea and China; in structural decline **Parts, service and upgrades:** Nature: Aftermarket; Characteristics: Not reported separately Broker estimates put the semiconductor mix at about 60% equipment and 40% slurry. The company sells products and has no subscription or licensing revenue. ### Value-chain position and customers KCTECH is a tier-1 supplier to wafer fabs. Its customers are integrated device makers, chiefly memory makers Samsung Electronics and SK hynix. In 2025 the company said it also works with several global foundry companies, including Intel, on next-generation materials development. It reported about 25 joint development projects in progress with Samsung and about 15 with SK hynix. End-markets are DRAM (including HBM), NAND, logic/foundry, and OLED/LCD panels. ### Independent characterisation In practice KCTECH is a Korean localisation champion inside a CMP oligopoly. In equipment it is a distant third to Applied Materials, which holds more than 60% of the global CMP tool market, and Ebara. It wins share mainly inside Korean fabs, where customers value a domestic second source. In slurry its ceria-based dielectric slurry is built on its own technology, and Samsung recognised it in April 2026 for replacing imported materials. Selling both the tool and the slurry lets KCTECH co-optimise them for one customer, which is a real but narrow advantage. Earnings power swings with Korean memory capex. Slurry gives it a floor that pure equipment peers lack.
Anji Microelectronics is China's leading domestic supplier of chemical mechanical planarization (CMP) slurries and one of the few Chinese semiconductor-materials companies with high-volume sales at leading-edge logic and 3D NAND fabs. Its "3+1" technology platform covers polishing slurries, functional wet electronic chemicals (post-etch residue removers, photoresist strippers, post-CMP cleaners, etchants) and electroplating solutions and additives. The "+1" is in-house development of critical upstream raw materials such as ceria abrasives. Revenue rose from RMB 687 million in 2021 to RMB 2,504 million in 2025, with net margins of about 30%. Anji's share of the global CMP slurry market rose from about 8% in 2023 to 11% in 2024 and 13% in 2025, by the company's estimate. That makes it a credible challenger to Entegris (CMC Materials), Fujifilm, Resonac, Fujimi, Merck and DuPont/Qnity. Anji grows by being localised, customising products with fabs and moving into new chemistries. It is now preparing an A+H dual listing to fund overseas expansion, as AI-driven demand for advanced logic, memory and advanced packaging increases the number of polishing and cleaning steps per wafer. **What the company does.** Anji develops, makes and sells formulated chemical consumables used in semiconductor wafer fabrication and advanced packaging. In its annual report the company describes its main business as "the R&D and industrialisation of key semiconductor materials". Its products are "different series of chemical mechanical polishing slurries, functional wet electronic chemicals, and electroplating solutions and additives, mainly applied in integrated circuit manufacturing and advanced packaging." The company's stated strategic positioning is "rooted in China, serving the world" (立足中国,服务全球). Its development concept is "technology innovation and intellectual property," built on its "3+1" technology platform. **Business model.** Anji earns almost all its revenue from product sales of formulated consumables, which are bought again each time wafers are processed. There is no material licensing, subscription or service revenue. Revenue depends on: **Wafer starts and utilisation:** at customer fabs. Consumption scales with wafer volume. **Process-step count per wafer:** More metal layers, 3D NAND stacking, gate-all-around and backside power, and hybrid bonding all add CMP and cleaning steps. **Qualification wins:** Fab qualification takes 1–3 years per process step. Once qualified, a slurry is rarely changed during a node's life, which makes revenue sticky. The company describes its offering as localised, customised and integrated. It co-develops formulations with customers, often for a single process step, and supplies matched slurry-and-cleaner sets. **Value-chain position.** Anji sits between upstream abrasive and chemical suppliers and downstream wafer fabs and outsourced packaging companies: **Upstream:** colloidal silica, fumed silica and ceria abrasives, specialty organics, oxidisers, corrosion inhibitors, surfactants and high-purity acids. Ultra-high-purity colloidal silica still comes mainly from Japanese suppliers such as Fuso Chemical. Anji is reducing this dependence by producing its own ceria abrasives and qualifying domestic abrasive particles. **Midstream (Anji):** formulation, blending, purification, filtration, packaging and in-fab technical service. **Downstream:** foundries, logic and memory makers (DRAM and 3D NAND), specialty fabs (CIS, power, analogue, MEMS, compound semiconductor) and advanced-packaging houses (TSV, bumping, wafer-level packaging, hybrid bonding). **Customer types and end markets.** Anji's products are used in logic, memory, analogue, power devices, sensors, third-generation (wide-bandgap) semiconductors and other specialty-process chips. The company says it is in the mainstream supplier lists of leading semiconductor customers. Industry research identifies SMIC and Yangtze Memory (YMTC) as anchor customers where Anji holds the leading materials share, and TSMC among its customers. Advanced packaging (TSV, TGV, hybrid bonding, polymer planarisation) is a fast-growing second end market. **Independent characterisation.** Anji is a high-margin, R&D-heavy specialty chemical formulator. Its economics resemble the CMP slurry franchises of Cabot Microelectronics before its acquisition by Entegris: gross margins in the mid-to-high 50s, R&D at about 18% of sales, and very low selling expense (1.9% of revenue in 2025), because a few large fabs buy through long qualification cycles. Its competitive edge is local proximity, customisation speed and the policy-backed drive for supply-chain localisation in China. Its main weaknesses are heavy reliance on Chinese fab capex, some imported raw materials, and a still-small base outside China. Profitability has also become noisier because large fair-value gains on equity investments are now booked in net profit.
Fujimi Incorporated — CNM
RTX occupies a structurally advantaged position that no other prime replicates: roughly half its revenue is commercial aerospace and half defence, giving it a natural hedge across two cycles that rarely peak together — and which, unusually, are peaking together in 2026. Collins Aerospace and Pratt & Whitney are entrenched on the installed base of the global narrowbody and widebody fleet, generating decades-long, high-margin aftermarket annuities. The Raytheon segment is the Western world's dominant supplier of ground-based air and missile defence effectors — Patriot, GEM-T, AMRAAM, Standard Missile, ESSM — precisely the munitions category that European rearmament and Middle East conflict have made scarce. A record $289 billion backlog at 30 June 2026, equal to roughly three years of sales, converts that positional advantage into unusual revenue visibility. The offsetting reality is that RTX carries $37 billion of debt, an $85 billion goodwill-and-intangible balance from the merger, and the unresolved cost tail of the GTF powder-metal remediation. RTX Corporation is the world's largest aerospace and defence company by revenue, and the only prime contractor that simultaneously holds franchise positions in commercial aircraft engines, commercial aerospace systems, and ground- and sea-based integrated air and missile defence. It was created in April 2020 by the merger of Raytheon Company with the aerospace businesses of United Technologies Corporation, and it renamed itself from Raytheon Technologies to RTX in July 2023 alongside a consolidation from four operating segments to three. --- ### What the company does RTX designs, manufactures, and services aerospace and defence systems for commercial airlines, aircraft OEMs, business aviation operators, the U.S. Government (principally the Department of Defense, latterly styled the Department of War in contract announcements), and allied governments worldwide. Its FY2025 Form 10-K describes the three segments as follows: Collins Aerospace provides advanced aerospace and defence products; Pratt & Whitney supplies aircraft engines; and Raytheon delivers defensive and offensive threat detection and mitigation capabilities. The company's independent characterisation is better expressed as three distinct economic engines bolted onto one balance sheet: 1. **An installed-base annuity business (Pratt & Whitney and, to a lesser degree, Collins).** Engines and nacelles are sold at or near cost — sometimes at a loss — to win position on an airframe, after which spare parts, overhauls, and long-term service agreements generate profit for twenty to thirty years. This is why Pratt & Whitney's reported segment margin (8.3% in FY2025) looks weak against Collins (16.2%) despite comparable revenue: Pratt is still absorbing original-equipment loss content on the GTF ramp while the aftermarket annuity has yet to reach maturity. 2. **A cost-plus and fixed-price government contracting business (Raytheon, plus Collins' defence lines).** Revenue is recognised over time on the percentage-of-completion basis, which makes reported margins highly sensitive to estimate-at-completion revisions. The FY2024 $575 million charge on a terminated foreign fixed-price development contract is the canonical illustration. 3. **A component and systems supply business (Collins).** Avionics, interiors, power management, and aerostructures sold to Airbus, Boeing, Embraer, Bombardier, and defence primes, with a large parts-and-repair aftermarket layered on top. ### Revenue model and mix | Metric | FY2025 | |---|---| | Commercial share of sales | 48% | | Defence share of sales | 52% | | Products share of sales | ~74% | | Services share of sales | ~26% | | Sales to U.S. Government (excl. FMS) | $33,279m (38% of net sales) | | Total international sales | $41,312m (47% of net sales) | | Total backlog | $268bn ($161bn commercial / $107bn defence) | | Backlog expected to convert within 12 months | ~25% | Sources: FY2025 Form 10-K Item 1 (U.S. government and international sales tables, backlog); RTX 2025 Annual Report sales-mix infographic; Q3 2025 disclosure for the product/service split. Note the structural shift: U.S. Government sales fell from 46% of revenue in FY2023 to 38% in FY2025 — not because U.S. volume declined (it rose from $31.6bn to $33.3bn) but because international and commercial revenue grew far faster. This is the single most important mix fact in the company today, because international direct commercial sales carry materially better margins than U.S. cost-type work, and because European air-defence procurement is the fastest-growing pool RTX addresses. ### Value chain position and customers RTX sits at the prime and Tier-1 layers simultaneously. On F-35 it is a major subsystem supplier (F135 propulsion via Pratt; sensors and avionics via Collins) to prime contractor Lockheed Martin — a direct competitor at the enterprise level. On Patriot and SPY-6 it is the prime. On A320neo it is a propulsion and nacelle supplier to Airbus, which in March 2026 was reported to be formally seeking damages from Pratt & Whitney over GTF disruption. This simultaneous supplier/competitor/counterparty posture across the same customer set is a defining feature of RTX's commercial relationships and a recurring source of litigation and negotiation risk. **End-markets served:** commercial air transport (OE and aftermarket); regional and business aviation; rotorcraft; military fixed-wing and rotary propulsion; integrated air and missile defence; naval combat systems; precision-guided munitions; space sensing and communications; airport and airline IT infrastructure; and government training and mission services.
### Identity and listing | Item | Detail | |---|---| | Entity profiled | Illinois Tool Works Inc. (exact legal-name match; active; publicly listed). The input classification "Public company" is confirmed | | Former names | None of significance disclosed. The company has operated as Illinois Tool Works since founding. Commonly abbreviated "ITW" | | Founded | 1912, Chicago, Illinois. Incorporated 1915 (Form 10-K FY2025) | | Jurisdiction of incorporation | Delaware, USA (Form 10-K FY2025) | | IRS Employer ID | 36-1258310 | | Headquarters | 155 Harlem Avenue, Glenview, Illinois 60025, USA. Tel. (847) 724-7500 | | Exchange / ticker | New York Stock Exchange: ITW (common stock) | | Other listed securities (NYSE) | Euro notes: 0.625% due 2027 (ITW27); 3.250% due 2028 (ITW28); 2.125% due 2030 (ITW30); 1.00% due 2031 (ITW31); 3.375% due 2032 (ITW32); 3.00% due 2034 (ITW34) | | ISIN / CUSIP | US4523081093 / 452308109 | | Fiscal year end | 31 December | | Index membership | S&P 500 constituent. Fortune 300 company (company description, 2026) | ### Scale and organisation | Item | Detail | |---|---| | Employees (latest) | About 43,000 at 31 Dec 2025; about 16,000 in the U.S. (Form 10-K FY2025) | | Employee trend | About 46,000 (FY2022 release); about 45,000 (FY2023); about 44,000 (FY2024 release); about 43,000 (FY2025). This is a steady decline driven by 80/20 simplification and productivity, not by revenue contraction | | Organisation | 88 divisions in 49 countries; about 410 plants and office facilities (Form 10-K FY2025) | | Auditor | Deloitte & Touche LLP. Ratification proposed for FY2026 (2026 Proxy) | | Holders of record | About 3,957 at 31 Jan 2026 | | Website | www.itw.com / investor.itw.com | ### Market data | Item | Detail | |---|---| | Shares outstanding | 288.2 million at 31 Jan 2026 (Form 10-K). About 284 million estimated at 30 Jun 2026, after 4.3 million shares were repurchased in H1 2026 (10-Q Q2 FY2026; derived) | | Market capitalisation (current) | About $82 billion. Basis: share price of roughly $288–$295 (5 Aug 2026 close $295.06; early-September 2026 dividend yield of 2.39% implies about $288) × about 284 million shares | | Market cap at 31 Dec 2025 | About $71 billion (2026 Proxy) | | Market cap discrepancies | Third-party aggregators show $71bn–$85bn depending on date. Live verification is recommended | | 52-week range | $238.82 – $303.16 (as of Aug 2026, aggregator data) | Illinois Tool Works is a 114-year-old, Glenview-based multi-industrial manufacturer with $16.0 billion of FY2025 revenue across seven segments: - Automotive OEM - Food Equipment - Test & Measurement and Electronics - Welding - Polymers & Fluids - Construction Products - Specialty Products ITW does not compete on scale or vertical integration. Its edge is a proprietary operating system, the "ITW Business Model," built on three elements: - **80/20 Front-to-Back management**, which concentrates resources on the largest, most profitable customers and products. - **Customer-Back Innovation (CBI)**, which develops products from customer pain points rather than from a central R&D lab. **A decentralised, entrepreneurial culture:** of 88 scaled-up divisions. Since launching its Enterprise Strategy in late 2012, ITW has lifted operating margin from 15.9% to 26.3% and after-tax ROIC from 14.5% to 29.3%. It has done this while shrinking revenue through divestiture of commoditised businesses (2026 Proxy). The "Next Phase" (2024–2030) pivots the agenda from margin expansion to sustained 4%+ organic growth, powered by a 3%+ CBI revenue yield. ITW is a Dividend King, with 63 consecutive annual dividend increases. --- ### Company's own description (Form 10-K FY2025, paraphrased) ITW describes itself as a global manufacturer of a diversified range of industrial products and equipment, organised into 88 divisions operating in 49 countries. Its seven reportable segments are grouped by similar product offerings and end markets. Products are distributed mainly direct to industrial manufacturers and through independent distributors. Backlog is not considered significant because delivery periods are short and inventory turns quickly. The company names its core competitive advantage as the ITW Business Model: - 80/20 Front-to-Back process - Customer-Back Innovation - Decentralised entrepreneurial culture Primary raw materials are steel, resins and chemicals, sourced from numerous commercial suppliers. ### Business model | Revenue type | Characterisation | Evidence | |---|---|---| | Product sales: consumables | Majority of revenue. Welding filler metals; Polymers & Fluids chemicals; fasteners; Hi-Cone carriers; marking inks; test consumables; contamination-control wipes | Segment product lists (10-K FY2025) | | Product sales: capital equipment | Welding power sources; food equipment; test systems (Instron, MTS); electronic assembly equipment; line automation | Segment product lists (10-K FY2025) | | Services | Food Equipment service, maintenance and repair (service organic growth +2.8% FY2025, +4.8% FY2024); aftermarket service in Test & Measurement | 10-K FY2025 Food Equipment discussion | | Software / subscription | Test & measurement software is embedded with equipment. Not reported separately | Not publicly disclosed | | Licensing | Not material / not disclosed | Not publicly disclosed | ITW's model rests on niche leadership in fragmented, technically demanding markets. Its businesses typically hold strong positions in specialised applications where: - the product is a small share of the customer's total cost but critical to performance (e.g., an automotive fastener, a weld wire, a test frame); and - differentiation comes from engineering, application know-how, brand and service. The 80/20 discipline continually prunes low-value SKUs and customers through Product Line Simplification (PLS). PLS deliberately reduced organic revenue by about 60 basis points in FY2024, about 60 bps in FY2025, and about 60 bps in H1 FY2026, in exchange for structurally higher margins (10-K FY2025; 10-Q Q2 FY2026). **Revenue model mix.** ITW does not report a formal product/service/subscription split. The analyst characterisation is: ### Value-chain position ITW sits as a Tier-1/Tier-2 component supplier (Automotive OEM, Specialty appliance components) and as an OEM of branded equipment and consumables (Welding, Food Equipment, Test & Measurement, Construction Products, Polymers & Fluids). It typically manufactures "in the market, for the market." This localisation was cited in FY2025 as the reason ITW could largely offset U.S. tariff costs through pricing and supply-chain actions (FY2025 release; 10-K FY2025). ### Customer types and end markets | Segment | Primary end markets (10-K FY2025) | Customer type | |---|---|---| | Automotive OEM | Automotive OEMs and tiers | Global and Chinese OEMs; Tier-1 suppliers | | Food Equipment | Food service, food retail, food institutional/restaurant | Restaurant chains, independents, institutions (healthcare, education), supermarkets | | Test & Measurement and Electronics | Electronics/semiconductor, general industrial, auto OEM/tiers, energy, industrial capital goods, consumer durables | R&D labs, quality labs, semiconductor fabs, electronics assemblers | | Welding | General industrial (fabrication, shipbuilding), construction, energy, MRO, capital goods, auto | Fabricators, contractors, OEMs; heavily via distributors | | Polymers & Fluids | Automotive aftermarket, general industrial, MRO | Retail auto-care, body shops, industrial maintenance | | Construction Products | Residential construction, renovation/remodel, commercial construction | Contractors, truss fabricators, big-box retail | | Specialty Products | Food and beverage, consumer durables, airlines, general industrial, capital goods, printing/publishing | Beverage packers, appliance OEMs, airports/airlines, packaging converters | ### Independent characterisation ITW is best understood as a portfolio of about 88 mid-sized, high-return niche franchises bound together by a common management system. Corporate allocates capital. Divisions run the business. Strengths of this structure: - A low-capital-intensity, cash-generative model. Capex was 2.6% of revenue in FY2025 ($419M on $16,044M), and after-tax ROIC is about 29–31%. - Demand is diversified across consumer, industrial and capex cycles. Weaknesses of this structure: - Organic growth has historically been modest (FY2023–FY2025 averaged roughly 0–2%). - PLS creates a built-in headwind to reported growth. - The company has unusually high exposure to Detroit-3 and European auto content, short-cycle construction, and the semiconductor capex cycle. The FY2026 data, with Q2 organic growth of +4.5% and double-digit growth in Welding and Test & Measurement, is the first meaningful evidence that the CBI-driven growth pivot may be gaining traction.
84 interactive charts drawn from the CMP Slurries and Pads Market dataset — market size, each segment breakdown, and every region and country by segment. Open one to read its full data table and download it.
Global CMP Slurries and Pads Market By Region
Global CMP Slurries and Pads Market By Product Type
Global CMP Slurries and Pads Market By Application / Process Step
Global CMP Slurries and Pads Market By End User
Global CMP Slurries and Pads Market — North America by Country
Global CMP Slurries and Pads Market — North America by End User
Global CMP Slurries and Pads Market — North America by Product Type
Global CMP Slurries and Pads Market — North America by Application / Process Step
Global CMP Slurries and Pads Market — U.S. by End User
Global CMP Slurries and Pads Market — U.S. by Product Type
Global CMP Slurries and Pads Market — U.S. by Application / Process Step
Global CMP Slurries and Pads Market — Canada by End User
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