Market Size (2025)
$1.46B
Vertical: SEMIBase Year: 2025
Market Size (2025)
$1.46B
Projected (2032)
$3.17B
CAGR (2022–2032)
11.7%
Key Players
12+
Market Overview
The global known good die (KGD) testing market covers the equipment, interface hardware and test processes used to confirm that an individual semiconductor die meets its electrical, thermal and reliability specification before it is committed to a multi-die package, a stacked memory device or a power module. The market was valued at USD 1.462 billion in 2025 and is projected to reach USD 3.174 billion in 2032, expanding at a CAGR of 11.5% over 2026–2032. The absolute increase between 2025 and 2032 amounts to USD 1.712 billion, which means the market more than doubles in value over the period.
The historic series shows that the market moved from USD 1.048 billion in 2022 to USD 0.991 billion in 2023, reflecting the inventory correction that hit memory, smartphone and consumer semiconductor demand during that year, before recovering to USD 1.241 billion in 2024. The rebound was led by AI accelerator and high-bandwidth memory (HBM) programmes, where a single defective die can scrap an expensive 2.5D or 3D assembly. From the base year onward, the forecast assumes a sustained build-out of AI and high-performance computing capacity, a steady increase in the number of dies per package, and wider use of die-level screening in automotive and power electronics.
Growth is not uniform across the value chain. Testing of stacked dies and known-good stacks is the smallest test type today but the fastest growing, while wafer-level probe testing remains the foundation of every KGD flow and keeps the largest share. The demand base is concentrated in Asia Pacific, where most wafer fabrication, advanced packaging and outsourced test capacity is located, but North America, Latin America and the Middle East & Africa all grow faster than the global average as new back-end capacity is added outside the established hubs.
Key Findings
By test type, Wafer-Level Probe Testing is the largest segment, valued at USD 0.599 billion in 2025 and holding a 41.0% share. Probe testing at wafer level is the first and highest-volume screen in every KGD flow, since it is applied to all dies on the wafer before any are singulated or assembled. Stacked-Die / Known-Good-Stack Testing is the fastest-growing segment, with a CAGR of 17.7% over 2026–2032, rising from USD 0.234 billion in 2025 to USD 0.752 billion in 2032. Its growth follows the move to taller HBM stacks and to logic-on-logic and memory-on-logic integration, where each partial stack must be verified before the next layer is bonded.
By die / device type, Logic & AI Processors form the largest segment at USD 0.556 billion in 2025, a 38.0% share, reflecting the high test content of large GPU, accelerator and server CPU dies. HBM & DRAM Memory is the fastest-growing segment, with a CAGR of 14.8%, expanding from USD 0.351 billion in 2025 to USD 0.940 billion in 2032 as each HBM stack requires screening of the base logic die and every DRAM core die.
By application, AI & HPC / Data Center is both the largest and the fastest-growing segment. It accounts for USD 0.497 billion in 2025, or 34.0% of the market, and grows at a CAGR of 14.5% to USD 1.301 billion in 2032. Automotive is the second-fastest application, at a CAGR of 12.8%, supported by safety-related screening requirements and the transition to silicon carbide and gallium nitride power modules.
By end user, OSATs are the largest segment, with USD 0.556 billion in 2025 and a 38.0% share, because outsourced assembly and test companies perform most wafer sort, die-level test and burn-in for fabless chip companies. Foundries are the fastest-growing end user, with a CAGR of 13.1%, as foundry-operated advanced packaging lines take on more of the test work associated with chip-on-wafer-on-substrate and similar integration flows.
By region, Asia Pacific is the leading market, valued at USD 1.038 billion in 2025 and accounting for 71.0% of global value. Latin America is the fastest-growing region, with a CAGR of 13.0% over 2026–2032, although it starts from a small base of USD 0.031 billion in 2025.
At the country level, Rest of Asia Pacific is the largest country-level entry, with USD 0.586 billion in 2025, equal to 40.1% of the global market; China is the largest individually reported country, at USD 0.275 billion, or 18.8% of global value. India is the fastest-growing country, with a CAGR of 17.0%, increasing from USD 0.052 billion in 2025 to USD 0.159 billion in 2032.
Segmentation Summary
The market is analysed across four product and demand segmentations (test type, die / device type, application and end user) and across five regions and twenty country-level entries. The segmentation shows a consistent pattern: the segments linked to AI computing and memory stacking lead growth, while the segments linked to mature consumer devices and single-die products grow more slowly. Wafer-level probe testing, logic and AI processors, the AI and HPC application and OSATs hold the largest positions in their respective segmentations, which reflects the concentration of current KGD spending on high-value processors tested by outsourced providers.
The fastest-growing segments point to where test intensity is rising fastest. Stacked-die testing, HBM and DRAM memory, AI and HPC applications and foundries all relate to the same structural change: more silicon is being integrated into a single package, and the cost of discovering a defect after assembly is rising in step. Table 1.1 summarises the largest and fastest-growing segment in each segmentation, together with the leading and fastest-growing region and country.
The summary also shows where growth and size diverge. In the application segmentation, the same segment leads on both measures, which concentrates the market's exposure to AI data-centre investment cycles. In the end-user segmentation, OSATs lead on size but foundries grow faster, which indicates a gradual shift of test value towards foundry-run advanced packaging. In the regional and country rows, the largest entries are in Asia Pacific, whereas the fastest-growing entries are emerging back-end locations, which signals that new test capacity is being added in regions with a smaller installed base.
Regional and Country Highlights
Asia Pacific dominates the market because it hosts the bulk of the world's wafer fabrication, HBM production, advanced packaging and outsourced test capacity. The region is projected to grow from USD 1.038 billion in 2025 to USD 2.243 billion in 2032 at a CAGR of 11.4%. Within the region, Rest of Asia Pacific, which includes the major memory and foundry centres outside China, India and Japan, is the largest entry at USD 0.586 billion in 2025. China follows at USD 0.275 billion and grows at a CAGR of 12.6%, supported by domestic capacity expansion in logic, memory and power devices. Japan, at USD 0.125 billion in 2025, grows at a CAGR of 8.9%, while India is the fastest-growing country in the study, with a CAGR of 17.0%, as its first outsourced assembly and test facilities and assembly, test, marking and packaging plants enter operation.
North America is the second-largest region, valued at USD 0.222 billion in 2025 and forecast to reach USD 0.516 billion in 2032 at a CAGR of 12.6%. The U.S. accounts for USD 0.191 billion of the regional value in 2025 and grows at a CAGR of 12.7%, driven by AI accelerator design activity, new domestic advanced packaging investment and the reshoring of test capacity. Mexico grows at a CAGR of 13.2% from a smaller base, linked to its role in automotive and industrial electronics assembly, while Canada grows at 9.2%.
Europe is valued at USD 0.137 billion in 2025 and is projected to reach USD 0.265 billion in 2032, a CAGR of 9.6%. Germany is the largest European country at USD 0.041 billion in 2025, reflecting its concentration of automotive and power semiconductor production, while Spain is the fastest-growing country in the region at a CAGR of 10.8%. Europe's demand profile is weighted towards power devices, sensors and automotive-grade screening rather than AI memory stacks.
Latin America and the Middle East & Africa are small but fast-growing. Latin America rises from USD 0.031 billion in 2025 to USD 0.073 billion in 2032 at a CAGR of 13.0%, with Brazil the largest and fastest-growing country in the region at a CAGR of 13.2%. The Middle East & Africa grows from USD 0.034 billion to USD 0.077 billion at a CAGR of 12.4%; Saudi Arabia is the fastest-growing country in that region at 16.2%, followed by the UAE at 15.0%, both linked to national technology programmes and AI data-centre investment.
Competitive Landscape Summary
The KGD testing market is moderately consolidated. A small group of automatic test equipment (ATE), probe card and wafer prober suppliers supplies most of the critical hardware, and their positions are reinforced by long qualification cycles at chip companies, OSATs and foundries. Advantest and Teradyne lead in test systems for logic, AI and memory devices; FormFactor and Technoprobe lead in probe cards, including the fine-pitch and high-parallelism cards needed for HBM and AI processors; and Tokyo Electron is a leading supplier of wafer probers. Micronics Japan, Tokyo Seimitsu, Cohu and Chroma ATE form a group of challengers with strong positions in specific steps such as memory probe cards, probers, handlers, inspection and system-level test. Aehr Test Systems, MPI Corporation and Japan Electronic Materials hold specialised positions in wafer-level burn-in and in probe cards for particular device classes.
Competition increasingly takes the form of partnerships and equity links rather than stand-alone product rivalry. Teradyne completed a minority investment in Technoprobe on 27 May 2024, in a transaction that also moved Teradyne's device interface business to Technoprobe. In January and February 2025, Advantest took non-controlling equity stakes in FormFactor and Technoprobe and agreed a partnership with Micronics Japan. In December 2025, Advantest and Tokyo Seimitsu announced the joint development of a die-level prober for AI and HPC devices, and in June 2026 Teradyne and Tokyo Electron introduced an integrated KGD test cell for AI and data-centre chips. These moves show that suppliers are assembling complete test cells, combining tester, prober, probe card and thermal control, because chip companies want a single accountable solution for screening high-power dies.
Challenges and Opportunities
The main challenge for the market is cost. KGD flows add test insertions, probe cards and burn-in time that would not be needed for a die destined for a conventional single-die package, and test cells for high-power AI dies require active thermal control and very high current delivery. The economic case is strong for expensive multi-die packages, but weaker for low-cost consumer and sensor devices, which limits the speed at which full KGD screening spreads beyond high-value products. A second challenge is technical: probing fine-pitch micro-bumps and hybrid-bonding pads without damaging them, and reproducing at wafer level the thermal and timing conditions a die will see in the final package, remain difficult. Test escapes that appear only after stacking continue to drive yield losses. Trade restrictions add a further layer of complexity, as export controls on advanced computing, HBM and some semiconductor tools affect where equipment can be shipped and serviced.
Opportunities are concentrated in three areas. First, wafer-level burn-in and high-power screening for AI processors is moving from evaluation to production, as shown by orders placed with Aehr Test Systems in 2025 and 2026 by AI processor suppliers. Second, the regionalisation of back-end capacity in the U.S., Japan, India, Europe and Southeast Asia is creating demand for new test cells and probe card supply close to new packaging lines. Third, test data analytics, adaptive test and outlier screening allow suppliers and OSATs to offer value-added services that reduce test time while improving the quality of dies shipped into stacks.
Future Outlook
The market is expected to grow in each forecast year, from USD 1.652 billion in 2026 to USD 3.174 billion in 2032. The growth outlook rests on continued investment in AI and HPC infrastructure, higher HBM stack counts with the transition to HBM4 and its successors, and the wider adoption of chiplet architectures that rely on dies from several sources being assembled into one package. Over the forecast period, Stacked-Die / Known-Good-Stack Testing is projected to gain share from Singulated Die-Level Testing and Wafer-Level Probe Testing, while HBM & DRAM Memory and AI & HPC / Data Center increase their weight in the device and application mixes.
Technology change will shape how value is captured. Die-level probers and handlers with active thermal control, wafer-level burn-in for high-power dies, design-for-test architectures for chiplets and analytics-driven test flows are all likely to become standard elements of KGD programmes. Suppliers able to deliver integrated test cells, rather than individual tools, are best placed to benefit. At the regional level, Asia Pacific will remain the centre of the market, while new capacity in North America, India and the Middle East gradually broadens the geographic base of KGD testing.
The Known Good Die Testing Market market is projected to grow at a CAGR of 11.7% from 2022 to 2032.
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View Subscription PlansDefinition
Known good die (KGD) testing is the set of electrical, thermal and reliability screening steps that confirm an unpackaged semiconductor die meets its full functional and parametric specification before it is committed to a multi-die assembly. The term originated in the multichip module and hybrid microelectronics sector, where a single faulty bare die could scrap an entire substrate carrying several expensive components. It has since become a central discipline in heterogeneous integration, where logic chiplets, high-bandwidth memory stacks, power transistors and sensors are combined in 2.5D interposer packages, 3D stacks, fan-out packages and power modules. In each case the economic logic is the same: the cost of a defect rises sharply with every assembly step, so the die must be proven good while it is still cheap to discard.
KGD testing differs from conventional wafer sort and final test in its objective. Traditional wafer sort was designed as a coarse filter that removed gross failures, with the packaged-part final test carrying the burden of full speed, full temperature and reliability screening. A die destined for a chiplet package or a memory stack never passes through an individual package of its own, so the screening that final test once performed must be pulled forward to the wafer or bare-die stage. KGD testing therefore aims for test coverage, temperature range and early-life failure screening comparable to packaged-part test, applied to a device that is fragile, has dense and fine-pitch contact points and must remain undamaged for subsequent bonding.
How KGD Testing Works
The first stage is wafer-level probe testing. A wafer prober positions each die under a probe card whose needles, MEMS spring contacts or vertical probes touch the bond pads or micro-bumps, while an automated test equipment (ATE) system applies test patterns, measures parametric values and records pass or fail results per die. For KGD purposes this step is extended well beyond basic continuity and leakage checks: probe cards must support high pin counts and fine bump pitches, test programs exercise at-speed logic and memory functions, and hot and cold chuck temperatures are used to catch temperature-sensitive defects. Results are written into an electronic wafer map that follows the die through the rest of the supply chain.
The second stage is burn-in and stress screening, which accelerates latent defects so that weak dies fail before assembly rather than in the field. Wafer-level burn-in applies elevated voltage and temperature to all dies on a wafer simultaneously through full-wafer contactors, while die-level and carrier-based burn-in stress individual dies held in temporary carriers. High-temperature operating life stress, dynamic burn-in with toggling patterns and high-voltage gate stress for power transistors all fall within this stage. The goal is to remove early-life failures that a short probe test would not reveal.
The third stage is singulated die-level testing. After dicing, individual dies are picked, placed in temporary carriers, sockets or die-level probers and retested, often at final-test conditions that are difficult to apply on a full wafer. This step verifies that the die survived dicing, thinning and handling, permits tri-temperature testing with tighter thermal control around each die, and supports full-power functional testing of large processors whose heat output exceeds what a wafer chuck can dissipate across many active dies.
The fourth stage is stacked-die or known-good-stack (KGS) testing. Where dies are bonded into vertical stacks, as in high-bandwidth memory or 3D logic-on-logic designs, the partially or fully built stack is tested through its base die or test access structures before it is mounted on an interposer next to the host processor. Through-silicon via continuity, inter-die interface timing, repair of faulty memory cells using built-in redundancy and thermal behaviour of the whole stack are verified at this point. Standards-based access architectures, including IEEE 1838 for 3D stacked integrated circuits and the test provisions in the Universal Chiplet Interconnect Express specification, give testers a defined path into stacked and chiplet-based devices.
Across all four stages, design-for-test features inside the die, such as scan chains, memory built-in self-test, boundary scan to IEEE 1149.1 and embedded instrument networks to IEEE 1687, determine how much coverage can be achieved through a limited number of probe contacts. Test data analytics then link results from each stage so that marginal dies can be binned, retested or excluded based on statistical outlier screening.
Products and Services Covered
The market covers the equipment, consumables and services used specifically to establish known good status at the die and stack level. This includes ATE systems and test cells configured for wafer-level and die-level KGD screening; wafer probers and die-level probers with high-power thermal control; probe cards designed for fine-pitch micro-bump and pad contact, including advanced MEMS and vertical probe cards for memory and logic; wafer-level and die-level burn-in systems together with full-wafer contactors and temporary die carriers; die handlers, pick-and-place and singulated-die test sockets; stacked-die and known-good-stack test solutions; and outsourced KGD test services provided by OSATs, foundries and specialist test houses. Test software, test program development and yield analytics are included where they are sold as part of a KGD test solution.
Consumables form a distinct and recurring part of this scope. Probe cards wear with every touchdown and must be refurbished or replaced, and each new device generation with a different bump layout or pitch requires a new card design. Full-wafer contactors for wafer-level burn-in and the temporary carriers used to hold singulated dies are similarly device-specific. As a result, a substantial share of KGD spending follows the cadence of new product introductions by chip designers rather than the purchase cycle for capital equipment alone, and suppliers of these interface products work closely with test engineering teams from the early design phase.
Services are included where they are delivered as KGD screening. This covers the wafer-level probe, burn-in, die-level retest and stack test performed by OSATs and specialist test houses on behalf of fabless companies and memory makers, as well as the KGD operations that foundries offer as part of integrated advanced packaging flows. Engineering services for test program conversion and probe card qualification are counted when they are contracted for a specific KGD flow.
Exclusions
The study excludes final test of conventionally packaged single-die devices, board-level and system-level test of finished modules and servers, and in-line process metrology and defect inspection performed during wafer fabrication. Design-for-test intellectual property licensed to chip designers, electronic design automation software sold independently of test operations and general-purpose laboratory instruments used for device characterisation are also excluded. Optical inspection is considered only where it forms part of an integrated KGD flow for stacked memory or chiplet dies; stand-alone inspection tools fall outside the scope. Spare parts and service contracts for equipment primarily used in packaged-part final test are not counted. Where a single ATE platform is used for both KGD screening and conventional final test, only the portion of its capacity allocated to bare-die and stack screening is attributed to this market.
Why KGD Testing Matters
The relevance of KGD testing has grown with the shift from monolithic system-on-chip designs to chiplets and stacked memory. A modern AI accelerator package combines one or more large compute dies with multiple high-bandwidth memory stacks on a silicon interposer, and the assembled package is far more valuable than any individual component. Because yield compounds across every die in a package, a small escape rate at the die level can translate into a large loss at the package level. KGD testing converts this compounding risk into a controllable screening cost, which is why test strategy now forms part of package architecture decisions at the design stage rather than being added after tape-out.
KGD testing also changes where test value sits in the supply chain. In a conventional flow, most test spending occurred after packaging at the OSAT. In a chiplet or stacked-memory flow, more of the screening moves to the wafer and bare-die stages, which are increasingly performed by foundries, memory manufacturers and specialist test houses before dies are shipped to the assembly site. Test data must therefore travel with each die across company boundaries, and responsibility for escapes must be agreed contractually between the die supplier and the package integrator.
The same principle applies outside computing. Silicon carbide and gallium nitride power transistors are mounted in multi-die power modules for electric vehicle traction inverters and industrial drives, where one weak die can disable the module. Radio-frequency front-end modules for smartphones and MEMS sensor packages in automotive and medical systems also combine several bare dies, each of which must be verified before assembly.
Variation by Device Type
The form that KGD testing takes depends heavily on the device being screened. Logic and AI processor dies carry very high transistor counts and draw large currents when exercised at speed, so the main difficulties are thermal: the prober or die-level handler must remove heat fast enough to keep junction temperature within a narrow window while the die runs realistic workloads. Test programs for these dies rely on scan compression, structural at-speed tests and on-die monitors, and they are often supplemented by burn-in to screen early-life failures in large compute dies whose failure would scrap a multi-die package.
Memory dies follow a different pattern. DRAM core dies destined for high-bandwidth memory stacks are probed at wafer level with high-parallelism probe cards that contact many dies in a single touchdown, and their redundant rows and columns are repaired using laser or electrical fuses before stacking. The completed stack is then retested through its base die so that faults introduced by thinning, bonding or through-silicon via formation are identified and, where possible, repaired with spare resources.
Radio-frequency and mixed-signal dies require probe cards and interfaces that preserve signal integrity at high frequencies and allow precise analogue measurements, which places demands on probe tip geometry, impedance-controlled paths and calibration. Power devices in silicon carbide, gallium nitride and silicon need high-voltage and high-current testing at the bare-die level, including avalanche, short-circuit and gate-stress screening, and they are vulnerable to arcing and probe damage unless test cells limit energy during a failure event. MEMS and sensor dies add physical stimulus to electrical test, for example pressure, motion or acoustic input, and they frequently require die-level handling because their moving structures are sensitive to contamination and mechanical shock.
These differences explain why the market is served by a mix of general-purpose ATE platforms and specialised probers, contactors and burn-in systems, and why test cell configuration, rather than any single instrument, determines the quality of a KGD screen.
Scope of the Study
This study assesses the global known good die testing market across four product and demand segmentations and one geographic segmentation, all taken directly from the underlying market dataset. The market is analysed by Test Type, covering Wafer-Level Probe Testing, Burn-in & Stress Screening, Singulated Die-Level Testing and Stacked-Die / Known-Good-Stack Testing. It is analysed by Die / Device Type, covering Logic & AI Processors, HBM & DRAM Memory, RF & Mixed-Signal Devices, Power Devices (SiC, GaN & Si) and MEMS & Sensors.
The market is further analysed by Application, covering AI & HPC / Data Center, Smartphones & Mobile, Automotive, Telecom & Networking, Industrial & Medical and Consumer Electronics, and by End User, covering OSATs, Foundries and IDMs. The end-user view reflects who purchases KGD test equipment and services or performs KGD screening in-house: outsourced semiconductor assembly and test providers, wafer foundries that offer integrated advanced packaging, and integrated device manufacturers that design, fabricate and test their own devices.
Geographically, the study covers five regions and their constituent countries. North America includes the U.S., Canada and Mexico. Europe includes Germany, the U.K., France, Italy, Spain and Rest of Europe. Asia Pacific includes China, India, Japan and Rest of Asia Pacific. Latin America includes Brazil, Argentina and Rest of Latin America. Middle East & Africa includes the UAE, Saudi Arabia, South Africa and Rest of MEA. Each region and country is analysed by the same four segmentations used at the global level, so that regional demand patterns can be compared on a consistent basis.
The study covers a historic period from 2022 to 2024, uses 2025 as the base year and provides forecasts for each year from 2026 to 2032. Growth over the forecast horizon is expressed as a compound annual growth rate for 2026–2032. All market values are stated in USD Billion at three decimal places, and shares are stated as percentages of the relevant total for 2025.
The four segmentations are complementary rather than overlapping views of the same spending. Test Type describes the screening step at which value is created, Die / Device Type describes what is being tested, Application describes the end market for which the tested die is ultimately destined, and End User describes the organisation that performs or purchases the testing. A single probe card used to screen DRAM core dies for an AI accelerator package, for example, is counted under Wafer-Level Probe Testing, HBM & DRAM Memory, AI & HPC / Data Center and the relevant end user, which allows the same market to be examined from technology, product and customer perspectives without changing its total.
Market value is measured at the level of spending on KGD testing activity, including the purchase of dedicated equipment and consumables and the value of outsourced KGD test services, attributed to the region in which the testing is performed. The study does not double count equipment purchased by a test service provider and the services that provider subsequently sells.
Research Objectives
The study was designed to meet the following objectives.
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View Subscription PlansOverview of the Research Process
The research process combined structured secondary research, primary interviews across the KGD testing value chain, bottom-up and top-down market modelling, and a final triangulation step in which independent estimates were reconciled into a single dataset. The work was organised in four phases. The first phase defined the market boundary, separating KGD screening from conventional wafer sort, packaged-part final test and system-level test, and fixed the segmentation by test type, die and device type, application, end user, region and country. The second phase built a fact base from published and proprietary sources covering semiconductor production, advanced packaging capacity, test equipment shipments and supplier financial disclosures. The third phase tested and refined that fact base through interviews with equipment suppliers, probe card makers, test service providers and chip companies. The fourth phase converted the validated inputs into market values for the historic years, the base year and the forecast period.
Because KGD testing is not reported as a separate line item by most suppliers or by industry statistics bodies, the research placed particular weight on understanding how test activity is distributed across the production flow. Analysts mapped the typical test sequence for each device category, from wafer-level probe and burn-in through singulated die retest and stack test, and estimated the portion of each supplier's test-related revenue that relates to bare-die and stack screening rather than to packaged-part test. This mapping was reviewed repeatedly during the primary research phase, since the boundary between wafer sort and KGD screening has moved as chiplet and high-bandwidth memory adoption has increased.
Quality control was applied throughout. Each segment estimate was checked for internal consistency, so that segment values sum to the total for every year and every region, and every regional total reconciles with the global market. Outlier inputs were investigated rather than averaged away, and the final dataset was reviewed by analysts who had not been involved in building the individual segment models.
Secondary Research
Secondary research established the baseline for production volumes, capacity, technology adoption and supplier activity. Industry associations were a primary starting point. SEMI publications on semiconductor equipment billings, back-end equipment and fab capacity provided context on spending patterns across test, assembly and packaging. The Semiconductor Industry Association and the World Semiconductor Trade Statistics organisation provided device-level sales data by product category and region, which was used to estimate the flow of logic, memory, analogue, power and sensor dies through the production system.
Standards bodies and technical communities supplied the technical framework for segmenting the market. JEDEC standards for high-bandwidth memory, including the HBM4 specification published in April 2025, and JEDEC reliability and qualification documents such as JESD47 and the JESD22 test methods, informed the analysis of memory test flows and burn-in practice. IEEE standards for test access, including IEEE 1149.1, IEEE 1687 and IEEE 1838 for stacked integrated circuits, together with the Universal Chiplet Interconnect Express specification, were reviewed to understand how test access is evolving for chiplets. Proceedings from the SWTest probe technology conference and the International Test Conference offered detailed engineering evidence on probe card technology, fine-pitch micro-bump probing, high-power thermal control and wafer-level burn-in.
Company disclosures were an important source of supply-side information. Annual reports, Form 10-K and 10-Q filings, investor presentations and earnings call commentary from test equipment and interface suppliers, including Advantest, Teradyne, FormFactor, Technoprobe, Cohu, Aehr Test Systems, Chroma ATE, Micronics Japan, Tokyo Electron and Tokyo Seimitsu, were reviewed for segment revenue, product launches, customer concentration and commentary on high-bandwidth memory and AI processor demand. Disclosures from OSATs, foundries and memory manufacturers were used to track advanced packaging and test capacity additions.
Government and regulatory sources provided information on policy, trade controls and incentives. These included export control rules issued by the U.S. Bureau of Industry and Security, CHIPS for America programme announcements from the National Institute of Standards and Technology, documents from the European Commission and national bodies implementing the European Chips Act, policy material from Japan's Ministry of Economy, Trade and Industry, and approvals published by India's Ministry of Electronics and Information Technology and the India Semiconductor Mission. Customs and trade statistics were used to trace flows of test equipment and probe cards between producing and consuming countries.
Trade journals and specialist media covering semiconductor test, packaging and manufacturing were used to track product introductions, partnerships and capacity announcements, while paid industry databases supplied company financials, merger and acquisition records and patent information. All secondary inputs were dated, and newer sources were preferred where figures differed.
Primary Research
Primary research was used to validate secondary findings, add detail at the level of individual test steps and device classes, and capture forward-looking views on technology and demand. Interviews were conducted through a combination of in-depth telephone and video discussions and structured questionnaires, and they were carried out iteratively so that early findings could be tested in later conversations.
On the supply side, respondents included product managers and business development executives at ATE suppliers, wafer and die-level prober manufacturers, probe card and contactor producers, burn-in system makers and die handler suppliers. Discussions with these respondents focused on installed base, shipment trends by device type, average selling prices of test cells and probe cards, replacement cycles for consumables, and the share of their activity linked to bare-die and stacked-die screening. Engineering staff at these companies were consulted on technical developments such as fine-pitch micro-bump probing, high-power thermal management and full-wafer burn-in contactors.
On the demand side, respondents included test engineering managers, operations heads and procurement staff at OSATs, foundries offering advanced packaging, memory manufacturers, fabless AI processor and networking chip designers, power semiconductor producers and automotive tier-one suppliers. These interviews explored KGD test strategy, the balance between in-house and outsourced test, typical test insertions by device category, target escape rates, and investment plans for test capacity. Independent consultants and former industry executives were also interviewed to provide a cross-company perspective.
The objectives of primary research were to confirm the market definition and segment boundaries, validate base-year estimates by segment and region, obtain qualitative and quantitative inputs for the forecast, and identify the competitive positioning of leading suppliers. Respondent views were cross-checked against each other and against secondary evidence, and points of disagreement were resolved through follow-up discussions.
Particular attention was given to topics where published information is thin. These included the proportion of high-bandwidth memory core dies that receive burn-in before stacking, the extent to which AI processor dies are retested in singulated form at full power, the share of power device dies screened at bare-die level before module assembly, and the division of KGD work between foundries, memory makers and OSATs in chiplet supply chains. Interviews in each of the five regions were used to understand local differences in test practice, such as the concentration of high-volume memory and logic screening in East Asia and the emphasis on automotive and power device testing in Europe.
Market Size Estimation
The base-year market was estimated using both bottom-up and top-down approaches, which were then reconciled. The bottom-up approach started from die volumes. For each device category, analysts estimated the number of dies that undergo KGD screening, distinguishing dies that enter 2.5D and 3D packages, high-bandwidth memory stacks, power modules, radio-frequency modules and multi-die sensor packages from dies that follow a conventional single-package flow. These volumes were combined with estimates of the number of test insertions per die, the test time per insertion and the effective cost per unit of test time on the relevant test cell, including depreciation of equipment, probe card and contactor consumption, and operating costs. The result was a value of KGD test activity by test type and device category.
A parallel bottom-up view was built from the installed base of equipment. Analysts estimated the number of ATE systems, probers, burn-in systems and handlers deployed in KGD flows, their utilisation and replacement cycles, and the annual consumption of probe cards and full-wafer contactors. Probe card consumption was modelled from new device introductions, card lifetime in touchdowns and refurbishment rates, since it is a large recurring element of KGD spending.
The top-down approach began with the total semiconductor test equipment and test services market, derived from supplier revenue and industry association data. Shares attributable to wafer-level and die-level screening were estimated from supplier disclosures and interviews, and the KGD portion was then isolated by removing conventional wafer sort for single-package devices and packaged-part final test. The resulting total was allocated across regions according to the location of test operations rather than the headquarters of the chip designer.
Data triangulation compared the bottom-up and top-down results at the global, segment and regional levels. Where the two approaches diverged, analysts reviewed the assumptions on test insertions, test time, utilisation and the KGD share of supplier revenue until the estimates converged within an acceptable range. Primary respondents were then asked to review the reconciled figures for their area of expertise.
Forecasting Methodology
The forecast was developed from the base-year estimates using a driver-based model. For each device category and application, analysts projected the number of dies requiring KGD screening by linking it to the expected adoption of chiplet-based processors, high-bandwidth memory generations, silicon carbide and gallium nitride power modules, multi-die radio-frequency front ends and advanced sensor packages. Assumptions on test intensity were then applied, reflecting changes in test insertions per die, test time per insertion and the move of burn-in and full-temperature test from the package stage to the wafer and die stages.
The factors considered included semiconductor demand by end market, capacity additions in advanced packaging and memory stacking, the pace of transition to new HBM generations and larger AI accelerator packages, electrification of vehicles, the rollout of 5G and data-centre networking upgrades, the pricing of test equipment and probe cards, productivity gains from higher test parallelism, and policy influences such as export controls and regional incentive programmes. Each factor was assessed for its direction and strength over the forecast period, and the scores were reflected in segment-level growth assumptions.
Regional forecasts were built by allocating projected test activity according to announced and expected capacity for wafer fabrication, advanced packaging and test, taking account of the relocation of back-end operations toward the U.S., Japan, India and Southeast Asia. The results were checked against supplier guidance and interview views, and sensitivity tests were run on the main assumptions, particularly AI accelerator volumes and HBM test intensity, to confirm that the forecast remained plausible under alternative scenarios. Compound annual growth rates were calculated for 2026–2032.
Segment forecasts were also checked against one another. Growth in Stacked-Die / Known-Good-Stack Testing, for example, was tied to the projected number of HBM stacks and 3D logic stacks, and it was reconciled with the growth assumed for HBM & DRAM Memory and AI & HPC / Data Center so that the same underlying die volumes produced consistent results across the test type, device type and application views. End-user forecasts were derived from the expected division of KGD activity between OSATs, Foundries and IDMs, taking into account foundry-integrated advanced packaging programmes and the decisions of integrated device manufacturers to outsource or retain test operations.
Base Year and Forecast Period
The study uses 2025 as the base year, which is the most recent full year for which supplier disclosures, trade data and interview inputs were available at the time of analysis. Historic market values are provided for 2022, 2023 and 2024 to show how the market developed through the semiconductor inventory correction and the subsequent recovery led by AI-related demand. The forecast period runs from 2026 to 2032, with values provided for each year, and growth over this horizon is expressed as a compound annual growth rate for 2026–2032.
All values are expressed in USD Billion at current prices, shown to three decimal places. Revenue reported in other currencies, including Japanese yen, euro, New Taiwan dollar, Korean won and Chinese yuan, was converted into U.S. dollars using average annual exchange rates for each historic year, and forecast values assume exchange rates held at base-year averages. Market shares are calculated on 2025 values.
The choice of 2025 as the base year reflects the point at which AI-related demand for wafer-level probe, burn-in and stacked memory testing had become a clearly established part of the market, following the weaker conditions experienced across parts of the semiconductor industry earlier in the historic period. The seven-year forecast horizon to 2032 is long enough to capture several generations of high-bandwidth memory, the broader spread of chiplet-based processors into networking, automotive and edge computing, and the commissioning of advanced packaging and test capacity announced under regional incentive programmes. Values for each year are reported so that readers can examine the trajectory of the market rather than relying solely on the endpoints.
Base Year
2025
Historical Period
2022 – 2024
Forecast Period
2026 – 2032
Primary Interviews
150+
Historical data (2022–2025) and forecast period (2025–2032)
Our research process spans primary interviews with industry stakeholders combined with comprehensive secondary data analysis, validated through triangulation across multiple independent sources.
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The KGD testing market is moderately consolidated at the equipment level and more fragmented at the level of interface hardware and services. Automatic test equipment for logic, AI and memory devices is supplied mainly by two companies, Advantest and Teradyne, whose platforms are installed at nearly every major OSAT, foundry and IDM. Wafer probers come from a small group of Japanese and Taiwanese suppliers, led by Tokyo Electron and Tokyo Seimitsu. Probe cards, which are the most device-specific part of the test cell, are supplied by a wider group that includes FormFactor, Technoprobe, Micronics Japan, Japan Electronic Materials and MPI Corporation, alongside regional suppliers in China and South Korea. Burn-in, handling, contacting and inspection are served by companies such as Aehr Test Systems, Cohu and Chroma ATE.
Competition is based on technical capability, qualification history and the ability to support customers during the ramp of new devices, rather than on price alone. A new AI processor or HBM generation requires a tester configuration, a probe card design and a thermal solution that work together, and chip companies typically qualify only a few suppliers for each element. Once a supplier is qualified, it tends to remain in place for the life of a product family, which gives incumbents an advantage. At the same time, each device generation reopens the competition, because new pitches, power levels and stack heights require new solutions.
A defining feature of the market since 2023 has been the formation of alliances between suppliers of different parts of the test cell. Equity investments, joint development agreements and integrated test cell offerings have linked testers with probe cards and probers, reflecting customer demand for complete, pre-validated KGD solutions for high-power dies.
Key Player Positioning
Leaders are the companies that supply the core of most KGD test cells and hold strong positions across several device types and regions. Advantest and Teradyne lead in test systems for logic, AI processors and memory, with broad installed bases, global service networks and dedicated products for HBM and stacked devices. FormFactor and Technoprobe lead in advanced probe cards: FormFactor has a strong position in DRAM and HBM probe cards and in engineering probe systems, while Technoprobe has grown through high-performance logic and AI probe cards and expanded its scope by acquiring Teradyne's device interface business in 2024. Tokyo Electron is a leader in wafer probers, with its Prexa platform used in high-volume probe testing and now in integrated KGD cells.
Challengers hold strong positions in specific steps or device classes and are expanding their scope. Micronics Japan is a major supplier of memory probe cards and has strengthened its position through its 2025 partnership with Advantest. Tokyo Seimitsu is the second major Japanese prober supplier and is co-developing a die-level prober with Advantest. Cohu supplies test handlers, contactors and inspection systems, and has extended into silicon carbide burn-in and HBM inspection. Chroma ATE supplies SoC, power and system-level test solutions and has a strong customer base in Taiwan and China.
Niche players focus on particular technologies where they hold specialised expertise. Aehr Test Systems is a specialist in wafer-level burn-in for silicon carbide and, increasingly, for AI processors, complemented by package-level burn-in from the Incal Technology acquisition. MPI Corporation supplies probe cards and probers, with a strong position among Taiwanese customers, and Japan Electronic Materials specialises in probe cards for memory devices. These companies are important in their segments but lack the breadth of portfolio and global reach of the leaders.
Competitor Dashboard
The competitor dashboard rates each company on four dimensions: the breadth of its KGD-relevant product portfolio, its regional presence, the depth of its strategic alliances and its industry experience. Ratings are qualitative assessments and are consistent with the leader, challenger and niche grouping. Table 11.1 presents the ratings for the twelve companies covered.
The competitive structure of known good die testing reflects high technical barriers, a concentrated supplier base, and a customer base that is itself concentrated in a few large manufacturers and service providers. The ratings that follow are assessed for the equipment, probe card and burn-in suppliers that make up the market.
Taken together, the forces describe a market in which profitability is supported by technical barriers and recurring consumable revenue but constrained by powerful, concentrated customers. The balance between these influences differs by segment: wafer-level probe testing and known-good-stack testing of HBM are most exposed to buyer concentration, while burn-in and stress screening for AI processors and silicon carbide dies remains a developing field where suppliers have more room to shape specifications. Singulated die-level testing sits between the two, because it requires new handling and thermal capability that only a few suppliers can deliver, yet it serves customers who can compare competing integrated test cells directly.
Threat of New Entrants: Low
The threat of new entrants is Low. A new tester or prober supplier must match decades of accumulated know-how in pin electronics, timing accuracy, thermal control and wafer handling, and must then pass long qualification cycles at foundries, IDMs and OSATs that will not risk yield on unproven equipment. Customers build test programs, correlation data and operator training around a specific platform, and switching to a new platform means re-qualifying test content for every device in production. This installed-base effect protects established tester families and makes it very difficult for an entrant to gain a first production slot.
Probe cards look more accessible because each card is a custom product and regional suppliers exist in Taiwan, South Korea and China. However, the cards needed for HBM, AI processors and stacked dies require MEMS probe fabrication at very fine pitch, high current per probe and very tight planarity across large areas, and a single card can carry tens of thousands of probes. Capital requirements for MEMS lines, the need for access to scarce multilayer ceramic substrates, and the fact that leading tester makers have taken equity positions in established probe card suppliers since 2023 all raise the barrier further. The main route for new entrants is domestic substitution in China, where policy support and restricted access to some foreign tools encourage local tester and probe card suppliers. This creates new competitors in mature-node and domestic segments, but it does not yet challenge the incumbents in the most demanding AI and HBM applications.
Burn-in and stress screening is the segment where entry is most visible, because wafer-level and package-level burn-in for AI processors and silicon carbide devices is still a developing application and customers are open to evaluating new approaches. Even here, however, the leading positions have been taken by suppliers with existing installed bases or through acquisition: Aehr Test Systems added package-level burn-in for AI processors by buying Incal Technology in 2024, and Cohu entered silicon carbide burn-in in October 2024 using its established handler and contactor business. A start-up would need to offer a clear improvement in cost per screened die or in thermal capability, and would still face the reluctance of customers to place unproven equipment in a high-value production flow. Software-led entrants, such as analytics firms that optimise test content using machine learning, face lower capital barriers, but their value depends on integration with the data streams of established testers, which again favours partnerships with incumbents over independent entry.
Bargaining Power of Suppliers: Medium
The bargaining power of suppliers is Medium. On the one hand, several inputs are highly concentrated. Multilayer ceramic space transformers, specialised probe alloys, high-current pin-electronics components and advanced thermal control units are supplied by a short list of firms, and probe card makers have reported substrate availability as a constraint during periods of rapid HBM demand growth. Fluorinated heat-transfer fluids used in some thermal sub-systems face supply changes as 3M completes its exit from PFAS manufacturing by the end of 2025, which forces equipment makers to qualify alternatives.
On the other hand, the leading equipment makers design many critical components in-house, including tester ASICs and probe technologies, which limits the leverage of outside suppliers. Long-term supply agreements and dual sourcing are common, and the largest participants have the scale to secure priority allocations. Supplier power is therefore felt mainly by smaller probe card and handler makers that lack in-house substrate or component capability, and by all participants during demand spikes, rather than as a constant structural pressure.
The equity links formed between tester makers and probe card suppliers also change the supplier relationship. Teradyne's 10% holding in Technoprobe, completed in May 2024, and Advantest's stakes in FormFactor, Technoprobe and Micronics Japan, announced in January and February 2025, give the largest system suppliers closer visibility of probe card roadmaps and capacity. For the tester makers, probe card suppliers are partners as much as vendors, and the alliances reduce the risk that a shortage of qualified cards delays tester shipments. From the perspective of an OSAT or foundry, the probe card supplier is itself a supplier with meaningful power, because a card designed for a specific HBM or AI processor die cannot easily be sourced elsewhere at short notice. When a new device ramps, the first qualified card supplier often holds a strong position until a second source completes qualification, which can take several months. This device-specific dependency is the main reason supplier power is assessed as Medium rather than Low.
Bargaining Power of Buyers: High
The bargaining power of buyers is High. Demand for the most advanced KGD test equipment comes from a small number of very large organisations: leading foundries with advanced packaging lines, the three main HBM producers, a handful of large OSATs and test houses, and the power device IDMs. Each of these buyers places large, programme-level orders and can concentrate a significant portion of a supplier's annual revenue in one decision. Buyers run competitive evaluations between tester platforms and between probe card vendors, request multi-sourcing to protect supply continuity, and negotiate on cost per tested die rather than on equipment price alone.
Buyer power is reinforced by the fact that chip owners, including fabless companies and hyperscalers designing their own accelerators, increasingly specify the test strategy and influence which platforms their OSAT partners use. Advantest's stated aim, when taking stakes in FormFactor and Technoprobe in January 2025, of offering customers several viable probe card sources reflects this pressure for choice. Switching costs moderate buyer power once a platform is in production, because re-qualifying test programs is slow and expensive. However, buyers use the start of each new device generation, such as the move from HBM3E to HBM4 or from one accelerator family to the next, to re-open supplier selection, which keeps pricing and service terms under steady negotiation.
The concentration of demand is particularly marked in the fastest-developing parts of the market. Known-good-stack testing of HBM is purchased by only three memory makers, and the leading AI accelerators are assembled by a small number of foundry and OSAT partners, so a single programme decision can determine the winner of a large share of the most advanced probe card and tester demand for a full product cycle. In power devices, the shift to silicon carbide and gallium nitride modules is led by a limited group of IDMs that operate their own test floors and develop much of their test know-how internally. Test service providers such as KYEC and ASE add a further layer of buyer power, because they aggregate demand from many chip owners and can standardise on preferred platforms across their sites. Smaller buyers, including fabless companies with niche RF, MEMS or industrial devices, have far less influence, but they account for a smaller portion of spending on advanced KGD equipment.
Threat of Substitutes: Low
The threat of substitutes is Low. Known good die testing has no direct functional substitute when multiple dies are assembled into a single package, because a defective die discovered after assembly destroys the value of every other die and of the interposer or substrate. Alternatives exist mainly in where and how much testing is done. A chip owner can rely more on package-level final test and system-level test, accepting higher assembly scrap in exchange for less wafer and die test, or can depend more on built-in self-test and redundancy, such as spare memory rows and lanes that can be repaired after assembly.
These approaches reduce the intensity of some KGD steps for lower-value devices, consumer products and designs with generous repair capability, but they do not remove the need for pre-assembly screening of high-value logic, HBM and power dies. Advances in design-for-test and in-field monitoring change the mix of test methods rather than replacing KGD testing. Improvements in wafer fabrication yield can also reduce the number of failing dies, yet even a low defect rate multiplied across many dies in a stack or module makes screening economically necessary.
There is also a partial substitution between test steps within the KGD flow rather than between KGD testing and an outside alternative. Wafer-level burn-in can replace part of package-level burn-in, die-level testing of singulated dies can reduce the need for some wafer-level test, and system-level test of a completed module can catch defects that escape structural tests. These shifts move spending between segments of the market but generally keep it within the market, because the equipment and probe card suppliers serve several steps. The most credible long-term substitute pressure comes from design techniques that make dies self-testing and self-repairing, such as more extensive built-in self-test, redundant lanes on die-to-die interfaces and in-field health monitoring. These reduce the duration of external test for some devices, but they still require probe access at wafer level to activate and verify the on-die structures, and they do not remove the need for burn-in to screen early-life failures in automotive and data-center parts.
Intensity of Competitive Rivalry: High
Competitive rivalry is High. Advantest and Teradyne compete directly for tester sockets in logic, memory and power test; Tokyo Electron and Tokyo Seimitsu compete in wafer probers; and FormFactor, Technoprobe, Micronics Japan, Japan Electronic Materials and MPI Corporation compete for probe card business that is won or lost device by device. Rivalry is driven by technology rather than by price alone: suppliers compete on probe pitch and current capacity, thermal control at high power, parallelism in memory test and the speed of test-cell bring-up.
The pace of product introductions shows the intensity of competition. Teradyne launched the Magnum 7H for HBM in August 2025, Advantest and Tokyo Seimitsu announced a die-level prober development in December 2025, and Teradyne and Tokyo Electron introduced an integrated KGD test cell in June 2026. Burn-in suppliers, including Aehr Test Systems and Cohu, compete to move stress screening from package level to wafer level for AI processors and silicon carbide devices. Equity alliances between testers and probe card makers add a strategic dimension, as each supplier group tries to secure qualified positions in the most important AI and HBM programmes. Cyclicality adds pressure: in periods when memory or consumer device demand weakens, suppliers compete hard for a smaller pool of orders.
Rivalry also takes place across geographic and customer boundaries. Japanese suppliers have long held strong positions with domestic memory makers and probers, U.S. suppliers with logic and AI processor programmes, and Taiwanese and Korean suppliers with local test houses and memory producers. These positions are being contested as AI accelerator and HBM programmes cross regions, and as Chinese customers develop domestic supply chains for testers and probe cards. Service quality is a competitive factor in its own right: suppliers maintain applications engineers on customer sites, offer test program conversion between platforms, and compete on the speed of probe card repair and re-tipping. Because the number of large programmes is limited, losing a qualification at a leading foundry or memory maker can remove a supplier from a device generation for several years, which raises the stakes of each competitive evaluation and encourages aggressive commercial terms during new product introductions.
Threat of New Entrants: Low; Platform know-how, long qualification cycles, installed test programs and scarce MEMS probe and substrate capability deter new suppliers.
Bargaining Power of Suppliers: Medium; Ceramic substrates, probe alloys and thermal sub-systems are concentrated, but leading equipment makers design many critical components in-house.
Bargaining Power of Buyers: High; A few foundries, HBM producers, OSATs and power IDMs place large programme orders and demand multi-sourcing at each new device generation.
Threat of Substitutes: Low; No functional alternative exists to screening high-value dies before multi-die assembly; only the mix of test steps can shift.
Intensity of Competitive Rivalry: High; Testers, probers and probe card makers compete device by device on pitch, thermal control and parallelism, with frequent product launches.
Market estimates by geography (2032)
InsightAsia Pacific leads with $2.24B by 2032, while Latin America is projected to grow fastest at a 13.3% CAGR.
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View Subscription Plans| REGION | 2022 | 2025 | 2032 | CAGR | SHARE |
|---|---|---|---|---|---|
| North America | $154.60M | $288.30M | $515.80M | 12.8% | 16% |
| Europe | $103.20M | $169.30M | $265.00M | 9.9% | 8% |
| Asia Pacific | $745.70M | $1.32B | $2.24B | 11.6% | 71% |
| Latin America | $21.10M | $40.20M | $73.30M | 13.3% | 2% |
| Middle East & Africa | $23.50M | $43.50M | $77.50M | 12.7% | 2% |
| Total | $1.05B | $1.86B | $3.17B | 11.7% | 100% |
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View Subscription PlansTotal Market Size
$3.17B
| APPLICATION | REVENUE ($B) | GROWTH RATE | MARKET PENETRATION |
|---|---|---|---|
| Wafer-Level Probe Testing | $1.19B | 10.3% | 38% |
| Stacked-Die / Known-Good-Stack Testing | $752.30M | 18.9% | 24% |
| Burn-in & Stress Screening | $720.50M | 12.2% | 23% |
| Singulated Die-Level Testing | $511.00M | 7.8% | 16% |
* Revenue projections based on 2025 estimates. Growth rates represent CAGR 2024–2030. Market penetration indicates current adoption rate within addressable market segments.
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Analytical insights on Known Good Die Testing Market covering market dynamics, competitive landscape, and strategic outlook.
The Known Good Die Testing Market market is projected to reach $3.17B by 2032, growing at 11.7% CAGR. The Wafer-Level Probe Testing segment holds the largest share.
Known good die (KGD) testing sits at the point where front-end wafer fabrication hands over to assembly, and its economics are set by a simple asymmetry: the cost of discarding a single faulty die before packaging is small, while the cost of discovering the same fault after that die has been bonded into a multi-die package can be the loss of every other good die, the interposer and the substrate attached to it. For most of the history of the semiconductor industry this asymmetry mattered mainly to a narrow set of multi-chip modules used in defence, aerospace and some telecom equipment. Since 2023, it has moved to the centre of mainstream production because the highest-value devices now shipping in volume, including AI accelerators, high bandwidth memory (HBM) stacks and multi-die automotive and power modules, are assembled from separately tested dies rather than packaged as single chips.
The dynamics of the market therefore reflect two layers of influence. The first is the macro environment: the pace of data-center construction, the industrial policies that are moving assembly and test capacity into new countries, the export controls that limit where advanced devices and tools can be shipped, and the long-cycle shifts in vehicles and consumer electronics. The second layer is the micro environment of the test cell itself: how many dies are stacked in a memory cube, how many chiplets share an interposer, how much heat a bare die dissipates under test, how much a probe card or prober costs, and how much information a test floor can extract from the data it already collects.
Taken together, these two layers determine how many dies require screening before assembly, how deeply each die is tested, at which insertion the testing takes place, and who performs it. They act on wafer-level probe testing, burn-in and stress screening, singulated die-level testing and stacked-die or known-good-stack testing in different ways, and they shape the purchasing decisions of the testers, probe cards, probers, burn-in systems and test services that make up the market's supply side.
Market Growth Factor Analysis
The scores used in this growth factor analysis are analyst assessments, on a scale of 0 to 10, of the strength of each factor's influence on demand for known good die testing in three forecast windows: 2026–2027, 2028–2030 and 2031–2032. A higher score indicates a stronger influence in the stated direction, whether that direction is promoting, inhibiting or steady. The factors were selected because each acts directly on the volume of dies that require pre-assembly screening, on the depth of testing applied to each die, or on the cost and feasibility of performing that testing, and the scores reflect the balance of evidence from supplier announcements, capacity investments, policy decisions and standards activity observed through 2025 and 2026.
Among the macro factors, investment in AI and data-center infrastructure carries the highest score in the near term because AI accelerators and the HBM stacks placed beside them are the devices for which a single faulty die is most costly. The score eases slightly in the 2031–2032 window, not because demand is expected to fade but because the installed base of KGD test cells for these devices will by then be larger and incremental additions are likely to slow relative to the build-out years. Semiconductor industrial policy and back-end reshoring is scored as a rising influence through 2028–2030, reflecting the timing of assembly and test plants that were announced between 2023 and 2026 in the United States, Japan, India, Europe and Southeast Asia and that are scheduled to start or expand operations in the second half of the decade. Its score moderates in the final window as most of these projects move from construction to steady-state operation.
Export controls are the only macro factor scored as inhibiting. The controls introduced by the U.S. Bureau of Industry and Security in October 2022, October 2023 and December 2024, the last of which added HBM, restrict the flow of advanced devices and of some test and manufacturing equipment to China, fragmenting supply chains and delaying some tool purchases. Their score declines in the later window on the assumption that affected supply chains will by then have adjusted, including through domestic Chinese test equipment and probe card supply. Vehicle electrification and driver-assistance content is scored as a steadily strengthening influence, since automotive programmes adopting silicon carbide and gallium nitride power modules and multi-die ADAS processors take several years to reach volume. The consumer device replacement cycle is scored as steady at a moderate level: smartphones, PCs and wearables continue to generate large die volumes, but their test requirements change slowly and packaging formats in these products rarely raise the penalty for a faulty die as sharply as AI or automotive modules do.
On the micro side, rising HBM stack height and interface speed and the adoption of chiplet and 2.5D or 3D packaging both score highly and strengthen over time, because each additional die in a stack or on an interposer multiplies the value at risk if an untested or under-tested die is assembled. The move from eight-high to twelve-high and sixteen-high memory stacks, and from monolithic processors to designs containing multiple compute and I/O tiles, raises both the number of dies screened and the depth of screening applied to each. Advances in probe card, prober and thermal-control technology are scored as promoting because new probers and probe cards that can hold a bare die at a controlled temperature while delivering high current are what make deeper pre-assembly screening practical.
Test cost per die and the capital intensity of test cells is scored as inhibiting, with its strongest effect in 2026–2027 when tester, probe card and burn-in prices for the newest AI and HBM devices are highest and when many manufacturers are deciding how much screening to move ahead of assembly. The score eases later as tool generations mature and as test-time reduction techniques spread. The adoption of test data analytics and adaptive test begins as a moderate influence and rises to one of the stronger factors by 2031–2032, reflecting the gradual spread of machine learning-based outlier screening, part average testing and feed-forward data links between wafer probe, burn-in and final test across foundries, OSATs and IDMs.
Read across the three windows, the profile of the scores indicates that the market's near-term momentum rests mainly on AI-related demand and on the physical complexity of HBM and chiplet packages, while its later momentum depends increasingly on vehicle electrification, on the completion of regional back-end capacity and on the maturity of data-driven screening. The inhibiting factors are concentrated in the early window, when equipment prices and trade restrictions bear most heavily on purchasing decisions, and are expected to weigh less as supply chains and tool generations settle.
Rising Cost of a Failed Die in Multi-Die AI Accelerator Packages
The economics of known good die testing are set by what is lost when a defective die reaches assembly. In a conventional single-die package, a die that fails final test wastes the die itself, a lead frame or substrate, and some assembly time, and the loss is limited to that one unit. In a 2.5D accelerator package built on a silicon interposer of the CoWoS class, the loss is of a different order. Nvidia's Blackwell B200, which moved into volume production across 2024 and 2025, joins two reticle-sized compute dies and eight stacks of HBM3E memory on one interposer, and later accelerator generations add further dies and larger interposers. Once these components are joined through micro-bumps and underfill, rework is rarely practical, so a single faulty die usually means scrapping the interposer, the organic substrate and every good die bonded beside it, including memory stacks that are themselves among the most expensive components in the server. Package yield behaves as the product of the yields of all its parts: a defect level that would be tolerable for a single-die product becomes expensive when it is multiplied across ten or more components.
The value of screening each die before it enters the package therefore increases with the number of dies per package and with the value of the parts that would be lost alongside a failure. This is the central reason why semiconductor companies that once accepted wafer sort as a coarse pass/fail step now treat die-level quality as a contractual specification negotiated between chip designer, foundry and assembler, with agreed coverage targets, test limits and data exchange obligations attached to every lot of dies that changes hands. The arithmetic also changes the way buyers judge test suppliers. When a defective die can destroy a package worth many times its own value, the relevant measure is no longer the cost of testing a die but the cost of the failures that testing prevents, and that comparison favours more thorough screening even when it adds noticeably to test time. Purchasing decisions for probe cards, testers and probers in this part of the market are therefore increasingly made on coverage and correlation rather than on equipment price alone.
Several forces are pushing the industry toward these multi-die designs at the same time. Lithographic reticle limits cap the area of a single die, so accelerator designers who need more transistors, more on-package memory bandwidth and more I/O must split the design into chiplets and reassemble them in the package. Chiplet partitioning also lets companies mix process nodes, keeping compute on the most advanced node while placing I/O, SRAM or analog functions on cheaper, mature nodes, and it improves the yield of each individual die because smaller dies are less likely to contain a random defect. AMD's Instinct MI350 series, launched in June 2025, illustrates the approach, with multiple accelerator compute dies stacked on I/O dies and surrounded by HBM3E stacks. Hyperscale operators designing their own accelerators, including Google with its TPU family and Amazon Web Services with Trainium, follow similar multi-die architectures, and custom accelerator programmes run by chip design service companies for other cloud operators add further designs of this type. Advanced packaging capacity has also been scarce: through 2024 and 2025, CoWoS-class capacity at TSMC was widely reported as the gating factor for accelerator shipments, and the foundry expanded it repeatedly.
When interposer slots are rationed, placing a die that later fails into one of them wastes scarce capacity and delivery time as well as money. For an accelerator vendor whose customers are waiting for systems, a lost package is also a lost delivery slot, which strengthens the case for screening every die thoroughly before it is committed to assembly. Design teams are also adding more chiplets per product as they gain experience with the approach. Early chiplet products combined two or three dies, whereas current accelerator and server processor roadmaps describe packages with a dozen or more active dies, including separate I/O, cache and compute tiles. Each additional tile is another component whose failure can scrap the whole package, so the trend toward finer partitioning steadily increases the economic weight that rests on die-level screening, independent of growth in the number of packages shipped.
The effect on the test flow is a move of test content upstream. Rather than relying on a final package test to catch most problems, device makers are raising coverage at wafer sort with fuller scan patterns, at-speed functional tests, high-current power-delivery checks and tighter parametric limits, and many are adding a second insertion on singulated dies before assembly. Test times per die lengthen, probe cards with tens of thousands of contacts and higher current capacity become standard for large accelerator dies, and testers need more power supply channels and more precise thermal management to run full-power patterns without damaging the die or the probes. Supply-side vendors have responded with product changes: probe card suppliers such as FormFactor, Technoprobe and Micronics Japan have focused development on high-pin-count vertical probe cards for advanced logic, while automatic test equipment platforms such as Advantest's V93000 and Teradyne's UltraFLEXplus have added power capacity and parallelism aimed at large compute dies. Advantest's decision in January 2025 to take non-controlling equity stakes in FormFactor and Technoprobe, framed around joint technology work on the tester-to-probe-card interface, reflects how closely the interface hardware and the tester now have to be co-designed for these devices.
The same pressure reaches test program development, where engineers must balance the extra coverage demanded by assemblers against the tester time that each additional pattern consumes, and where the quality data generated at wafer sort increasingly travels with the die to the assembly site so that downstream yield problems can be traced back to their source. Correlation between test insertions has become a technical priority in its own right. When the same die is measured at wafer sort, again after singulation and finally in the package, differences between the three sets of results reveal whether the earlier tests are catching the faults that matter. Device makers use these comparisons to tighten wafer-level limits and to retire patterns that add time without detecting failures, which keeps the cost of higher coverage within bounds while preserving the protection that assemblers expect from a known good die.
The driver is concentrated in specific parts of the market. Among device types, Logic & AI Processors carry the largest burden because compute dies are the most expensive components in the package and the ones with the most complex fault models, ranging from stuck-at and transition faults to timing marginality in large on-die memories. By application, AI & HPC / Data Center demand is the main source of new test content, with Telecom & Networking following as switch and network processor makers begin to adopt chiplet partitioning and co-packaged optics. Within test types, Wafer-Level Probe Testing absorbs most of the higher coverage, and Singulated Die-Level Testing gains a role for dies whose value justifies an additional insertion after dicing, where edge chipping and handling damage can be checked. Among end users, Foundries that offer integrated front-end and advanced packaging services, with TSMC as the prime case, and OSATs such as ASE and Amkor that assemble multi-die modules for fabless customers both have a direct interest in the quality of incoming dies, because they bear the cost and schedule impact of assembled failures.
IDMs that build multi-die processors in their own facilities, such as Intel with its Foveros-based client and data-center products, face the same arithmetic internally. Consumer Electronics and other categories built around single-die packages remain far less exposed to this driver, because the cost of a failed package in those products is still close to the cost of the die alone. Geography adds a further dimension, because the assembly of multi-die accelerators is concentrated in Taiwan, with growing volumes in the United States, Japan and Southeast Asia. Dies tested in one location are often assembled in another, so the specification of a known good die becomes part of a cross-border supply chain in which the receiving site must trust the test data generated elsewhere. That dependence encourages common test standards, shared data formats and qualification audits between suppliers and assemblers.
Taller HBM Stacks and the Shift to Known-Good-Stack Testing
High bandwidth memory is a stack of thinned DRAM core dies connected vertically by through-silicon vias and placed on a base die that manages the interface to the host processor. Over the past two years the height of these stacks has risen steadily. HBM3E moved into volume production in 8-high and then 12-high configurations during 2024 and 2025, and the JEDEC HBM4 standard, published as JESD270-4 in April 2025, doubles the interface width to 2,048 bits and allows stacks of up to 16 dies. SK hynix announced in September 2025 that it had completed HBM4 development and prepared for mass production, and Nvidia's Rubin platform, scheduled for 2026, is designed around HBM4. A further structural change concerns the base die: for HBM4 the base die is increasingly manufactured on foundry logic processes rather than DRAM processes, as signalled by the memorandum of understanding signed by SK hynix and TSMC in April 2024 to cooperate on HBM4 base dies.
Moving the base die to a logic process allows memory makers and their customers to add custom logic functions to it, which turns the base die into a more complex device in its own right with test requirements closer to those of a processor than of a memory. Each of these changes adds components and process steps to a single memory stack, and each increases the dependence of stack yield on the quality of every die that enters it. Because stack yield compounds across layers in the same way that package yield compounds across chiplets, the move from eight to twelve and then sixteen dies raises the penalty for any weak die that is allowed into the stacking process. For accelerator vendors, the number of stacks per package is rising at the same time as their height. Accelerator roadmaps published by Nvidia and AMD through 2025 describe packages that carry more HBM stacks with each generation in order to raise memory capacity and bandwidth, so the total number of DRAM dies inside one accelerator package grows on two axes at once.
The quality of each core die therefore matters more to the accelerator vendor than at any earlier point in the history of the product.
Testing a memory stack is not the same as testing its parts. Every DRAM core die is tested at wafer level for cell array defects, retention behaviour and speed, and failing rows and columns are replaced through redundancy repair before the die is thinned. Stacking then introduces new risks that no wafer-level test can see: TSV opens and shorts, micro-bump cracks, die warpage, damage from thinning and handling, and thermal stress from mass reflow or thermocompression bonding with non-conductive film. A stack that contains sixteen individually good dies can still fail because one interconnect layer was not formed correctly or because a die cracked during bonding. Memory makers therefore test the completed stack, verifying the TSV channels, running memory array tests through the base die, performing post-stacking repair where the architecture allows it, and applying stress screens, before the stack is shipped to the accelerator assembler. This known-good-stack step has become a separate test insertion with its own equipment set, because the customer who places the stack on a CoWoS-class interposer next to an expensive processor die expects it to work the first time and has no practical means of replacing it afterwards.
With HBM4 base dies coming from a logic foundry, the stack maker must also confirm the quality of a die it did not fabricate, which adds an incoming-inspection and test responsibility that did not exist in earlier generations. The test programmes for stacks are also longer, because each additional layer adds memory capacity that has to be exercised and channels that have to be verified, so test time per stack increases with every generation even when per-bit test efficiency improves. Thermal behaviour adds another test dimension. Tall stacks dissipate heat poorly through their upper layers, and retention and refresh characteristics of DRAM cells change with temperature, so stack testing increasingly includes measurements at elevated temperature that approximate conditions inside a working accelerator. Memory makers have also tightened the speed bins applied to HBM stacks, since accelerator vendors specify bandwidth at particular data rates and expect every stack in a package to meet them, which adds further measurement time and sorting to the known-good-stack step.
Wafer-Level Burn-In and High-Power Screening of AI Processors Before Packaging
Burn-in has traditionally been performed on packaged parts: a finished device is placed in a socket on a burn-in board, held at elevated temperature and voltage for a defined period, and then retested to remove units that fail early in life. That sequence works well when a package contains one die, because a failure during burn-in costs only that package. For AI accelerators assembled on silicon interposers with several HBM stacks, the logic of package-level burn-in changes sharply. A latent defect in the compute die that appears only under stress will, if found after assembly, condemn a module that already carries several memory stacks, an interposer and an organic substrate, each of which is expensive and, in recent years, capacity-constrained. Moving the stress step forward, so that latent defects in processor dies are triggered and removed while the dies are still on the wafer or are individual bare dies, therefore represents a clear commercial opportunity for burn-in equipment makers, contactor suppliers and test service providers.
The opportunity is reinforced by the reliability expectations of hyperscale data-center operators, who run accelerators continuously at high utilisation and for whom early-life failures in deployed servers translate into lost compute time, field replacement cost and, in large training clusters, disruption of jobs that span thousands of devices. There is also a capacity argument: advanced packaging lines for interposer-based modules have been one of the tightest bottlenecks in AI hardware supply during 2024 and 2025, and every module scrapped because of a die that could have been screened earlier consumes packaging capacity that could have produced a saleable unit. For the processor maker, removing weak dies before they reach that bottleneck raises effective output from the same packaging allocation, which gives wafer-level stress a value that goes beyond the cost of the scrapped materials alone and makes the business case easier to justify to buyers who measure their supply in modules shipped rather than wafers started.
The technical demands of this opportunity are what make it valuable to suppliers rather than simply a shift of existing work. A modern AI processor can draw several hundred watts and, under stress conditions, more than that, which means a wafer-level burn-in system must deliver high current through a full-wafer contactor while removing heat evenly enough that each die sees the intended stress and none is damaged by local hot spots. Aehr Test Systems has positioned its FOX-XP platform and WaferPak full-wafer contactors for this application, and its order flow during 2025 and 2026 illustrates how the opportunity is developing. On 26 August 2025, the company announced a paid wafer-level burn-in evaluation order from a leading AI processor supplier, covering a custom high-power wafer contactor and test program development, and on 26 February 2026 it announced a US$14 million order for fully automated FOX-XP systems, WaferPak contactors and auto-aligners from its lead AI processor customer. Aehr's acquisition of Incal Technology, agreed on 16 July 2024, added ultra-high-power package-level burn-in systems for AI processors, giving it a route to serve customers at both wafer and package level while they decide where to place the stress step.
The pattern of evaluation followed by production orders indicates that processor makers are validating wafer-level stress as a replacement for, or complement to, package-level burn-in rather than treating it as an experiment. Automation is a further element of the opportunity. Early wafer-level burn-in installations in other device categories relied on manual loading of wafers and contactors, which was acceptable at modest volumes but becomes a constraint when a processor programme ramps to many thousands of wafers per month. Fully automated systems that align wafers to contactors, load and unload them without operator handling and integrate with factory scheduling software reduce handling damage and labour cost, and they are what allow wafer-level stress to be adopted as a standard production step rather than a sampling or engineering activity.
The opportunity extends beyond burn-in equipment itself. Each high-power wafer-level or die-level burn-in step requires custom contactors matched to the die layout and bump pitch, test programs that apply stress patterns representative of AI workloads, power delivery hardware capable of supplying very high currents at low voltage, and thermal interfaces able to keep die temperatures within a narrow window. Probe card suppliers such as FormFactor and Technoprobe, whose businesses are built on fine-pitch contact technology, and handler and thermal specialists such as Cohu are positioned to supply parts of this stack. For OSATs and test specialists, including companies like KYEC that already test large volumes of AI devices, offering wafer-level stress as a service gives them a way to capture value that would otherwise sit inside the processor maker's own facilities. For foundries offering integrated advanced packaging, wafer-level stress screening can be bundled into a turnkey flow, which strengthens their position with fabless AI chip designers who prefer a single accountable supplier for compute die, interposer assembly and test.
Within the market's segmentation, this opportunity bears most directly on Burn-in & Stress Screening, on Logic & AI Processors as the device type and on AI & HPC / Data Center as the application. The consumable side of the opportunity is significant in its own right. Full-wafer contactors and high-power burn-in boards are matched to a particular die design, so each new accelerator generation and each customer-specific variant requires new contact hardware even when the burn-in system itself is reused. Contactors also wear with repeated thermal cycling and touchdowns, generating replacement demand over the life of a product. This gives suppliers of contact technology a recurring revenue stream tied to the number of active AI designs rather than only to the number of systems installed. Suppliers that can design, manufacture and refurbish contactors close to the customer's test floor also shorten the time between a design change and a working burn-in setup, an advantage that matters when processor makers release revised steppings at short notice.
The opportunity is not limited to the largest accelerators. Custom AI silicon developed by hyperscale cloud providers, network processors and data-processing units used in AI clusters, and high-performance CPUs built from multiple chiplets share the same economics in which a single weak die can compromise an expensive package. As these designs move to more advanced process nodes, early-life failure mechanisms associated with gate oxide integrity, interconnect electromigration and power-delivery networks become harder to screen with functional test alone, which increases the value of a stress step that accelerates those mechanisms before assembly. The suppliers best placed to benefit are those able to qualify their contactors and thermal systems quickly for each new die design, because accelerator generations now refresh roughly every year and a burn-in solution that takes too long to qualify risks missing the volume window of the device it was designed for.
The opportunity also rewards close collaboration between burn-in suppliers and processor designers on the stress conditions themselves, since defining a stress recipe that removes latent defects without consuming useful device lifetime requires reliability data that only the chip designer holds, and suppliers that can co-develop those recipes tend to become embedded in a product line for several generations. Custom accelerators add a further dimension, because hyperscale companies that design their own chips frequently rely on design-service partners, foundries and OSATs to manage manufacturing, and each of these parties may take responsibility for part of the screening flow. A burn-in supplier that can work across that chain, providing equipment to the test house, contactors matched to the foundry's bump process and stress programs aligned with the system owner's reliability targets, can win a position on several custom programmes at once rather than depending on a single merchant processor vendor. Breadth across programmes also spreads the supplier's exposure, since the volume of any individual custom accelerator depends on the deployment plans of one cloud operator and can change sharply from one year to the next.
Regionalised Back-End and Advanced-Packaging Capacity Creating New Test-Cell Demand
For several decades, the assembly and test stage of the semiconductor industry was concentrated in a small number of locations, principally Taiwan, mainland China, South Korea, Malaysia, the Philippines and Singapore. Government policy since 2022 has deliberately broadened that footprint, and because KGD testing is an integral part of every advanced packaging line, each new back-end facility built outside the traditional clusters creates demand for a complete set of testers, probers, probe cards, burn-in systems and handlers that did not previously exist in that location. In the United States, the CHIPS and Science Act of August 2022 funded not only wafer fabs but also the National Advanced Packaging Manufacturing Program and a series of packaging and test projects, including Amkor's advanced packaging and test campus in Arizona, whose CHIPS award was finalised in December 2024, and SK hynix's advanced packaging plant for HBM in West Lafayette, Indiana, announced in April 2024. On 10 July 2026, KYEC, a test supplier to Nvidia, announced it would invest up to US$1.4 billion in a U.S. facility. Each of these sites requires KGD capability because the devices they will handle, including AI accelerators, HBM and multi-die processors, cannot be assembled economically without pre-screened dies.
The U.S. projects are significant for test suppliers in a second way: they place advanced packaging close to the wafer fabs being built in Arizona, Texas, Ohio and New York, which creates the possibility of a domestic flow in which dies are fabricated, screened, assembled and tested without leaving the country. Customers for whom supply-chain security is a procurement requirement, including defence programmes and some government-funded computing projects, are expected to prefer such flows, and they typically specify qualified, documented KGD procedures that add test steps compared with commercial practice. Such programmes often require traceability of each die from wafer to finished module, which in turn requires test data systems that record die identity and screening history at every insertion.
Asia is seeing a parallel redistribution of back-end investment. In Japan, the government's support for Rapidus, whose 2 nm pilot line in Hokkaido started in April 2025, includes plans for back-end and chiplet capability, and Micron's planned investment of around US$9.6 billion in a memory plant in Hiroshima, reported by TrendForce on 2 December 2025, is tied to HBM production. India's Semiconductor Mission has approved several assembly, test, marking and packaging projects since June 2023, starting with Micron's Sanand facility in Gujarat and followed by Tata Electronics in Assam, the CG Power–Renesas joint venture and Kaynes in Sanand, and the HCL–Foxconn project approved in May 2025. In Southeast Asia, Malaysia's National Semiconductor Strategy of May 2024 aims to move the country's large back-end base toward advanced packaging, and Singapore hosts Micron's HBM packaging facility, where ground was broken in January 2025, as well as ASE capacity that its Singapore subsidiary moved to expand on 29 September 2026 through the purchase of a factory in Yishun. Even within Taiwan, the established centre of advanced test, ASE broke ground on 10 April 2026 on a test facility of around NT$108.3 billion in Renwu, Kaohsiung, scheduled to start operations in April 2027.
These Asian projects differ in the stage of KGD capability they demand. The Indian facilities are initially oriented toward conventional packages for memory, power, automotive and consumer devices, where wafer probe and final test dominate and stacked-die test is limited, so their first equipment purchases are expected to centre on probers, probe cards and mainstream testers. The Japanese, Singaporean and Taiwanese projects, by contrast, are linked to HBM and AI packaging and therefore require stack-level test, high-power die-level test and burn-in capability from the outset. The difference in starting point means that suppliers can address India first with mainstream probe and final-test equipment and expand the offering as local customers move to more complex packages, whereas the HBM-linked sites demand the full range of KGD tools at once.
Capital Intensity and Cost per Tested Die
Known good die testing adds equipment, consumables and time to the manufacturing flow, and the combined cost is a real limit on how widely it is applied. A test cell for advanced dies combines an automatic test system with high-current power supplies and high-speed digital channels, a wafer or die prober with an actively controlled thermal chuck, and an interface that includes the probe card. The probe card is a custom consumable: each new device design normally needs its own card, advanced vertical probe cards for large logic or memory dies carry tens of thousands of probes, their lead times are measured in weeks, and they wear out with use and must be cleaned, repaired or replaced. Singulated die testing adds handlers, die carriers and pick-and-place equipment that must manage fragile thinned dies without chipping or contaminating them. Burn-in requires boards, sockets or wafer-level contactors and ovens in which devices may spend many hours under voltage and temperature stress, along with the power distribution and cooling infrastructure that such equipment needs. Each of these items represents non-recurring engineering for every new device, plus floor space, electrical power and skilled engineering staff in the test house.
The total is not a one-off purchase but a recurring commitment, because every new product generation brings new probe cards, new burn-in hardware and new test programmes, and the equipment itself must be upgraded as device power, pin counts and data rates rise. For many companies, the decision to offer a die as a known good die product therefore depends less on technical feasibility than on whether its expected volume and price can carry this stack of costs. Engineering capability is a further element of cost that is easy to overlook. Developing a high-coverage test programme for a large accelerator die or a memory stack requires test engineers with knowledge of the device architecture, the tester and the interface hardware, and such engineers are in short supply in most back-end locations. Device makers and OSATs compete for the same pool of specialists, and the time needed to develop and debug programmes adds to the cost and delay of bringing a known good die product to market.
These costs are rising because the devices that most need known good die assurance are also the hardest to test. AI accelerator dies draw very high currents during full-power test, which demands larger power delivery networks in the probe card and tester and creates heat that the prober must remove in real time. Larger dies mean fewer dies per wafer, which reduces the number of devices over which the fixed cost of a probe card and test program can be spread. Die-level testing usually runs at lower parallelism than wafer-level testing, since handlers present a limited number of singulated dies to the tester at a time, so the cost per tested die increases for every additional insertion. Long burn-in durations tie up capacity for hours or days, and stack testing for memory multiplies test time because each layer of the stack must be exercised. For premium products such as compute dies and HBM stacks, these costs are small relative to the value of the assembled package.
For mid-value products, including many mobile, consumer and sensor devices, the same cost structure often does not pay back, which is why full known good die screening remains confined to a subset of the dies that are eventually assembled into multi-chip packages. Device makers in these categories commonly fall back on sampling plans, reduced test coverage or reliance on final package test, accepting a higher assembled failure rate as the cheaper option. This creates a ceiling on the addressable volume of the market that moves only as equipment costs fall or as the price of the surrounding package rises. Equipment pricing reflects these technical demands. High-power test systems, probers with active thermal control and fine-pitch probe cards are produced by a small number of suppliers, and their prices have risen with each generation as capability has increased. Buyers have limited ability to negotiate when only two or three qualified suppliers exist for a given tool, which keeps capital cost per test cell high and prevents the cost of known good die screening from falling as quickly as device volumes grow.
A second cost issue is utilisation risk. Test capacity is typically purchased or allocated for particular customer programmes, and probe cards, burn-in boards and handler kits are often specific to a single device. If a programme is delayed, redesigned or lost to a competitor, the associated tooling can be stranded and the test cell may run well short of full load, while depreciation continues regardless of how many dies pass through it. The semiconductor industry's 2023 downturn in memory, smartphones and personal computers showed how quickly test capacity can move from shortage to surplus, and OSATs that had added equipment during the preceding upturn faced pricing pressure from customers seeking to share the burden. The concentration of advanced known good die demand in a small number of AI accelerator and memory programmes adds to this risk, since a change in one large customer's product roadmap or sourcing strategy can shift a large block of test demand from one supplier or site to another within a few quarters. Test service providers in emerging back-end locations, where volumes are smaller and customer bases less diversified, find it especially difficult to justify the latest high-power test cells.
Equipment purchase decisions are further complicated by export control regimes covering advanced semiconductor technology, which can limit which customers a supplier may serve and add compliance work to cross-border sales and service, and by long equipment lead times that force buyers to commit capital before customer volumes are confirmed. Inventory and logistics add a hidden cost. Dies sold as known good die must be stored and shipped in carriers that protect them from contamination and damage, and dies awaiting die-level test or burn-in tie up working capital while they wait for capacity. When test capacity is tight, these queues lengthen and delay assembly schedules; when it is loose, idle equipment absorbs cost. Both situations weigh on the profitability of screening and make test planning a significant operational challenge for device makers and OSATs.
The restraint affects the segments of the market unevenly. Singulated Die-Level Testing and Stacked-Die / Known-Good-Stack Testing are most exposed, because they combine low parallelism with expensive, device-specific handling and interface hardware. Burn-in & Stress Screening is exposed through the long occupancy of capacity, particularly when burn-in is applied to high-power AI dies whose thermal management requires specialised ovens or contactors that cannot easily be redeployed to other products. Wafer-Level Probe Testing is the least exposed of the four test types, since it benefits from high parallelism and from the fact that wafer sort is already a standard step in every fab's flow, although rising probe card costs still weigh on it. By device type, MEMS & Sensors and RF & Mixed-Signal Devices, which have lower average selling prices and often need special stimulus or calibration hardware, face the weakest payback, and by application Consumer Electronics and Smartphones & Mobile are where cost sensitivity most often limits screening to sampling or to wafer-level tests alone. Among end users, smaller OSATs feel the restraint most acutely, while large IDMs and Foundries are better able to absorb the capital requirement across a broad product base and to reuse equipment across product generations.
This difference tends to concentrate advanced known good die testing among the largest participants and in the established back-end clusters of East Asia, where installed capacity can be shared among many customers. The restraint also shapes how the work is divided across the supply chain. Device makers with the largest volumes increasingly negotiate dedicated capacity agreements with test suppliers, while smaller fabless companies rely on shared capacity and may find themselves deprioritised when demand from large customers rises. This imbalance can delay the introduction of known good die products by smaller companies and limits the breadth of the market even when the technical case for screening is clear.
Physical and Coverage Limits of Bare-Die Testing
Even where the economics favour screening, the physics of contacting and exercising an unpackaged die limits what a test can prove. The interconnects used in advanced packages are shrinking faster than probe technology. Micro-bump pitches in HBM stacks and 2.5D interposer assemblies are measured in tens of micrometres, and hybrid bonding, which joins copper pads and dielectric surfaces directly without solder, reaches single-digit micrometre pitches. Hybrid bonding also requires the bonding surface to be flat and free of contamination, so any scrub mark left by a probe tip can create voids and weak joints. In practice this means the functional bonding pads often cannot be touched at all during test. Designers respond by adding sacrificial test pads or larger probe-friendly bumps at a coarser pitch, but these consume die area, add parasitic loads and verify a proxy rather than the actual interconnect that will carry signals in the finished product. Probe damage to micro-bumps, including deformation that affects later bonding, remains a known yield risk, and every touchdown on a fragile thinned die adds handling exposure.
Probe card makers are working on finer-pitch MEMS probe technologies and on contact methods that reduce scrub, but the rate at which bonding pitches are shrinking means that probing technology is generally a step behind the interconnect it is meant to verify. This gap is widest for the most advanced 3D-stacked products, which are also the products where the cost of an undetected defect is greatest. Mechanical handling of thinned dies compounds the contact problem. Core dies for HBM and dies destined for 3D stacks are thinned to a small fraction of their original thickness, which makes them prone to cracking, warping and edge chipping during probing, transfer and storage. Testing such dies requires carriers, temporary bonding or support wafers and carefully controlled probe forces, and each of these measures adds cost, introduces its own failure modes and reduces the throughput of die-level testing.
Coverage gaps follow from the same constraints. The electrical path through a probe card has far more inductance and capacitance than the short, dense connections inside a 2.5D or 3D package, so very high-speed interfaces, such as the 2,048-bit HBM4 bus or die-to-die links running at several gigabits per second per lane, are difficult to exercise at their real operating speed during wafer or die test. Power delivery is similarly limited, which can prevent a processor die from being run at the full current and switching activity it will experience in a server, and voltage droop across the probe card can mask or create failures that would not occur in the final system. Thermal conditions on a prober chuck also differ from those inside a package, where the die sits under a heat spreader next to other hot components and develops hot spots that a chuck cannot reproduce. As a result, some speed-related, power-related and thermal faults pass wafer and die test and appear only at final or system-level test after assembly.
Radio-frequency devices face their own version of this problem, since millimetre-wave measurements on bare dies need careful probe calibration and may not replicate the impedance environment of the final module. Many MEMS devices need physical stimulus such as pressure, motion or sound that cannot practically be applied at a wafer prober, so their full functional test still takes place after packaging. Built-in self-test and design-for-test structures can recover part of the lost coverage, but they add design effort and silicon area and cannot reproduce every interaction that occurs in the finished assembly. Test standards are only partly able to close these gaps. Interface specifications for die-to-die links define test and repair features that allow links to be checked after assembly, and standards for test access in stacked dies give designers a framework for reaching inner layers, but their adoption is uneven across suppliers and product generations. Where different dies in one package come from different companies, the absence of a common test architecture limits how much coverage can be achieved before assembly and leaves more of the burden to post-assembly testing.
A further category of failures arises only after the dies are combined. Thinning, through-silicon via formation, bonding heat and warpage of the assembly can introduce defects into dies that were genuinely good when tested. Electrical interactions between dies, such as supply noise coupling or crosstalk on dense interposer wiring, cannot be tested until the dies sit together. Some defects are latent and appear only after operating stress, which burn-in can accelerate but not completely eliminate. Hyperscale operators, beginning with papers published by Meta and Google in 2021, have documented silent data corruption caused by marginal processor cores that passed manufacturing tests, and the topic has remained a regular subject at industry test conferences through 2025. These effects mean that a known good die is a statistical assurance rather than a guarantee, and in multi-vendor chiplet assemblies they create disputes about responsibility when a module fails, because the die supplier, the stack maker and the assembler each tested their own contribution.
Without agreed fault models and shared data formats, it is difficult to establish whether an assembled failure stems from a test escape at die level or from damage during assembly, and this uncertainty complicates commercial terms for buying and selling dies between companies. It also weakens the case for paying a premium for die-level screening when the buyer knows that a share of the failures it most fears will survive that screening regardless of its thoroughness. Field data show that these escapes have real consequences. Operators of large computing installations replace failed accelerator modules as a routine part of operations, and every replacement removes an expensive assembly from service even when only one die within it is faulty. The cost of such replacements, together with the downtime they cause, sharpens attention on the limits of die-level testing and pushes both device makers and their customers to look for complementary forms of protection beyond the known good die screen.
Convergence of Probe and Final Test Through Thermally Controlled Die-Level Probers
The KGD flow has traditionally been divided between two kinds of equipment. Wafer probers, supplied by companies such as Tokyo Electron, Tokyo Seimitsu and MPI Corporation, move a whole wafer under a probe card and test each die in place, typically with limited ability to dissipate high power from an individual die. Test handlers, supplied by companies such as Advantest and Cohu, pick and place packaged devices into sockets and can apply active thermal control, but they were designed for packaged parts rather than fragile bare dies with exposed bumps. A clear trend since late 2024 is the emergence of a third category that combines elements of both: die-level probers and handlers that present an individual singulated die, or a small group of dies, to a probe interface while actively controlling its temperature under high power. This equipment allows test content that was previously possible only after packaging, including full-speed functional tests and high-power stress conditions, to be applied to a bare die before it is committed to an expensive multi-die assembly. The trend also reflects a change in where manufacturers expect escapes to occur.
With monolithic devices, a die that passed wafer probe with marginal results would be caught by final test after packaging at modest cost. In multi-die assemblies the final test is no longer a cheap safety net, because by then the marginal die has been combined with other expensive components. Manufacturers have therefore sought an insertion between wafer probe and assembly that delivers final-test-level coverage on bare silicon, and die-level probers with thermal control are the equipment category that has formed to fill that gap. Its arrival also changes the language customers use when specifying KGD quality: rather than referring only to wafer-level yield, buyers of multi-die modules increasingly specify the test coverage and stress conditions a die must have passed before it may be released to assembly, which in turn defines the capabilities a die-level test cell must provide.
The trend is visible in a series of product announcements across 2024 to 2026. On 10 December 2024, Advantest launched an integrated KGD test cell for power semiconductors that pairs its CREA MT series testers with its new HA1100 die prober, designed to improve die-level yield for silicon carbide and gallium nitride devices; its probe interface limits power to protect probe cards, chucks and devices, and only passing dies are assembled into power modules. On 16 December 2025, Advantest and Tokyo Seimitsu announced joint development of a die-level prober for AI and high-performance computing devices, combining probing and handling technologies specifically to deal with the heat these chips generate during test. On 8 June 2026, Teradyne announced an integrated test cell pairing its UltraFLEXplus tester with Tokyo Electron's Prexa SDP prober, developed with TEL, for screening known good dies in AI and data-center chips, and describing the cell as open to other probe cards, manipulators, probers and testers. These are three different combinations of tester and prober suppliers addressing the same problem, which indicates that the industry regards die-level thermal test as a mainstream requirement rather than a specialist niche. The sequence of announcements is also instructive.
The first product addressed power devices, where die-level test of SiC and GaN chips had a clear and immediate return in module yield, and the later announcements extended the concept to AI and HPC processors, where power densities are higher and the thermal problem harder. This progression suggests that the technology is moving from device categories with simpler test content to those with the most demanding requirements, and that further product releases for HBM base dies and other chiplet types are a logical next step. Each extension into a new device category requires new thermal heads, contactors and handling kits, which adds to the value of the installed base for suppliers that are first to qualify.
Several technical pressures explain the convergence. As AI processors and HBM base dies grow in power density, a conventional wafer chuck can no longer keep each die at a uniform, controlled temperature while it runs at full functional speed, which means that wafer probe results may not reflect how the die will behave in service. Testing at full speed and full power on the wafer is further complicated by the parasitic inductance and resistance of probe card paths, which limit how much current can be delivered without voltage droop. A singulated die on a dedicated thermal stage avoids some of these limitations because heat can be extracted directly from one die and the power delivery path can be shortened. At the same time, the probe interface remains essential, because hybrid-bonding pads and micro-bumps on dies destined for 2.5D and 3D packages cannot tolerate the contact force or scrubbing of conventional sockets. The resulting equipment therefore borrows precision alignment and fine-pitch contact from wafer probing and active thermal management and device handling from final test.
For probe card makers such as FormFactor, Technoprobe and Micronics Japan, the trend creates demand for new contactor designs suited to singulated dies, while for handler suppliers it opens a route into a step previously served only by wafer probers. Handling of singulated bare dies introduces its own engineering requirements. Dies must be picked from dicing tape or carriers, aligned to a probe interface with micrometre-level accuracy, held flat during contact and returned to carriers without chipping or contaminating the bonding surfaces. Particle control is especially important for dies intended for hybrid bonding, where a small particle on the surface can prevent a reliable bond, so die-level test equipment must meet cleanliness standards closer to those of front-end processing than of traditional final test. Inspection of dies before and after contact is therefore becoming part of the cell, so that probe marks and surface damage can be checked before a die proceeds to bonding. Integrating this inspection avoids a separate handling step and the contamination risk that comes with it.
The commercial consequences of the trend are already reshaping supplier relationships. Because a die-level test cell must integrate a tester, a prober or handler, a probe interface and a thermal subsystem from potentially different suppliers, partnerships among equipment makers have become more frequent, as the Advantest–Tokyo Seimitsu and Teradyne–Tokyo Electron announcements show. Customers, for their part, are evaluating where in their flow each test should occur: some content may move from final test to die-level test, some from wafer probe to die-level test, and in some cases die-level test may allow a reduction in package-level burn-in. This reallocation of test content between insertions affects how equipment budgets are divided and favours suppliers with offerings at more than one insertion point. Within the market's segmentation, the trend is most closely associated with Singulated Die-Level Testing, and it is particularly relevant to Logic & AI Processors and Power Devices (SiC, GaN & Si), the two device groups where high power density and expensive multi-die assemblies coincide. It also matters to IDMs that build their own power modules, since they can apply die-level screening in-house without depending on an outside test house for the step that most affects module yield.
Throughput remains the main open question for the trend. Testing one or a few dies at a time is inherently slower than parallel testing of many dies on a wafer, so die-level test cells must justify their cost through the value of the assemblies they protect rather than through test economics alone. Suppliers are addressing this with multi-site die handling and faster thermal stabilisation, and the speed at which these improvements arrive is likely to determine how widely die-level test spreads beyond the highest-value processors and power modules. A further consideration is the floor space and facility power each cell requires, since high-power thermal control adds chiller and power infrastructure that test floors must plan for. Lower-cost variants aimed at RF, sensor and mid-range logic dies would broaden the addressable base considerably.
Design-for-Test Standards Moving Test Content Into the Chiplet
A second trend works from the opposite direction. Rather than building more capable external equipment to reach into each die, chip designers are building more test capability into the die itself, and industry bodies are defining standard ways for that on-die capability to be accessed once dies are combined. The motivation is that, after chiplets are bonded side by side on an interposer or stacked vertically, most of their pins and pads are no longer reachable by external probes. If an assembled multi-die package fails, identifying which die caused the failure, and whether the fault lies in a die or in one of the thousands of die-to-die connections, depends on test structures that were designed in from the start. The burden of test planning therefore moves earlier, into the architecture phase of a chiplet, where decisions about test access are made alongside decisions about performance and power. These same structures also make pre-assembly testing more complete, because they allow interfaces that will later connect to neighbouring dies to be exercised in loopback or through dedicated test paths while the die is still on the wafer.
Die-to-die interfaces are a particular focus because they are the part of a chiplet that conventional wafer probe tests least well. These interfaces use very fine bump or hybrid-bond pitches, too small and too numerous to contact individually with a probe card, and they are designed to operate at high data rates over very short distances to a neighbouring die. Without built-in test features, a defect in such an interface may remain hidden until the chiplet is bonded, which is precisely the outcome KGD testing is meant to prevent. Designers therefore add loopback paths, pattern generators and checkers, and lane repair capability so that interface quality can be verified with only a small number of contacted pads. The trade-off is silicon area: every test structure added to a chiplet consumes space that could otherwise hold logic or memory, so designers must balance test coverage against die size, and standards help by reducing the area overhead of reinventing access logic for each new design.
Several standards underpin this trend. IEEE 1838-2019 defines a test access architecture for three-dimensional stacked integrated circuits, including a die wrapper register and a standard way for test signals to travel up and down a stack, which allows each layer to be tested both before and after stacking. IEEE 1149.1, the long-established boundary-scan standard, and IEEE 1687, which governs access to embedded instruments such as on-chip monitors and built-in self-test engines, provide the infrastructure for reaching test features inside each die. For chiplet interconnect, the Universal Chiplet Interconnect Express (UCIe) 2.0 specification released in August 2024 introduced a manageability and design-for-excellence architecture, often described as DFx, that standardises how test, debug and telemetry functions are accessed across chiplets from different suppliers. In memory, the JEDEC HBM4 standard published in April 2025 as JESD270-4 continues the use of built-in self-test and repair features in the base die, allowing the memory stack to test and repair itself in ways an external tester cannot easily reach once the stack is assembled. The value of these standards lies as much in their common vocabulary as in their technical content.
When a foundry, an OSAT and a test equipment supplier all work from the same description of how test access is structured on a die, test programs can be developed once and reused at different insertions and sites, and test equipment can be configured to recognise standard structures automatically. This reduces the engineering effort required for each new chiplet design, which matters because the number of distinct dies requiring KGD screening increases as designs are partitioned into more chiplets. Common structures also support failure analysis, because a fault found after assembly can be localised to a specific die or interface with standard diagnostic routines, and that information can be returned to the die supplier to tighten its own pre-shipment screens.
The practical effect is a change in how test content is divided between automatic test equipment and the die itself. Memory built-in self-test, logic built-in self-test, on-die process and temperature monitors, and the monitoring features associated with silicon lifecycle management increasingly perform work that once required external tester resources. This does not reduce the role of external testing in the KGD market; rather, it changes what external equipment must do. Testers must be able to configure, run and read out embedded test engines quickly through standard interfaces, deliver accurate power and timing during those tests, and combine on-die results with external measurements. For probe card and prober suppliers, the trend can reduce the number of signals that must be contacted on each die, since test access is concentrated in a smaller set of pads, while increasing the precision required on power delivery. For test data platforms, it adds a new stream of on-die monitor data that can be used to predict field reliability, linking pre-assembly screening with the operating life of the device in a data center or vehicle. Silicon lifecycle management, in particular, extends the reach of test beyond the factory.
On-die sensors that measure timing margins, voltage droop and temperature during manufacturing test continue to report the same measurements once the device is in service, which allows the behaviour of a die in the field to be compared with its signature at wafer probe. Over time, this feedback can be used to refine pre-assembly screens, identifying which test-time signatures are associated with later failures and tightening the KGD criteria accordingly. For data-center operators running large accelerator fleets, this feedback loop is of practical value, because it allows emerging reliability problems to be traced back to specific wafers or lots and screened out of future production more quickly than field returns alone would permit.
The known good die testing value chain links a small group of precision component makers, a concentrated tier of test equipment and probe card suppliers, and a demand base made up of OSATs, foundries and IDMs that run test floors on behalf of chip owners. The chain differs from conventional final test because the device under test is a bare die or a stack of dies rather than a packaged part. That change pushes more electrical, thermal and mechanical capability into the wafer-level and die-level stages, where contact is made directly to bumps, micro-bumps or hybrid bonding pads, and where a missed defect is only discovered after an expensive multi-die assembly has been built. The value chain therefore rewards accuracy of contact, thermal control and test coverage more than throughput alone, and the bargaining position of each participant depends on how hard its contribution is to reproduce.
Inputs and Enabling Technologies
The first stage covers the materials, sub-components and intellectual property that make a KGD test possible. Probe cards are the most material-intensive input. Advanced vertical and MEMS probe cards use thousands to tens of thousands of microfabricated probes formed from nickel alloys, palladium alloys, rhodium-plated tips or copper-based composites, chosen for spring force, current-carrying capacity and resistance to wear over millions of touchdowns. These probes are mounted through guide plates and connected to the tester through a space transformer, which is commonly a multilayer ceramic or organic substrate that fans out the very fine pitch of micro-bumps to the coarser pitch of the printed circuit board. Multilayer ceramic substrates are supplied by a short list of Japanese and Korean ceramic specialists, and probe card makers frequently cite substrate lead times as a constraint when demand for high-bandwidth memory and AI accelerator cards rises quickly.
Automatic test equipment depends on its own input chain of pin-electronics ASICs, high-speed digital channels, precision parametric measurement units, device power supplies capable of hundreds of amperes, and RF and mixed-signal instruments. Leading tester makers design many of these ASICs in-house, which is one reason why platform architectures such as the Advantest V93000 and the Teradyne UltraFLEX family have long service lives and large installed bases. Thermal sub-systems form a third input group. Die-level testing of AI processors and stacked memory generates heat densities that standard chucks cannot remove, so active thermal control units, liquid-cooled chucks, and in some cases fluorinated heat-transfer fluids are bought from specialist suppliers. Sockets, contactors and pogo-pin assemblies, together with consumable cleaning media for probe tips, round out the hardware inputs.
The least visible but increasingly decisive input is test content. Design-for-test structures embedded in the die, such as scan chains, built-in self-test engines, IEEE 1149.1 boundary scan and IEEE 1687 instrument access, determine how much of a die can be tested through a limited number of probe contacts. For stacked devices, IEEE 1838-2019 defines a test access architecture for dies in a three-dimensional stack, and the UCIe 2.0 specification released in August 2024 added a DFx framework for chiplet links. Electronic design automation vendors and chip designers own much of this content, which means that test coverage at the KGD stage is partly decided long before a wafer reaches a prober. The value added at this stage lies in physics and materials know-how: the ability to deliver a stable, low-resistance contact at fine pitch and high current without damaging pads that must later be bonded.
Test Equipment Manufacturing and Test-Cell Integration
The second stage turns these inputs into the four main equipment categories used in KGD flows: testers, wafer and die probers, handlers and burn-in systems, together with the probe cards that link them to the device. Tester supply is concentrated in Advantest and Teradyne for high-performance logic and memory, with Chroma ATE active in system-level and power test. Teradyne's Magnum 7H, unveiled in August 2025, is an example of a platform built specifically for HBM2E, HBM3 and HBM4 devices, where massively parallel memory test must be completed before dies are committed to a stack. Wafer probers come mainly from Tokyo Electron, whose Prexa series replaced the Precio line, and from Tokyo Seimitsu, marketed as Accretech, with MPI Corporation serving engineering and specialty segments.
Probe cards are produced by a separate group of specialists. FormFactor and Technoprobe lead advanced logic and memory probe cards, Micronics Japan and Japan Electronic Materials hold strong positions in DRAM and HBM probe cards, and MPI Corporation supplies vertical and cantilever designs. Probe card production combines semiconductor-style MEMS fabrication, precision assembly and design services, because each card is engineered for a specific die layout. That custom element is a large share of the value added in the chain and explains why probe cards behave as a recurring consumable revenue stream rather than a one-time capital purchase.
Burn-in and stress screening equipment follows a different path. Wafer-level burn-in systems such as Aehr Test Systems' FOX-XP, used with its WaferPak full-wafer contactors, apply voltage and temperature stress to every die on a wafer before singulation. Aehr extended its scope to package-level burn-in for AI processors through the Incal Technology acquisition announced in July 2024. Cohu, which entered silicon carbide burn-in test in October 2024, supplies handlers, contactors and inspection platforms, including its Neon optical inspection system for HBM micro-pillars.
The most important change at this stage is the shift from selling separate tools to delivering integrated KGD test cells. Advantest launched a KGD test cell for power semiconductors in December 2024 that pairs its CREA MT testers with the HA1100 die prober. In December 2025 Advantest and Tokyo Seimitsu announced joint development of a die-level prober aimed at the thermal demands of AI and HPC devices, and in June 2026 Teradyne and Tokyo Electron introduced a cell combining UltraFLEXplus with the Prexa SDP prober for AI and data-center dies. Integration adds value because it shortens the time needed to correlate tester, prober, probe card and thermal control, which is often the longest part of bringing up a new KGD flow. It also creates dependencies: a cell built around one tester and one prober favours the probe cards and thermal heads that have already been qualified with it.
Probe card fabrication itself carries several dependencies that shape value capture at this stage. Each new device generation, for example a move to a finer micro-bump pitch on an HBM base die or a larger reticle-sized AI processor, requires a new card design, new probe geometry and often a new space transformer, so probe card makers must reserve MEMS fabrication and assembly capacity months in advance of a customer's ramp. Card lead times, rather than tester availability, frequently set the pace at which a new KGD flow can enter production. Card makers also depend on accurate design data from the chip owner and on early access to test wafers, which tends to favour suppliers that already hold a position at the customer. This is one reason why FormFactor's purchase of a manufacturing site in Farmers Branch, Texas, in June 2025, with roughly 50,000 square feet of cleanroom, and Technoprobe's second probe card factory in Suzhou, launched in 2026 under its China-focused Nexprobe brand, are directed at adding capacity close to demand.
Distribution, Service and Test Services
Distribution in this market is almost entirely direct. Testers, probers and burn-in systems are sold through the suppliers' own account teams and applications engineers, who work with the customer's product and test engineers for months before a production order. Regional subsidiaries in Taiwan, South Korea, Japan, China, Singapore, Malaysia and the United States provide installation, calibration and spare parts, and service contracts are a material and stable source of supplier income. Probe cards add a further service layer: cards are repaired, re-tipped, cleaned and re-planarised at regional service centres, and a probe card supplier with a nearby repair site has a practical advantage because downtime on a high-value AI or HBM wafer is costly.
The second channel is test as a service. Many chip owners do not run their own test floors and instead buy wafer sort, burn-in and die-level test from OSATs and independent test houses. ASE and Amkor run large test operations alongside packaging, while KYEC in Taiwan specialises in test and is a key supplier of test capacity for leading AI processors. In July 2026 KYEC announced an investment of up to US$1.4 billion in a United States facility, and in April 2026 ASE broke ground on a large IC test facility in Renwu, Kaohsiung, with operations planned from April 2027. These service providers buy equipment and probe cards from the supplier tier and resell test time, so they capture value through utilisation, test program engineering and the ability to run multi-site, high-parallelism test economically.
Supplier relationships at this stage are becoming more structured. Teradyne's investment in a 10% stake in Technoprobe, completed in May 2024, and Advantest's non-controlling stakes in FormFactor and Technoprobe announced in January 2025 and in Micronics Japan announced in February 2025, show tester makers securing access to probe card technology and capacity. For customers this reduces integration risk, while for smaller probe card and handler suppliers it raises the bar for qualification on the leading tester platforms.
Commercial terms in this stage differ by product type. Testers and probers are sold as capital equipment with multi-year service agreements and software licences that unlock additional instruments or test capacity, so a supplier's revenue from an installed system continues well after the initial sale. Probe cards, contactors, sockets and burn-in boards behave as consumables: they wear out, must be replaced for each new device design and are purchased from operating budgets, which gives suppliers a recurring revenue base that follows wafer starts and test volumes. Wafer-level burn-in contactors, such as Aehr's WaferPak, follow the same pattern, since each device design needs its own contactor set. Test service providers price their offer per hour of tester time or per tested wafer, and their margins depend on keeping expensive test cells loaded. When demand for AI processors and HBM rises faster than test capacity, test houses gain pricing power over chip owners, while in slower periods equipment suppliers concentrate on service and consumables to stabilise revenue.
End Users and Ownership of Test Decisions
The final stage is the set of organisations that own the decision to test a die before assembly. Foundries that also perform advanced packaging, most visibly TSMC with its CoWoS and SoIC flows, need known good dies before they place logic chiplets and HBM stacks on an interposer, and they increasingly run probe and die-level test in-house. Memory makers such as SK hynix, Samsung and Micron are IDMs that test DRAM core dies and base logic dies at wafer level and then test the completed stack before shipment to an accelerator maker, which makes them among the most demanding users of known-good-stack testing. Power device IDMs including Infineon, STMicroelectronics, onsemi and Bosch test silicon carbide and gallium nitride dies before mounting them into multi-die traction modules, where one weak die can force the scrapping of a module.
OSATs act both as end users of equipment and as service providers for fabless companies and hyperscalers designing their own accelerators. The chip owner, often a fabless company, sets the quality targets, defines the test program with its test partner and decides how much test to do at the wafer, die and stack stages. Because the cost of a defect rises sharply at each assembly step, the chip owner's choice of where to place screens drives demand across the chain. The strongest dependency at this stage is on yield data: the value created by KGD testing is realised only when test results are fed back to design, wafer fabrication and assembly so that the right dies are binned and assembled, which is why data analytics capability, such as the AI-based process control Cohu added through Tignis in January 2025, is becoming part of the offer.
Across the chain, the main dependencies are therefore a concentrated supply of probe card substrates and probes, a small number of tester and prober platforms on which test content is built, a test-service tier clustered in Taiwan, South Korea and Southeast Asia, and a demand base driven by a limited number of AI accelerator, HBM and power device programmes. Value is captured mostly by the participants who control contact technology, platform architecture and test data.
Known good die testing is shaped less by product-specific rules than by three broader groups of regulation: export controls and industrial policy that decide where advanced chips are made and tested, qualification and test standards that define what a known good die must demonstrate, and environmental rules that affect the materials and fluids used in test equipment.
North America
In the United States, the CHIPS and Science Act signed in August 2022 provides manufacturing incentives administered by the CHIPS Program Office within the Department of Commerce, together with research funding that includes the National Advanced Packaging Manufacturing Program. Its significance for KGD testing lies in the support it gives to domestic advanced packaging and test capacity, such as Amkor's packaging and test campus in Arizona, whose CHIPS award was finalised in December 2024, and SK hynix's advanced packaging plant in West Lafayette, Indiana, announced in April 2024. Each of these facilities requires wafer probe, die-level and stack-level test capability on U.S. soil.
The Bureau of Industry and Security has issued successive export control rules on advanced computing items and semiconductor manufacturing equipment, notably in October 2022, October 2023 and December 2024. The December 2024 rules added controls on high-bandwidth memory, which directly affects where HBM stacks can be shipped and therefore where known-good-stack testing capacity is located. These rules remain in force and are periodically updated, so suppliers of testers, probers and probe cards must screen end users and end uses, particularly for shipments to China.
On the technical side, U.S.-based bodies set many of the standards that define KGD quality. JEDEC, headquartered in the United States, publishes the JESD47 stress-test-driven qualification guideline, the JESD22 family of reliability test methods and the HBM standards, including the HBM4 standard JESD270-4 published in April 2025. The Automotive Electronics Council's AEC-Q100 for integrated circuits and AEC-Q101 for discrete semiconductors set the stress qualification expected of dies supplied into vehicles. For defence and space, MIL-STD-883, including Test Method 1015 for burn-in, and MIL-PRF-38534 for hybrid microcircuits define screening requirements for die elements used in multi-chip assemblies. Canada and Mexico generally align with these U.S. and international standards, and both are covered by U.S. supply chain programmes that encourage regional back-end investment.
In Canada, federal and Quebec support for the IBM packaging and test operation in Bromont and for the C2MI research centre has focused on keeping advanced back-end capability in North America, while Infineon's completion of its GaN Systems acquisition in October 2023 tied an Ottawa-based gallium nitride design base to a European power device IDM. Mexico's role is shaped by the United States–Mexico–Canada Agreement, whose rules of origin and customs treatment influence where electronics and automotive assemblies containing tested dies are produced. For test equipment suppliers, the practical regulatory requirements across North America are export classification, customs compliance for equipment and consumables moving across borders, and product safety certification of test systems, which typically follows UL and IEC electrical safety standards.
Europe
The European Chips Act entered into force on 21 September 2023. It created a framework for state aid to first-of-a-kind facilities, a pilot line programme and a monitoring mechanism for supply disruptions. Projects relevant to KGD testing include the ESMC fab in Dresden, a joint venture of TSMC, Bosch, Infineon and NXP whose groundbreaking took place in August 2024, Infineon's Smart Power Fab in Dresden and STMicroelectronics' silicon carbide campus in Catania, approved in 2024. Power device and automotive projects of this kind increase demand for die-level and burn-in screening of silicon carbide and gallium nitride dies. Not every project has proceeded: Intel stated in July 2025 that it would not continue with its planned fab in Magdeburg. Discussion of a revised Chips Act framework has continued in 2025 and 2026.
European environmental regulation has a direct bearing on test equipment. The Restriction of Hazardous Substances Directive limits certain substances in electrical and electronic equipment, including test systems sold in the EU. Under REACH, the European Chemicals Agency is reviewing a broad restriction proposal on per- and polyfluoroalkyl substances first published in February 2023. The proposal remains under evaluation, and its outcome matters for fluorinated heat-transfer fluids used in some thermal test systems and for certain fluoropolymer components. Equipment makers are already qualifying alternative fluids, partly in response to 3M's exit from PFAS manufacturing by the end of 2025. For functional safety, ISO 26262:2018 applies to road vehicles and is widely used by European automotive suppliers to set the defect-rate and test coverage expectations that flow down to die suppliers.
Europe's equipment and probe card base is itself subject to these rules. Technoprobe, headquartered in Italy, is a leading probe card supplier, and Advantest maintains a significant research and development presence in Germany, so EU environmental, product safety and export control requirements apply to equipment designed and built within the region as well as to imports. The EU Dual-Use Regulation, recast in 2021, governs exports of controlled items from member states, and the Netherlands and other member states have added national controls on certain advanced semiconductor equipment since 2023. The Machinery Regulation adopted in 2023, which will replace the Machinery Directive from January 2027, will also apply to automated test handling systems placed on the EU market.
Asia Pacific
In Asia Pacific, regulation is dominated by industrial policy. China's National Integrated Circuit Industry Investment Fund raised a third phase in May 2024 with registered capital of RMB 344 billion, supporting domestic chip production and equipment development, including test and probe card suppliers. China has also applied export controls on gallium and germanium since August 2023, which affects the supply of materials used in compound semiconductor devices whose dies are tested before module assembly.
Japan has funded new capacity through subsidies to TSMC's JASM fab in Kumamoto, which opened in February 2024, and to Rapidus, which started its 2 nm pilot line in Hokkaido in April 2025 and plans to include back-end and chiplet work in its programme. Japan also maintains its own export controls on advanced semiconductor equipment, aligned in part with U.S. measures. South Korea supports its memory and packaging base through tax credits for national strategic technologies, while Taiwan provides incentives for research and advanced manufacturing that support the island's test-service and advanced packaging cluster. India's Semiconductor Mission provides fiscal support for fabs and for assembly, test, marking and packaging units, including Micron's Sanand facility approved in June 2023 and later OSAT approvals such as the HCL and Foxconn venture approved in May 2025. Malaysia launched its National Semiconductor Strategy in May 2024 to move its large back-end base toward more advanced packaging and test.
Technical standards in the region follow JEDEC, AEC and IEEE practice. IEEE 1838-2019, which defines test access for dies in a three-dimensional stack, and the UCIe 2.0 specification of August 2024, which adds test and debug features for chiplet interconnects, are particularly relevant to the HBM and chiplet programmes concentrated in Taiwan and South Korea.
Status differs across the region. China continues to expand domestic support and to tighten its own controls on critical minerals, while the United States and allied export rules restrict Chinese access to certain advanced testers and to HBM. Japan's and South Korea's measures are active and periodically renewed, and India's Semiconductor Mission has moved from approving projects to supporting their construction and early operation, with discussion during 2025 and 2026 of a follow-on phase. For suppliers, these differences mean that the same tester or probe card may face different licensing conditions depending on the customer's location and the device being tested, and that customer audits increasingly check equipment provenance and end-use declarations.
Rest of the World
In Latin America, the Middle East and Africa, regulation affecting KGD testing is mainly about investment incentives and trade rules rather than test standards. Brazil supports semiconductor activity through incentive programmes for the electronics and semiconductor sectors and reversed the liquidation of its state chip company CEITEC in 2023. Argentina maintains the special industrial regime in Tierra del Fuego for electronics assembly. In the Gulf, the Saudi National Semiconductor Hub launched in 2024 and large AI computing programmes such as Saudi Arabia's HUMAIN and the UAE's Stargate UAE campus, both announced in May 2025, are subject to U.S. export licensing for advanced AI processors. Test equipment and probe cards imported into these regions must comply with the same export screening as elsewhere, and local qualification generally references international JEDEC, AEC and IEC standards.
Israel, which accounts for much of the advanced semiconductor activity in the Middle East through Intel's Kiryat Gat operations, Tower Semiconductor and a large chip design community, applies its own export control regime and works closely with U.S. standards and licensing practice. Türkiye and Egypt are developing electronics manufacturing policies but have little KGD testing capacity today. In South Africa, demand for tested dies comes indirectly through the automotive industry, where vehicle makers supply export markets that require AEC-qualified components and ISO 26262-compliant electronic systems. Across these regions the current regulatory status is therefore one of import compliance and investment promotion rather than test-specific rule-making, and any future local KGD capacity is likely to follow the qualification standards already used by the global customers it serves.
Recent developments show three patterns: suppliers are forming equity and technology links across the test cell, new products target the thermal and contact demands of AI and HBM devices, and capacity investments are expanding the base of probe card manufacturing. Table 11.2 lists confirmed product launches, acquisitions, partnerships and expansions by the companies covered, in date order.
07 Nov 2023: Teradyne; Technoprobe; Partnership; Teradyne agreed to invest about USD 516 million for a 10% stake in Technoprobe, and Technoprobe agreed to acquire Teradyne's Device Interface Solutions business for about USD 85 million.
27 May 2024: Technoprobe; Teradyne; M&A; The Teradyne investment in Technoprobe closed, completing the transactions that transferred Teradyne's Device Interface Solutions business to Technoprobe.
16 Jul 2024: Aehr Test Systems; M&A; Aehr agreed to acquire Incal Technology, a supplier of package-level burn-in and test systems for AI and high-performance computing processors, for USD 21 million.
31 Oct 2024: Cohu; Product Launch; Cohu announced its entry into the silicon carbide burn-in test market.
10 Dec 2024: Advantest; Product Launch; Advantest launched a KGD test cell for power semiconductors that combines its CREA MT Series testers with the HA1100 die prober for SiC and GaN dies.
07 Jan 2025: Cohu; M&A; Cohu completed the acquisition of Tignis, adding AI-based process control and analytics software to its portfolio.
08 Jan 2025: Advantest; FormFactor; Technoprobe; Partnership; Advantest took non-controlling equity stakes in FormFactor and Technoprobe and formed partnerships covering joint technology development and circuit board production.
27 Feb 2025: Advantest; Micronics Japan; Partnership; Advantest and Micronics Japan signed a partnership to offer joint test solutions, with Advantest planning to acquire a minority stake in Micronics Japan.
02 Jun 2025: FormFactor; Expansion; FormFactor acquired a manufacturing site in Farmers Branch, Texas, for USD 55 million, including about 50,000 square feet of cleanroom space.
04 Aug 2025: Teradyne; Product Launch; Teradyne unveiled the Magnum 7H memory tester for high-bandwidth memory devices, covering HBM2E, HBM3 and HBM4.
16 Dec 2025: Advantest; Tokyo Seimitsu; Partnership; Advantest and Tokyo Seimitsu announced the joint development of a die-level prober for AI and HPC devices, addressing heat generated during test.
08 Jun 2026: Teradyne; Tokyo Electron; Product Launch; Teradyne introduced an integrated KGD test cell combining its UltraFLEXplus platform with Tokyo Electron's Prexa SDP prober for AI and data-centre chips.
Political
Political factors have a direct effect on where known good dies are tested. Export controls on advanced computing chips, high-bandwidth memory and semiconductor tools, tightened by the United States in October 2022, October 2023 and December 2024, determine which customers can receive leading-edge test capacity and which devices can be shipped across borders after test. Governments now treat advanced packaging and test as strategic capacity, so subsidy programmes in the United States, the European Union, Japan, India and Malaysia increasingly fund back-end projects that need wafer probe, burn-in and die-level test equipment. At the same time, China's policy of domestic substitution supports local tester and probe card suppliers, which gradually reduces the addressable share of China's demand open to foreign suppliers in mature-node and domestic segments.
Trade tensions also affect the cost and timing of equipment deliveries. Tariff measures and licensing reviews introduced since 2025 have led suppliers and customers to reassess where test cells are built and shipped from, and several OSATs and test houses have announced capacity in the United States, Singapore and Malaysia partly to offer customers geographically diversified test options. KYEC's announcement in July 2026 of up to US$1.4 billion for a U.S. facility reflects this political pressure to locate test near end customers.
Economic
The economics of KGD testing are tied to the cost of a failed assembly. As AI accelerators combine large logic dies with several HBM stacks on a silicon interposer, the value placed at risk by a single defective die grows, which makes additional test before assembly economically justified even when it adds cost per die. Capital spending on AI infrastructure by hyperscalers and the build-out of HBM capacity by memory makers drive orders for testers, probe cards and burn-in systems, while weaker periods in smartphones, personal computers and industrial markets reduce demand for test in RF, MEMS and consumer devices. Currency movements matter because several leading suppliers are Japanese and report in yen, while most customer budgets are set in U.S. dollars.
The cost structure of the market also changes the economic case for each test step. Probe cards for advanced HBM and AI processor dies are expensive custom items, high-power burn-in equipment requires significant facility investment in power and cooling, and test time on high-end testers is costly. Chip owners therefore balance the cost of extra test against the expected scrap savings, and this balance shifts in favour of more pre-assembly test as the number of dies per package and the cost of interposers and substrates increase.
Social
Social factors work mainly through talent and through end-user expectations. Test engineering for KGD requires expertise in test program development, probe card design, thermal engineering and data analysis, and the semiconductor industry in the United States, Europe, Japan and Taiwan reports shortages of such engineers as new back-end facilities are built. Training programmes linked to national semiconductor strategies, including those in India and Malaysia, aim to address this gap. On the demand side, expectations of reliable AI services, vehicle safety and medical device dependability raise tolerance for higher test cost when it improves field reliability.
Public awareness of data-center reliability has grown as AI services become part of everyday work, and hyperscalers publish more information on silent data errors and hardware failures in their fleets. This visibility increases pressure on chip suppliers to screen for marginal dies that may pass a standard test but fail in service, which supports demand for extended burn-in and stress screening of AI processors and server memory.
Demographic change in established semiconductor regions adds to the talent challenge. Japan and Taiwan in particular face ageing workforces in manufacturing engineering, while new back-end sites in the United States, India and Southeast Asia must recruit and train technicians quickly, which favours equipment with higher automation and simpler operation.
Technological
Technology is the strongest external influence on this market. The move to chiplets and 2.5D and 3D integration, the transition from HBM3E to HBM4 with more dies per stack and a wider interface, and the use of hybrid bonding all reduce the pitch of contact pads and raise the number of contacts per die. These changes require finer-pitch MEMS probe cards, low-force probing that does not damage bonding surfaces, and active thermal control for dies that dissipate high power during test. Standards such as IEEE 1838 and UCIe 2.0 improve test access to stacked dies and chiplet links. Data analytics and machine learning are increasingly applied to test results to predict reliability and adapt test content, reducing test time without losing coverage.
Thermal management is a further technological constraint. AI processor and HBM base dies can draw very high current during test, and probing such dies without overheating the device or the probe card needs active thermal control at the chuck and, increasingly, at the probe card itself. The joint die-level prober development announced by Advantest and Tokyo Seimitsu in December 2025 targets exactly this heat-handling problem.
Environmental
Environmental factors affect both equipment design and test operations. Burn-in and high-power die-level testing consume large amounts of electricity and require cooling, so customers increasingly evaluate equipment on energy per tested die. Restrictions on PFAS, including the REACH restriction proposal under review by the European Chemicals Agency and 3M's exit from PFAS manufacturing by the end of 2025, push suppliers toward alternative heat-transfer fluids and materials. Screening dies before assembly also has an environmental benefit, because it reduces the scrapping of interposers, substrates, HBM stacks and power modules that embody significant energy and materials.
Customers are also adding environmental criteria to supplier selection, including equipment energy efficiency, refrigerant choice in thermal units and the recyclability of probe cards and burn-in boards. Large IDMs and foundries have published decarbonisation targets for their operations, and test floors, which run continuously, are part of the electricity consumption these targets cover.
Legal
Legal factors include export licensing, intellectual property and product liability. Suppliers and test service providers must classify equipment and screen end users under U.S., Japanese, Dutch and other export control regimes, and errors can lead to penalties and loss of export privileges. Intellectual property is concentrated in probe structures, tester architectures and test methods, and patent protection is an important competitive tool for probe card and tester makers. In automotive and medical markets, functional safety obligations under ISO 26262 and quality agreements based on AEC-Q100 and AEC-Q101 transfer defect-rate commitments from vehicle makers to chip suppliers, which then specify more thorough KGD screening to manage their own contractual exposure.
Contract law also shapes the market through quality agreements between chip owners and their foundry and OSAT partners. These agreements set yield and defect-rate commitments, define responsibility for failures found after assembly, and specify data-sharing requirements for test results. As multi-die packages combine dies from different suppliers, for example HBM from a memory maker and logic from a foundry, the allocation of liability for a failed package depends on demonstrating that each die met its KGD specification, which increases the importance of traceable test records.
Profiles of 36 companies operating in the Known Good Die Testing Market market, including revenue, employee count, and market positioning where available.
Showing 36 of 36 companies
Cohu is a mid-cap U.S. supplier of back-end semiconductor manufacturing equipment and services. Its business centres on the final-test cell: the test handlers that move and thermally condition packaged chips, the contactors and probes that connect each device to the tester, the automated test equipment (ATE) itself, and the vision inspection and metrology systems that screen finished devices. Around this hardware sits a large recurring business in spares, kits, consumable contactors, service and, increasingly, software. That software includes DI-Core equipment analytics and the AI process-control tools from Tignis, which together give Cohu a role in data-driven yield management and manufacturing traceability across test floors. The company was built through acquisitions (Delta Design, Rasco, Ismeca, Kita and Xcerra), and it has been the leading supplier of test and inspection handlers to automotive, industrial and mobile chipmakers. Since 2025 it has been moving into AI data-centre computing: its Eclipse handler with T-Core active thermal control, and Neon inspection systems for high-bandwidth memory (HBM), now account for a growing share of orders. That shift has brought Cohu's highest growth in years, although profitability is still recovering. --- ### What the company does Cohu describes itself as a global supplier of equipment and services that improve semiconductor manufacturing yield and productivity, with a portfolio of test, automation, inspection and metrology products, software analytics and services for the semiconductor industry. Its equipment works in the "back end" of chip manufacturing, after wafers are processed. Devices are tested at wafer level or in packaged form, sorted by performance grade, inspected for physical defects and then shipped. Cohu sells into integrated device manufacturers (IDMs), fabless chip companies that set test strategy, outsourced semiconductor assembly and test (OSAT) subcontractors, memory makers and foundries. The FY2025 10-K reports an active installed base of more than 25,000 systems, serving more than 280 high-volume manufacturing facilities for 108 customers in 31 countries. The ten largest customers accounted for 60% of FY2025 revenue. STMicroelectronics was the only customer above 10% of consolidated net sales in the last three years, at 12.0% in FY2023; no customer reached that level in FY2024 or FY2025. ### Business and revenue model | Revenue mix (% of net sales) | FY2023 | FY2024 | FY2025 | |---|---|---|---| | Systems (%) | 51 | 35 | 40 | | Recurring (%) | 49 | 65 | 60 | Cohu has two revenue streams: systems and recurring. **Systems:** are capital equipment: test handlers (pick-and-place, turret, gravity, strip, MEMS), thermal subsystems, semiconductor testers (Diamondx, PAx) and inspection/metrology systems (Neon, Krypton). Systems revenue rises and falls with customer capital spending and with test-cell utilisation. **Recurring:** revenue is tied to the installed base: contactors, probe heads and probe pins (consumables that wear out with use), device-specific change kits, spare parts, service contracts and software subscriptions (DI-Core, the PAICe tools, the PACE inspection software). It is less volatile than systems revenue. **Systems (%):** FY2023: 51; FY2024: 35; FY2025: 40 **Recurring (%):** FY2023: 49; FY2024: 65; FY2025: 60 Source: FY2025 Form 10-K. The mix swings sharply with the cycle. Recurring revenue made up about two-thirds of sales at the FY2024 trough. It fell to 48% of Q3 FY2026 revenue as systems shipments for AI computing ramped up. Systems accounted for 59% of Q3 FY2026 bookings. Software is still small: Q2 FY2026 was the first quarter in which software analytics revenue reached USD 1 million, and software orders that quarter rose about 140% year-on-year. ### Value-chain position Cohu sits between the ATE majors (Teradyne, Advantest), which supply the tester "brain", and the chipmakers and OSATs that run test floors. Its handlers and contactors are the mechanical, thermal and electrical interface that lets a tester work at production volume. Because Cohu also sells testers (Diamondx, PAx) and inspection systems, it can offer much of a full test cell, but it competes directly with Teradyne and Advantest only in mid-range ATE for power, analog, mixed-signal and RF devices. Most testers are manufactured for Cohu by Jabil at a Jabil facility in Malaysia. Handlers and inspection systems are built in Cohu's own plants in Melaka and Penang (Malaysia), and interface products are made in the Philippines and Japan. ### End-markets Cohu's traditional strengths are automotive (ADAS processors, power devices, microcontrollers), industrial, mobile (RF front-end modules, power-management ICs) and consumer. From 2025 onward, computing became the growth driver: AI and high-performance computing (HPC) processors, networking ASICs, silicon photonics and HBM. Computing accounted for 46% of system orders in Q2 FY2026, and computing orders grew 150% year-on-year that quarter. Management expects FY2026 HPC revenue of about USD 120 million, compared with roughly USD 11 million of HBM inspection revenue and a small base of other computing revenue in FY2025. ### Independent characterisation Cohu is a cyclical back-end equipment company with an unusually high recurring share, and it is in the middle of a portfolio rotation. Its handler and contactor franchise in automotive and industrial semiconductors is strong but mature and depends on the cycle. Between FY2022 and FY2024 revenue fell by more than half as test-cell utilisation collapsed at IDM customers. In 2025 and 2026 Cohu used its thermal-control know-how from high-power microprocessor testing, a field Delta Design pioneered around 2000, to win AI-accelerator and networking test programmes. It used vision inspection inherited from Ismeca to enter HBM inspection. The investment case now depends mainly on whether these computing programmes reach repeat production volume and whether margins can expand while new products ramp.
Advantest is the world's largest supplier of automatic test equipment (ATE) for semiconductors, the instruments that check chips electrically before they ship. Its share of the global tester market rose from 58% in CY2024 to 65% in CY2025, according to its 2026 Integrated Annual Report. Its V93000 SoC platform is the standard production tester for the AI accelerators, GPUs and high-performance processors driving the current semiconductor cycle. Its T5000-series memory testers are central to high-bandwidth DRAM (HBM) production. Around these core testers the company has built a wider "integrated test solution" offering: test handlers, device interfaces and test boards, system-level and burn-in test, test-cell software, cloud and real-time data analytics, and photomask metrology SEMs. Almost all sales (97.8% in FY2025, 99.4% in H1 FY2026) come from outside Japan, mainly Taiwan, Korea and China. AI-driven demand has transformed the company's scale and profitability. Net sales rose from JPY 486.5 billion in FY2023 to JPY 1,128.6 billion in FY2025, and the FY2026 guidance is JPY 1,863.0 billion with a 51.9% operating margin. Advantest is now one of Japan's most valuable listed companies. --- **What the company does.** Advantest designs, manufactures, sells and services equipment that tests semiconductors at several points in the value chain: design verification and silicon validation, wafer sort, final test after packaging, burn-in and system-level test (SLT). Its customers are integrated device manufacturers (IDMs), fabless chip designers, foundries and outsourced semiconductor assembly and test companies (OSATs). Fabless designers often specify the tester even when an OSAT or foundry buys and runs it. The company also makes test handlers that move devices into and out of the tester, device-interface hardware (test boards, sockets, probe-card interfaces), and scanning electron microscopes used to measure photomasks. **The company's own description.** Advantest calls itself the leading maker of automatic test and measurement equipment used to design and produce semiconductors for high-performance computing (HPC), AI, automotive, industrial and consumer applications. It says it offers test solutions across the semiconductor value chain, covering wafer sort and final test, design verification and silicon validation, system-level test, test handlers, device interfaces, photomask SEMs and yield-improving data analytics. Its vision statement is "Be the most trusted and valued test solution company in the semiconductor value chain," and its purpose is "Enabling Leading-Edge Technologies." **Independent characterisation.** In economic terms, Advantest has become a near-monopoly supplier of production test capacity for leading-edge AI silicon. Two forces drive its revenue. The first is unit volume of complex devices (GPUs, custom AI ASICs, HBM stacks, networking chips). The second is test intensity per device, which rises with transistor count, chiplet integration, advanced packaging (2.5D/3D, CoWoS-class), higher power and the need for "known good die" before costly packaging. Each new AI-processor generation needs more tester time per unit, more digital and power channels per tester, and more test steps (wafer-level, final and SLT). As a result, tester demand has grown faster than semiconductor revenue. This explains why Advantest's sales grew 44.7% in FY2025, while management expects the overall semiconductor market to grow more modestly, possibly passing USD 1 trillion in CY2026. **Business and revenue model.** Revenue is mainly product sales of capital equipment (test systems, handlers), plus a growing recurring base: consumable device-interface products (test boards and interfaces from R&D Altanova and Shin Puu), field service and support contracts, spare parts, software licences (SmarTest, ACS cloud and real-time data offerings, Velocity EDA from AllianceATE) and upgrades. **SoC test systems:** FY2025 sales (JPY bn): 767.4; Share of total: 68.0%; Nature: Capital equipment, product sale **Memory test systems:** FY2025 sales (JPY bn): 171.5; Share of total: 15.2%; Nature: Capital equipment, product sale - **Other systems (handlers, device interfaces, nanotechnology, SLT etc.)** — FY2025 sales (JPY bn): 80.5; Share of total: 7.1%; Nature: Equipment and semi-consumables - **Services & others (support services, consumables, software, other)** — FY2025 sales (JPY bn): 109.2; Share of total: 9.7%; Nature: Recurring service, consumables, licences **Total:** FY2025 sales (JPY bn): 1,128.6; Share of total: 100.0% Licensing and subscription revenue is not reported separately. **Value-chain position.** Advantest is a back-end and test-stage equipment supplier. It sits downstream of front-end wafer-fab tools (lithography, deposition, etch), alongside probers and probe cards at wafer sort, and alongside packaging and assembly equipment at final test. Joining Applied Materials' EPIC platform in April 2026, as the first ATE company to do so, signals a strategy to link front-end process development with back-end test data. **Customer types and end-markets.** In FY2025, 95% of SoC tester sales went to computing and communications devices and 5% to automotive, industrial, consumer and display-driver ICs. The FY2026 forecast is 90/10. Memory tester sales were 90% DRAM (driven by HBM and high-performance DRAM) and 10% non-volatile memory in FY2025, moving to 85/15 in the FY2026 forecast. Mature-node automotive and industrial demand stayed soft through FY2025.
Tokyo Electron is Japan's largest semiconductor equipment maker and one of the four or five global companies that set the pace of wafer-fab equipment (WFE) technology. It sells front-end tools for coating and developing photoresist, plasma etching, thermal and single-wafer deposition, wafer cleaning, wafer probing and, increasingly, wafer bonding and laser processing for advanced packaging. In coater/developers it holds a near-monopoly, and in EUV-lithography tracks it is effectively the sole supplier. Its customers are the leading logic foundries, DRAM and NAND makers, and a broad base of Chinese mature-node fabs. About 90% of sales go outside Japan. A Field Solutions business for parts, service, upgrades and refurbished tools, built on an installed base of more than 90,000 systems, supplies a growing recurring layer. In FY2026 TEL booked record sales of ¥2.44 trillion. Its first full-year forecast for FY2027 calls for ¥3.7 trillion in sales and operating income above ¥1 trillion for the first time, on the back of AI-driven investment in advanced logic, HBM/DRAM and 3D NAND. ### What the company does Tokyo Electron designs, develops, manufactures, sells and services production equipment used to fabricate semiconductors. Its tools cover most of the non-lithography steps in front-end-of-line and middle-of-line processing: - coating and developing photoresist around the scanner; - etching patterns into films; - depositing films by batch thermal processes, chemical vapour deposition and atomic layer deposition; - removing particles and residues; - testing finished dies on the wafer with probers. TEL also supplies wafer-to-wafer and die-level bonding, laser lift-off and thinning equipment for 3D integration and advanced packaging, and a small line of flat-panel display (FPD) production equipment. TEL describes itself in its Japanese securities report as a group operating in the single business of semiconductor production equipment. It covers research, development, manufacturing, sales and maintenance, and FPD equipment is reported within that segment. Development and production sit in Japanese manufacturing subsidiaries: Tokyo Electron Technology Solutions for deposition and thermal tools, Tokyo Electron Kyushu for coater/developers, cleaning and bonding, and Tokyo Electron Miyagi for plasma etch. TEL Manufacturing and Engineering of America produces surface-preparation tools. Field engineering is delivered through Tokyo Electron FE in Japan and regional subsidiaries such as Tokyo Electron America, Tokyo Electron Korea, Tokyo Electron Taiwan and Tokyo Electron Europe. Logistics, facilities and insurance functions sit in Tokyo Electron BP. ### Business and revenue model | Revenue stream | Nature | FY2026 sales (¥bn) | Share of total | |---|---|---|---| | New equipment (SPE and FPD) | Capital equipment sold per tool, recognised mainly on customer acceptance | 1817.3 | 74.4% | | Field Solutions | Spare parts, service contracts, upgrades and modifications, used and refurbished equipment | 626.3 | 25.6% | | Total | — | 2443.5 | 100% | **New equipment (SPE and FPD):** Nature: Capital equipment sold per tool, recognised mainly on customer acceptance; FY2026 sales (¥bn): 1817.3; Share of total: 74.4% **Field Solutions:** Nature: Spare parts, service contracts, upgrades and modifications, used and refurbished equipment; FY2026 sales (¥bn): 626.3; Share of total: 25.6% **Total:** FY2026 sales (¥bn): 2443.5; Share of total: 100% The model is product-led and cyclical. Tools are sold to fab owners, and revenue is recognised mostly on customer acceptance, so quarterly results swing with acceptance timing. The fourth quarter, which contains the fiscal year-end acceptance month, is usually the largest. Field Solutions is the counter-cyclical layer. Its sales rose from ¥456.1 billion in FY2022 to ¥626.3 billion in FY2026, and reached ¥188.0 billion in the June 2026 quarter alone. It monetises the installed base through consumable parts, service contracts, productivity and node-extension upgrades, and resale of certified used tools. TEL does not run subscription or licensing businesses of any significance. Software and data services, such as remote diagnostics and process-control software, are bundled into equipment and service sales. ### Value-chain position TEL is a tier-1 capital-goods supplier to integrated device manufacturers, foundries and memory makers. Upstream it depends on a deep Japanese and global sub-supplier base: vacuum pumps, RF generators, valves, robotics, ceramics, quartz, specialty materials and precision machining. Downstream it sells directly to fab operators, without distributors. It co-develops processes with leading customers years before high-volume manufacturing, typically three or four technology generations ahead, and that early engagement is the source of most of its competitive moat. ### Customer types and end-markets | Customer type | Representative customers | Main TEL tools | Demand driver | |---|---|---|---| | Leading-edge logic and foundry | TSMC, Samsung Foundry, Intel, Rapidus | EUV tracks, etch, deposition, cleaning, bonding | 3 nm, 2 nm and 1.4 nm ramps, gate-all-around transistors, backside power | | DRAM and HBM | Samsung, SK hynix, Micron, CXMT | Etch, deposition, tracks, bonding | AI servers, HBM stacking | | NAND flash | Samsung, SK hynix, Kioxia, Micron, YMTC | High-aspect-ratio etch (including cryogenic), deposition | Layer-count increases, enterprise SSDs for AI | | Mature-node and specialty fabs | Chinese foundries and IDMs, power and analog makers | Thermal, deposition, cleaning, tracks | Localisation in China, automotive, industrial | | Advanced packaging | Foundries, OSATs, memory makers | Wafer bonders, laser lift-off, thinning | Chiplets, hybrid bonding, HBM | | Display makers | Panel producers | FPD etch/ash and inkjet systems | OLED investment | **Leading-edge logic and foundry:** Representative customers: TSMC, Samsung Foundry, Intel, Rapidus; Main TEL tools: EUV tracks, etch, deposition, cleaning, bonding; Demand driver: 3 nm, 2 nm and 1.4 nm ramps, gate-all-around transistors, backside power **DRAM and HBM:** Representative customers: Samsung, SK hynix, Micron, CXMT; Main TEL tools: Etch, deposition, tracks, bonding; Demand driver: AI servers, HBM stacking **NAND flash:** Representative customers: Samsung, SK hynix, Kioxia, Micron, YMTC; Main TEL tools: High-aspect-ratio etch (including cryogenic), deposition; Demand driver: Layer-count increases, enterprise SSDs for AI **Mature-node and specialty fabs:** Representative customers: Chinese foundries and IDMs, power and analog makers; Main TEL tools: Thermal, deposition, cleaning, tracks; Demand driver: Localisation in China, automotive, industrial **Advanced packaging:** Representative customers: Foundries, OSATs, memory makers; Main TEL tools: Wafer bonders, laser lift-off, thinning; Demand driver: Chiplets, hybrid bonding, HBM **Display makers:** Representative customers: Panel producers; Main TEL tools: FPD etch/ash and inkjet systems; Demand driver: OLED investment ### Independent characterisation TEL is best understood as a "process-breadth" toolmaker. It has a narrow lithography-adjacent monopoly in tracks, top-tier positions in etch and thermal deposition, and an expanding presence in bonding. Earnings power rests on three things: 1. **Process-step intensity.** Each new node and memory generation adds deposition, etch and patterning steps per wafer. 2. **Customer concentration.** A handful of leading-edge customers decide most of incremental WFE spending. 3. **China exposure.** China was 41.7% of sales in FY2025, 34.1% in FY2026, and is guided to the low 30s in FY2027. It is both a large profit pool and the main policy risk. TEL is structurally net-cash. It returns about half of net income as dividends and adds opportunistic buybacks, and it has been raising R&D toward ¥300 billion or more a year to defend share in etch and deposition against Applied Materials and Lam Research.
RTX occupies a structurally advantaged position that no other prime replicates: roughly half its revenue is commercial aerospace and half defence, giving it a natural hedge across two cycles that rarely peak together — and which, unusually, are peaking together in 2026. Collins Aerospace and Pratt & Whitney are entrenched on the installed base of the global narrowbody and widebody fleet, generating decades-long, high-margin aftermarket annuities. The Raytheon segment is the Western world's dominant supplier of ground-based air and missile defence effectors — Patriot, GEM-T, AMRAAM, Standard Missile, ESSM — precisely the munitions category that European rearmament and Middle East conflict have made scarce. A record $289 billion backlog at 30 June 2026, equal to roughly three years of sales, converts that positional advantage into unusual revenue visibility. The offsetting reality is that RTX carries $37 billion of debt, an $85 billion goodwill-and-intangible balance from the merger, and the unresolved cost tail of the GTF powder-metal remediation. RTX Corporation is the world's largest aerospace and defence company by revenue, and the only prime contractor that simultaneously holds franchise positions in commercial aircraft engines, commercial aerospace systems, and ground- and sea-based integrated air and missile defence. It was created in April 2020 by the merger of Raytheon Company with the aerospace businesses of United Technologies Corporation, and it renamed itself from Raytheon Technologies to RTX in July 2023 alongside a consolidation from four operating segments to three. --- ### What the company does RTX designs, manufactures, and services aerospace and defence systems for commercial airlines, aircraft OEMs, business aviation operators, the U.S. Government (principally the Department of Defense, latterly styled the Department of War in contract announcements), and allied governments worldwide. Its FY2025 Form 10-K describes the three segments as follows: Collins Aerospace provides advanced aerospace and defence products; Pratt & Whitney supplies aircraft engines; and Raytheon delivers defensive and offensive threat detection and mitigation capabilities. The company's independent characterisation is better expressed as three distinct economic engines bolted onto one balance sheet: 1. **An installed-base annuity business (Pratt & Whitney and, to a lesser degree, Collins).** Engines and nacelles are sold at or near cost — sometimes at a loss — to win position on an airframe, after which spare parts, overhauls, and long-term service agreements generate profit for twenty to thirty years. This is why Pratt & Whitney's reported segment margin (8.3% in FY2025) looks weak against Collins (16.2%) despite comparable revenue: Pratt is still absorbing original-equipment loss content on the GTF ramp while the aftermarket annuity has yet to reach maturity. 2. **A cost-plus and fixed-price government contracting business (Raytheon, plus Collins' defence lines).** Revenue is recognised over time on the percentage-of-completion basis, which makes reported margins highly sensitive to estimate-at-completion revisions. The FY2024 $575 million charge on a terminated foreign fixed-price development contract is the canonical illustration. 3. **A component and systems supply business (Collins).** Avionics, interiors, power management, and aerostructures sold to Airbus, Boeing, Embraer, Bombardier, and defence primes, with a large parts-and-repair aftermarket layered on top. ### Revenue model and mix | Metric | FY2025 | |---|---| | Commercial share of sales | 48% | | Defence share of sales | 52% | | Products share of sales | ~74% | | Services share of sales | ~26% | | Sales to U.S. Government (excl. FMS) | $33,279m (38% of net sales) | | Total international sales | $41,312m (47% of net sales) | | Total backlog | $268bn ($161bn commercial / $107bn defence) | | Backlog expected to convert within 12 months | ~25% | Sources: FY2025 Form 10-K Item 1 (U.S. government and international sales tables, backlog); RTX 2025 Annual Report sales-mix infographic; Q3 2025 disclosure for the product/service split. Note the structural shift: U.S. Government sales fell from 46% of revenue in FY2023 to 38% in FY2025 — not because U.S. volume declined (it rose from $31.6bn to $33.3bn) but because international and commercial revenue grew far faster. This is the single most important mix fact in the company today, because international direct commercial sales carry materially better margins than U.S. cost-type work, and because European air-defence procurement is the fastest-growing pool RTX addresses. ### Value chain position and customers RTX sits at the prime and Tier-1 layers simultaneously. On F-35 it is a major subsystem supplier (F135 propulsion via Pratt; sensors and avionics via Collins) to prime contractor Lockheed Martin — a direct competitor at the enterprise level. On Patriot and SPY-6 it is the prime. On A320neo it is a propulsion and nacelle supplier to Airbus, which in March 2026 was reported to be formally seeking damages from Pratt & Whitney over GTF disruption. This simultaneous supplier/competitor/counterparty posture across the same customer set is a defining feature of RTX's commercial relationships and a recurring source of litigation and negotiation risk. **End-markets served:** commercial air transport (OE and aftermarket); regional and business aviation; rotorcraft; military fixed-wing and rotary propulsion; integrated air and missile defence; naval combat systems; precision-guided munitions; space sensing and communications; airport and airline IT infrastructure; and government training and mission services.
### Identity and listing | Item | Detail | |---|---| | Entity profiled | Illinois Tool Works Inc. (exact legal-name match; active; publicly listed). The input classification "Public company" is confirmed | | Former names | None of significance disclosed. The company has operated as Illinois Tool Works since founding. Commonly abbreviated "ITW" | | Founded | 1912, Chicago, Illinois. Incorporated 1915 (Form 10-K FY2025) | | Jurisdiction of incorporation | Delaware, USA (Form 10-K FY2025) | | IRS Employer ID | 36-1258310 | | Headquarters | 155 Harlem Avenue, Glenview, Illinois 60025, USA. Tel. (847) 724-7500 | | Exchange / ticker | New York Stock Exchange: ITW (common stock) | | Other listed securities (NYSE) | Euro notes: 0.625% due 2027 (ITW27); 3.250% due 2028 (ITW28); 2.125% due 2030 (ITW30); 1.00% due 2031 (ITW31); 3.375% due 2032 (ITW32); 3.00% due 2034 (ITW34) | | ISIN / CUSIP | US4523081093 / 452308109 | | Fiscal year end | 31 December | | Index membership | S&P 500 constituent. Fortune 300 company (company description, 2026) | ### Scale and organisation | Item | Detail | |---|---| | Employees (latest) | About 43,000 at 31 Dec 2025; about 16,000 in the U.S. (Form 10-K FY2025) | | Employee trend | About 46,000 (FY2022 release); about 45,000 (FY2023); about 44,000 (FY2024 release); about 43,000 (FY2025). This is a steady decline driven by 80/20 simplification and productivity, not by revenue contraction | | Organisation | 88 divisions in 49 countries; about 410 plants and office facilities (Form 10-K FY2025) | | Auditor | Deloitte & Touche LLP. Ratification proposed for FY2026 (2026 Proxy) | | Holders of record | About 3,957 at 31 Jan 2026 | | Website | www.itw.com / investor.itw.com | ### Market data | Item | Detail | |---|---| | Shares outstanding | 288.2 million at 31 Jan 2026 (Form 10-K). About 284 million estimated at 30 Jun 2026, after 4.3 million shares were repurchased in H1 2026 (10-Q Q2 FY2026; derived) | | Market capitalisation (current) | About $82 billion. Basis: share price of roughly $288–$295 (5 Aug 2026 close $295.06; early-September 2026 dividend yield of 2.39% implies about $288) × about 284 million shares | | Market cap at 31 Dec 2025 | About $71 billion (2026 Proxy) | | Market cap discrepancies | Third-party aggregators show $71bn–$85bn depending on date. Live verification is recommended | | 52-week range | $238.82 – $303.16 (as of Aug 2026, aggregator data) | Illinois Tool Works is a 114-year-old, Glenview-based multi-industrial manufacturer with $16.0 billion of FY2025 revenue across seven segments: - Automotive OEM - Food Equipment - Test & Measurement and Electronics - Welding - Polymers & Fluids - Construction Products - Specialty Products ITW does not compete on scale or vertical integration. Its edge is a proprietary operating system, the "ITW Business Model," built on three elements: - **80/20 Front-to-Back management**, which concentrates resources on the largest, most profitable customers and products. - **Customer-Back Innovation (CBI)**, which develops products from customer pain points rather than from a central R&D lab. **A decentralised, entrepreneurial culture:** of 88 scaled-up divisions. Since launching its Enterprise Strategy in late 2012, ITW has lifted operating margin from 15.9% to 26.3% and after-tax ROIC from 14.5% to 29.3%. It has done this while shrinking revenue through divestiture of commoditised businesses (2026 Proxy). The "Next Phase" (2024–2030) pivots the agenda from margin expansion to sustained 4%+ organic growth, powered by a 3%+ CBI revenue yield. ITW is a Dividend King, with 63 consecutive annual dividend increases. --- ### Company's own description (Form 10-K FY2025, paraphrased) ITW describes itself as a global manufacturer of a diversified range of industrial products and equipment, organised into 88 divisions operating in 49 countries. Its seven reportable segments are grouped by similar product offerings and end markets. Products are distributed mainly direct to industrial manufacturers and through independent distributors. Backlog is not considered significant because delivery periods are short and inventory turns quickly. The company names its core competitive advantage as the ITW Business Model: - 80/20 Front-to-Back process - Customer-Back Innovation - Decentralised entrepreneurial culture Primary raw materials are steel, resins and chemicals, sourced from numerous commercial suppliers. ### Business model | Revenue type | Characterisation | Evidence | |---|---|---| | Product sales: consumables | Majority of revenue. Welding filler metals; Polymers & Fluids chemicals; fasteners; Hi-Cone carriers; marking inks; test consumables; contamination-control wipes | Segment product lists (10-K FY2025) | | Product sales: capital equipment | Welding power sources; food equipment; test systems (Instron, MTS); electronic assembly equipment; line automation | Segment product lists (10-K FY2025) | | Services | Food Equipment service, maintenance and repair (service organic growth +2.8% FY2025, +4.8% FY2024); aftermarket service in Test & Measurement | 10-K FY2025 Food Equipment discussion | | Software / subscription | Test & measurement software is embedded with equipment. Not reported separately | Not publicly disclosed | | Licensing | Not material / not disclosed | Not publicly disclosed | ITW's model rests on niche leadership in fragmented, technically demanding markets. Its businesses typically hold strong positions in specialised applications where: - the product is a small share of the customer's total cost but critical to performance (e.g., an automotive fastener, a weld wire, a test frame); and - differentiation comes from engineering, application know-how, brand and service. The 80/20 discipline continually prunes low-value SKUs and customers through Product Line Simplification (PLS). PLS deliberately reduced organic revenue by about 60 basis points in FY2024, about 60 bps in FY2025, and about 60 bps in H1 FY2026, in exchange for structurally higher margins (10-K FY2025; 10-Q Q2 FY2026). **Revenue model mix.** ITW does not report a formal product/service/subscription split. The analyst characterisation is: ### Value-chain position ITW sits as a Tier-1/Tier-2 component supplier (Automotive OEM, Specialty appliance components) and as an OEM of branded equipment and consumables (Welding, Food Equipment, Test & Measurement, Construction Products, Polymers & Fluids). It typically manufactures "in the market, for the market." This localisation was cited in FY2025 as the reason ITW could largely offset U.S. tariff costs through pricing and supply-chain actions (FY2025 release; 10-K FY2025). ### Customer types and end markets | Segment | Primary end markets (10-K FY2025) | Customer type | |---|---|---| | Automotive OEM | Automotive OEMs and tiers | Global and Chinese OEMs; Tier-1 suppliers | | Food Equipment | Food service, food retail, food institutional/restaurant | Restaurant chains, independents, institutions (healthcare, education), supermarkets | | Test & Measurement and Electronics | Electronics/semiconductor, general industrial, auto OEM/tiers, energy, industrial capital goods, consumer durables | R&D labs, quality labs, semiconductor fabs, electronics assemblers | | Welding | General industrial (fabrication, shipbuilding), construction, energy, MRO, capital goods, auto | Fabricators, contractors, OEMs; heavily via distributors | | Polymers & Fluids | Automotive aftermarket, general industrial, MRO | Retail auto-care, body shops, industrial maintenance | | Construction Products | Residential construction, renovation/remodel, commercial construction | Contractors, truss fabricators, big-box retail | | Specialty Products | Food and beverage, consumer durables, airlines, general industrial, capital goods, printing/publishing | Beverage packers, appliance OEMs, airports/airlines, packaging converters | ### Independent characterisation ITW is best understood as a portfolio of about 88 mid-sized, high-return niche franchises bound together by a common management system. Corporate allocates capital. Divisions run the business. Strengths of this structure: - A low-capital-intensity, cash-generative model. Capex was 2.6% of revenue in FY2025 ($419M on $16,044M), and after-tax ROIC is about 29–31%. - Demand is diversified across consumer, industrial and capex cycles. Weaknesses of this structure: - Organic growth has historically been modest (FY2023–FY2025 averaged roughly 0–2%). - PLS creates a built-in headwind to reported growth. - The company has unusually high exposure to Detroit-3 and European auto content, short-cycle construction, and the semiconductor capex cycle. The FY2026 data, with Q2 organic growth of +4.5% and double-digit growth in Welding and Test & Measurement, is the first meaningful evidence that the CBI-driven growth pivot may be gaining traction.
Dell Technologies is the world's largest branded server vendor by revenue and the third-largest personal computer vendor, and it is now the principal listed proxy for the migration of artificial-intelligence infrastructure from hyperscale cloud into enterprise, sovereign and neocloud data centres. Two reporting segments — Infrastructure Solutions Group and Client Solutions Group — generated $113.5bn of revenue in FY2026, and the business is running at an annualised revenue rate above $190bn in FY2027 on the strength of AI-optimised server demand. Dell's structural advantages are a direct-plus-channel go-to-market reaching customers in more than 170 countries, a supply chain that can integrate, liquid-cool and deploy rack-scale GPU systems at volume, an installed base served by a global support organisation, and a captive financing arm. Its structural constraints are thin hardware gross margins, a negative book equity position, high customer concentration in AI, and dependence on component suppliers whose pricing power currently exceeds its own. --- ### The company's own description In its FY2026 Form 10-K the Company describes itself as "a leader in the global technology industry focused on providing broad and innovative technology solutions for the data and artificial intelligence ('AI') era," with solutions that "range from client devices and peripherals to infrastructure solutions across servers, networking, and storage." It states that it designs, deploys and supports "secure, integrated solutions that extend from the edge to the core to the cloud," delivering "AI-optimized, software-defined, and cloud native infrastructure solutions across a broad partner ecosystem." The stated vision is "to become the most essential technology partner," executed by "leveraging our strengths to extend our leadership positions and capture new growth," anchored in a corporate purpose "to create technologies that drive human progress." ### Independent characterisation Dell is, at its economic core, a high-velocity systems integrator and distributor of other companies' silicon. It does not manufacture processors, GPUs, memory or flash; it buys them, engineers systems and racks around them, and monetises the assembly, integration, deployment, financing and multi-year support that surrounds them. This is a low-gross-margin, high-asset-turnover, negative-working-capital business model. In FY2026 consolidated gross margin was 20.0% and operating margin 7.2%, while asset turnover was approximately 1.25x and the current ratio 0.91 — Dell is funded in substantial part by its suppliers through $33.6bn of accounts payable at year end, rising to $49.7bn by 31 July 2026. Three characteristics distinguish the current business from the Dell of five years ago: **First, mix has inverted.** ISG overtook CSG as the larger segment in FY2026 ($60.8bn versus $51.0bn) and by Q2 FY2027 was more than twice CSG's size ($31.8bn versus $15.0bn). Within ISG, AI-optimised servers — a product category that did not exist as a separate disclosure line until Q4 FY2026 — generated $24.7bn in FY2026 and $32.5bn in the first half of FY2027 alone. **Second, the revenue model has bifurcated.** Product revenue grew 27% in FY2026 to $90.4bn while services revenue declined 4% to $23.1bn. The services decline is a reporting artefact of the wind-down of VMware resale and the disposal of Secureworks rather than a deterioration in attach rates; ISG and CSG services both grew. Nevertheless, the services line — historically the margin ballast of the business — is now only 20.4% of revenue, down from 25.3% in FY2025, and 12.5% of revenue in Q2 FY2027. Mix is moving away from Dell's most profitable revenue. **Third, consumption models have become material.** The Dell Payment Solutions portfolio offers utility, subscription, as-a-Service, lease, loan and immediate-pay structures. Dell Financial Services funded $11.9bn of originations in FY2026 and carried a $14.3bn global financing-receivables portfolio at year end. Financing receivables grew by $6.4bn in the first half of FY2027 alone, a direct consequence of large AI transactions carrying longer payment terms — this is why adjusted free cash flow ($11.3bn in H1 FY2027) diverges so sharply from unadjusted free cash flow ($4.1bn). ### Value chain position, customers and end markets Dell occupies the systems-integration and channel layer between component suppliers (NVIDIA, AMD, Intel, Broadcom, Micron, Samsung, SK Hynix, Western Digital, Seagate) and end customers. Manufacturing is a hybrid: Dell owns plants in the United States, Malaysia, China, Brazil, India, Poland and Ireland, and also uses contract manufacturers, principally in Asia, purchasing components and on-selling them to those manufacturers — an arrangement that generates large non-trade receivables and is disclosed as a credit-concentration risk. Customer segments are large global and national enterprises, government agencies and public institutions, educational institutions, healthcare organisations, small and medium businesses, and consumers. In FY2026 approximately 40% of net revenue was generated through channels other than the direct sales force — value-added resellers, systems integrators, distributors and retailers. Two customer cohorts now drive the growth narrative and both concentrate risk. The 10-K states plainly that AI solutions "have been purchased primarily by a small number of larger customers and cloud service providers," that large orders "may occur in some periods and not others," and that such transactions "may also involve larger amounts of credit or longer payment terms than have been typical for our business." Management has separately characterised the AI pipeline as a mix of "neocloud, sovereign and enterprise customers."
110 interactive charts drawn from the Known Good Die Testing Market dataset — market size, each segment breakdown, and every region and country by segment. Open one to read its full data table and download it.
Global Known Good Die Testing Market By Region
Global Known Good Die Testing Market By Test Type
Global Known Good Die Testing Market By Die / Device Type
Global Known Good Die Testing Market By Application
Global Known Good Die Testing Market By End User
Global Known Good Die Testing Market — North America by Country
Global Known Good Die Testing Market — North America by End User
Global Known Good Die Testing Market — North America by Test Type
Global Known Good Die Testing Market — North America by Application
Global Known Good Die Testing Market — North America by Die / Device Type
Global Known Good Die Testing Market — U.S. by End User
Global Known Good Die Testing Market — U.S. by Test Type
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