Introduction
Competition in TSV processing services is organized around two quite different industrial problems. At the high end, via-middle TSVs formed in silicon interposers and in the DRAM core dies of HBM stacks are tied to the packaging of AI accelerators and data-center processors, and a small group of foundries, OSATs and integrated device makers controls the qualified capacity. At the other end, via-last TSVs in CMOS image sensors, MEMS devices, RF filters and power components are produced by a broader population of OSATs and specialty fabs, where the process windows are mature and price competition is sharper. Both tiers run the same core sequence of deep reactive-ion etch, liner and barrier/seed deposition, copper fill, thinning and backside via reveal, yet they differ in wafer size, via geometry, customer concentration and the capital required to stay competitive.
Concentration at the high end follows from the way 2.5D interposer work is bought. TSMC's CoWoS flow treats interposer fabrication as one step in a sequence that also covers chiplet and HBM bonding, substrate assembly and test, so customers tend to award the entire flow to whoever can guarantee capacity. The shortages of 2024 pushed TSMC to secure additional floor space, including the agreement announced on 15 August 2024 to buy an idle Innolux display plant in Tainan for NT$17.14 billion, and pulled OSATs toward CoWoS-type work: ASE broke ground on its K28 plant in Kaohsiung on 9 October 2024 to add CoWoS packaging and testing capacity, and its subsidiary SPIL began construction of a CoWoS plant in Douliu, Yunlin County, on 11 August 2026. HBM via formation itself remains largely captive within the memory makers SK hynix, Samsung and Micron, which means merchant providers address the HBM opportunity mainly through stacking, interposer integration and test rather than through DRAM via etch and fill.
The lower tier is more fragmented because image sensor and MEMS customers can qualify several sources and because via-last processing from the wafer backside needs less specialized front-end infrastructure. Powertech Technology reported in May 2025 that its CIS-TSV packaging was in mass production, and ASE inaugurated Penang Plant 4 in Malaysia on 16 January 2024 with image sensor packaging among its focus areas. Alongside these OSATs, MEMS specialists such as Sweden-based Silex Microsystems and Teledyne's MEMS foundry operations sell TSV formation as part of complete sensor process flows. Competition here turns on cost per wafer, cycle time, hermetic sealing know-how and qualification for automotive and industrial grades rather than on reticle-scale integration.
Across both tiers, four levers decide contract awards. Capacity comes first in the AI segment, where lead times for interposer and stacking slots have shaped customer allocation. Yield is the second lever: a void in the copper fill, a crack during thinning or a failure at debonding scraps a wafer that may already carry known-good dies, so a documented yield record in temporary bonding, backside reveal and stacking carries commercial weight. Technology roadmaps form the third lever, as providers compete on interposer size, finer micro-bump and hybrid-bond pitches and alternatives to full silicon interposers. ASE's FOCoS-Bridge, qualified in May 2023 in a 70mm x 78mm package linking two ASICs and eight HBM devices through eight silicon bridges, illustrates how OSATs offer bridge-based options that compete with interposer TSV content, while UMC promotes wafer-to-wafer hybrid bonding of logic and DRAM wafers as a route to 3D stacking. The fourth lever is customer co-design, since via placement, keep-out zones, thermal paths and test access must be planned with the chip designer; Samsung used the inaugural Multi-Die Integration Alliance workshop in June 2024 to focus partners on 2.5D and 3D IC design.
The foundry and OSAT models compete and collaborate at the same time. Foundries such as TSMC, Samsung, Intel Foundry, UMC and GlobalFoundries form TSVs inside fabs that already operate etch, deposition and CMP tools, which favors via-middle integration in the wafer flow. OSATs such as ASE, Amkor, JCET, Tongfu Microelectronics and Powertech concentrate on thinning, reveal, bumping, stacking and test, and increasingly take on CoWoS-type assembly. The boundary is becoming contractual rather than fixed: under a memorandum of understanding signed on 4 October 2024, TSMC will contract turnkey advanced packaging and test services from Amkor's planned facility in Peoria, Arizona, for customers of its Phoenix fabs. Government incentives add a geographic dimension, with up to US$407 million in CHIPS direct funding awarded to Amkor in December 2024 and up to US$75 million in federal funding announced for GlobalFoundries' New York packaging center in January 2025 encouraging onshore TSV and assembly capacity outside Asia.
Key Player Positioning
The providers profiled in the competitive assessment fall into three groups. Leaders combine qualified high-volume capacity for 2.5D interposers or 3D stacking with a broad customer base for AI and HPC devices and multi-site operations. Challengers hold credible TSV process capability and are investing to move up the value chain, but either serve a narrower set of applications, depend more on a single region, or have yet to convert technology announcements into large external volumes. Niche players build TSVs into specialized device flows, mainly MEMS and sensors, and compete on process depth rather than scale. The grouping reflects technology position, capacity commitments and customer access, and it is qualitative; no share ranking is implied.
The Leaders group comprises TSMC, ASE Technology Holding including SPIL, Amkor Technology and Samsung Electronics. TSMC is the reference supplier for 2.5D integration through CoWoS and also offers InFO, and it is extending its packaging footprint beyond Taiwan: on 4 March 2025 it announced an additional US$100 billion investment in the United States, raising its planned U.S. total to US$165 billion and including two advanced packaging facilities alongside three new fabs and an R&D center. ASE combines its own TSV-based 2.5D and 3D IC processing, one of the six pillars of the VIPack platform introduced in June 2022, with the CoWoS-oriented expansion of SPIL, which inaugurated an advanced packaging plant at Tanzi Science Park on 16 January 2025 and later committed NT$100 billion to its Douliu site, with first-phase operations scheduled for 2028. Amkor offers the main merchant alternative in the United States through its Peoria campus, which it described in 2023 as set to become the largest outsourced advanced packaging facility in the country; in October 2025 it expanded the Arizona project to US$7 billion across two phases, named Apple and NVIDIA as customers the campus will support, and set production to begin in early 2028.
Samsung qualifies as a leader because it pairs internal HBM TSV stacking with foundry and Advanced Package operations, which it marketed from June 2024 as Samsung AI Solutions, a turnkey platform that it said shortens total turnaround time by 20% and that it plans to extend with a co-packaged optics option in 2027.
The Challengers are Intel Foundry, Powertech Technology, JCET Group, Tongfu Microelectronics, UMC and GlobalFoundries. Intel Foundry has some of the deepest 3D technology in the industry, including Foveros, Foveros Direct with hybrid-bond pitch under 5 µm, and EMIB-T, presented in April 2025, which adds TSVs to the EMIB bridge to improve power delivery for HBM4-class memory; its Intel 3-T node is optimized with TSVs for 3D designs. Its ASAT offering, expanded in February 2024 with FCBGA 2D+ alongside EMIB, Foveros and Foveros Direct, is still building an external customer base, and its new engagement with Amkor shows Intel combining internal lines with partner OSAT capacity. Powertech raised its 2024 capital budget to NT$15 billion with a major portion directed to 2.5D packaging and TSV technology for HBM, and it pursues HBM work with domestic and Japanese memory makers alongside panel-level fan-out.
JCET put its XDFOI chiplet platform, which covers 2D, 2.5D and 3D integration on an RDL stack interposer with 2 µm line and space, into high-volume manufacturing in January 2023 and acquired an 80% stake in SanDisk's Shanghai plant for US$667.8 million in September 2024; a CNY 10 billion wafer-level microsystem integration project in Jiangsu was also listed among major provincial projects for 2024. Tongfu Microelectronics, headquartered in Nantong and a joint-venture partner of AMD at sites in Suzhou and Penang, broke ground on a CNY 7.5 billion advanced packaging base covering multi-layer stacking in September 2024 and in January 2026 announced a RMB 4.4 billion private placement aimed largely at expanding capacity on existing process technologies, which keeps it closer to the volume end of the challenger group. UMC offers TSV-based interposers for CoWoS-S-style integration, with embedded deep trench capacitors in the interposer, and introduced a 3D IC solution for RFSOI on its 55nm platform in May 2024; as a foundry without its own assembly lines, it relies on OSAT partners to complete the packages built on its interposers.
GlobalFoundries demonstrated TSVs on 20nm wafers at Fab 8 in 2013 and is building a US$575 million New York Advanced Packaging and Photonics Center for wafer-to-wafer bonding and 3D and heterogeneous integration on its 12LP+ and 22FDX platforms, with volume ramp expected in the first half of 2028. The center also serves silicon photonics packaging and aerospace and defense work under GlobalFoundries' Trusted Foundry accreditation, which gives it a distinct position with U.S. government customers even though its TSV volumes are modest next to those of the leaders.
The Niche Players are Silex Microsystems and Teledyne's MEMS foundry operations. Silex, based in Järfälla near Stockholm and majority-owned since July 2015 by the Hong Kong holding company GAE, built its position on Sil-Via, a full-wafer-thickness via formed from a DRIE-etched silicon post surrounded by insulating material, and offers it within MEMS process flows. Teledyne's MEMS foundry, which spans Teledyne DALSA and Teledyne Micralyne with the latter also offering polysilicon and metal TSVs, provides via-first silicon TSVs with oxide-filled trench isolation on 150 mm and 200 mm wafers and via-last copper TSVs with a 5 µm critical dimension on thinned 200 mm wafers, used in its inertial sensor platform and in hermetically sealed oscillators, pressure sensors and image sensors. Neither competes for interposer or HBM work, but both serve automotive, industrial, medical and aerospace customers for whom TSV-enabled wafer-level packaging of sensors matters more than large-area integration.
Competitor Dashboard
The dashboard rates each provider on four criteria using a four-step scale of Low, Medium, High and Very High. Product Portfolio reflects the breadth of TSV-related services offered, from via etch and copper fill through thinning, backside reveal, temporary bonding, stacking and metrology, and whether these cover 2.5D interposers, HBM stacking, 3D logic and sensor applications. Regional Presence considers the number and spread of manufacturing sites that can deliver TSV or associated packaging steps, including committed new capacity in the United States and Asia. Strategic Alliances captures confirmed partnerships with foundries, OSATs, memory makers and chip designers that secure demand or extend capability. Industry Experience reflects the length and depth of the provider's track record in TSV and advanced packaging production.
The threat of new entrants is rated Low because TSV processing combines the capital intensity of a wafer fab with the know-how of advanced assembly. A credible entrant needs cleanroom space suitable for via etch, liner, barrier/seed deposition, copper fill and CMP, together with temporary bonding, thinning, reveal and stacking lines, inspection tools capable of finding voids and cracks in thinned wafers, and process engineers who understand how each step affects stress and yield in the next. Equipment for these steps, such as Bosch etch chambers, copper plating cells, high-precision grinders and thermo-compression or hybrid bonders, has long lead times and is often allocated first to existing high-volume customers. Even with tools installed, a new provider has no qualification history; buyers of AI accelerators and HBM will not move a production program to a site that has not passed extended reliability testing on their own products. In the via-middle scheme the barrier is higher still, because TSVs are inserted into the device wafer flow between transistor and interconnect formation, so only a company that already owns the logic or DRAM process can perform those steps. Accumulated patents on via fill chemistry, reveal processes and bonding methods, and the trust needed to handle unreleased chip designs, add further obstacles that capital alone does not overcome.
Entry is more feasible in specific niches and through state support. Via-last TSV for MEMS and image sensors uses lower aspect ratios and older tool sets, so specialty MEMS foundries and regional OSATs can offer it without leading-edge capacity, and back-end-like steps such as thinning, bumping and stacking on consigned wafers require less fab infrastructure than front-side via formation. Government programs aimed at domestic advanced packaging, such as the U.S. National Advanced Packaging Manufacturing Program, for which the Department of Commerce announced final awards in January 2025, lower the cost of research facilities and pilot lines for new participants. These programs mainly support development and prototyping, however, and turning a pilot line into a qualified high-volume source for an accelerator or memory customer takes several product cycles. The high-volume interposer and HBM segments therefore remain held by a few foundries, memory makers and the largest OSATs, each of which is expanding capacity in ways that raise the scale a newcomer would need to compete on cost and delivery. A newcomer would also face incumbents that bundle TSV steps with logic wafer supply or memory supply, so it must compete against a package of services rather than against a single process step.
The bargaining power of suppliers is rated High because the equipment and materials that define TSV performance come from a short list of companies, and switching between them requires requalification. Deep silicon etch is concentrated among Lam Research, Applied Materials, Tokyo Electron and SPTS Technologies, part of KLA. Temporary bonding and debonding tools come mainly from Tokyo Electron, EV Group and SUSS MicroTec; wafer thinning relies heavily on DISCO and Tokyo Seimitsu; and thermo-compression and hybrid bonding for HBM and 3D logic stacking is supplied by a small group that includes Hanmi Semiconductor, BESI, ASMPT and the Applied Materials and BESI partnership. Each of these suppliers holds process know-how embedded in its tools, and a service provider that has tuned a via-middle flow on one supplier's etch chamber or bonder cannot switch without reworking recipes and repeating customer qualification. When demand for interposers and HBM rises quickly, the same suppliers serve every competing provider at once, so delivery slots, field engineering support and early access to next-generation tools become points of negotiation in which suppliers hold the stronger position. Tool vendors also shape the technology roadmap itself, since the bump pitch, die thickness and bonding accuracy a provider can promise its customers depend on what the next tool generation can deliver.
Materials suppliers add to this power. Copper plating additive packages, CMP slurries for copper and barrier removal, temporary bonding adhesives and molded underfill compounds are formulated for specific via dimensions and stack structures, and providers usually qualify only one or two sources per material. The long-running exclusive arrangement between SK hynix and Namics for MR-MUF materials shows how a single material can become tied to a leading HBM process. Service providers offset supplier power partly through scale, since the largest foundries and memory makers are among the most important accounts for every tool vendor, and partly by encouraging competition among suppliers, as SK hynix did when it ordered thermo-compression bonders from ASMPT in November 2025 alongside its long-standing reliance on Hanmi. Applied Materials' April 2025 purchase of a 9% stake in BESI also shows equipment makers consolidating positions around hybrid bonding, which may concentrate supply further as that step moves from pilot use into volume production of HBM and stacked logic. Vendors able to supply etch, deposition, plating and CMP for the same TSV module can also offer integrated process support across several steps, which deepens the provider's dependence on them.
The bargaining power of buyers is rated Medium because buyers are few and large but capacity for leading-edge TSV processing has been scarce. Demand for 2.5D interposers and logic stacking is concentrated among a small number of GPU and custom ASIC designers, including NVIDIA, AMD, Broadcom and Marvell, and among hyperscale cloud operators that commission their own accelerators. Each of these buyers places large, multi-year volume commitments, negotiates directly with foundry and OSAT executives and can steer future programs between TSMC, Intel Foundry, Samsung Electronics and the larger OSATs. Hyperscalers are also becoming direct buyers of packaging capacity: in April 2026, WIRED reported that Intel was in talks with Google and Amazon to provide advanced packaging services for their custom AI processors. The willingness of buyers to fund second sources, as when AMD was reported in 2026 to be backing chip-on-wafer lines at ASE and SPIL, gives them a measure of influence over pricing and allocation that smaller chip companies do not have. Their design-enablement engagements also give buyers detailed insight into process steps and yields, which strengthens their position when volume agreements are renewed.
Several factors limit buyer power. Interposer and stacking capacity at the leading provider has repeatedly been fully booked, so buyers compete with one another for allocation rather than pressing providers on price, and long-term capacity reservations have become the usual way to secure supply. Switching costs are high, since a qualified package is tied to a specific interposer process, bump pitch, assembly flow and test program, and moving it to another provider adds months of engineering and reliability work at a time when product launch windows are short. In HBM, the largest buyers of memory stacks depend on three memory makers whose TSV lines are captive, which narrows choices further. Buyers of via-last TSV for image sensors and MEMS have more alternatives and more pricing power, because those processes are mature and offered by several OSATs and specialty foundries, and smartphone and consumer electronics customers negotiate hard on per-wafer cost. That combination of weak buyer power in the leading-edge segments and stronger buyer power in mature ones brings the overall rating to Medium.
The threat of substitutes is rated Medium because some TSV applications have practical alternatives while others do not. For 2.5D integration, the main substitutes are packages that reduce or avoid TSVs in large silicon areas: organic RDL interposers with embedded local silicon bridges, such as TSMC's CoWoS-L, Intel's EMIB embedded bridge, high-density fan-out packaging and, in development, glass core substrates that use through-glass vias, which fall outside this market. These options can lower cost and allow larger package sizes than a full silicon interposer, which is limited by lithography reticle stitching and wafer area, and they are being adopted for some of the largest AI accelerators. Many of them still contain TSVs in bridge dies or in logic base dies, as bridge designs that carry power through TSV-equipped bridge dies show, so substitution often reduces TSV area per package rather than removing TSVs altogether. For the service provider, the effect is a shift of value from interposer via formation toward bridge-die and base-die processing, which favors providers able to offer both. Monolithic integration on one very large die is a further theoretical alternative, but reticle size limits and the yield penalty of large dies restrict it for the processor sizes used in AI training systems.
In memory and 3D logic stacking, substitution risk is lower. HBM relies on TSVs through each DRAM die to deliver the bus width and bandwidth defined by the JEDEC HBM4 standard published in April 2025, and no alternative interconnect currently offers comparable bandwidth per footprint for accelerators. Hybrid bonding changes how dies are joined but still requires TSVs to carry signals and power through the stack, so it alters the mix of services, raising the value of thinning, surface preparation and inspection, rather than replacing TSV processing. In image sensors, wafer-level hybrid bonding between pixel and logic wafers can reduce the number of TSVs needed for some designs, and in MEMS and RF devices, wire bonding and through-mold vias remain alternatives for cost-sensitive products where TSVs are not required for performance. Chiplet designs that use standard organic substrates and die-to-die interfaces such as UCIe can also avoid silicon interposers for lower-bandwidth links, but they do not remove the need for TSVs where memory bandwidth is the limiting factor. These lower-value applications therefore carry more substitution exposure than the AI and HPC segments that account for most new TSV capacity.
Competitive rivalry is rated Medium because competition is intense on technology and capacity but moderated by capacity shortages and a concentrated provider base. TSMC, Samsung Electronics and Intel Foundry compete for the most valuable 2.5D and 3D integration programs, offering combined foundry and packaging services and making large capacity commitments, with Intel Foundry's push to sell packaging to external customers adding a third integrated provider to the leading-edge contest, while ASE, Amkor, JCET, Tongfu Microelectronics and Powertech Technology compete for back-end-like TSV steps, HBM-related assembly and via-last work. In HBM, SK hynix, Samsung Electronics and Micron Technology compete on stack height, thermal performance, yield and qualification timing with the largest accelerator customers, and those contests directly shape investment in captive TSV lines. Rivalry is strongest in the timing of new process generations, as providers race to qualify thinner dies, finer bump pitches and hybrid bonding ahead of competitors, because the first qualified source for a new accelerator or memory generation usually captures most of its early volume. Competition also runs through ecosystem programs, as providers offer design kits, partner alliances and reference flows that make their platforms easier for chip designers to adopt.
Price competition is limited in the leading-edge segments, where utilization has been high and buyers value capacity assurance and yield over unit price. It is more pronounced in mature applications such as via-last TSV for image sensors and MEMS, where several OSATs and specialty foundries offer comparable processes, and among Chinese providers, including JCET and Tongfu Microelectronics, that compete for domestic demand while U.S. export controls restrict their access to some advanced semiconductor equipment. High fixed costs and long equipment depreciation schedules encourage providers to keep lines full, which could intensify rivalry if AI accelerator or HBM demand slows and newly added interposer and stacking capacity sits idle. Under current capacity conditions, however, competition centers on technology roadmaps, yield learning and customer qualification rather than on price. Among memory makers the dynamic is sharper, because HBM qualification with one large accelerator customer can determine the utilization of a supplier's TSV lines for a full product generation.
Threat of New Entrants: Low; High capital needs, long tool lead times, scarce process expertise and lengthy customer qualification keep leading-edge interposer and HBM TSV work with incumbents.
Bargaining Power of Suppliers: High; Few qualified suppliers of deep etch, plating, bonding and thinning tools and specialty materials, with requalification required to switch.
Bargaining Power of Buyers: Medium; Concentrated GPU, ASIC and hyperscaler buyers negotiate hard, but tight capacity and high switching costs restrict their pricing influence.
Threat of Substitutes: Medium; RDL interposers, silicon bridges and fan-out reduce TSV area in 2.5D packages, while HBM and 3D stacking still require TSVs.
Competitive Rivalry: Medium; Foundries, memory makers and OSATs compete intensely on technology and qualification timing, while capacity scarcity restrains price competition.
