Introduction
The 3D IC stacking services market is moderately consolidated. The most advanced processes, including hybrid-bonded logic stacking and 12-high and 16-high HBM assembly, are performed by a small number of companies with the cleanroom capacity, process know-how and customer qualifications required for leading-edge AI and data-centre devices. Below this top tier, the market is fragmented across OSATs, specialty foundries and regional packaging houses that serve image sensors, NAND, RF modules, automotive devices and mature-node logic.
Competition takes three forms. Foundries compete by integrating 3D stacking into their wafer fabrication flow and offering customers a single route from front-end processing to stacked die, as TSMC does with its 3DFabric platform and Intel Foundry does with Foveros. Memory manufacturers compete on the yield, height and thermal performance of their own HBM stacks, which they assemble largely in-house using thermocompression bonding or mass reflow molded underfill and, for future generations, hybrid bonding. OSATs compete on capacity, cost, geographic diversity and the breadth of their assembly and test services, and increasingly partner with foundries and memory makers to take on parts of the flow that the leaders cannot absorb.
Customer relationships in this market are long and technical. Qualification of a new stacking process for an AI accelerator or a smartphone image sensor can take a year or more, and switching costs are high once a design has been taped out for a specific bonding interface. As a result, capacity announcements, long-term supply agreements and joint development programmes are the main competitive tools, rather than price alone.
Key Player Positioning
The leaders are TSMC, SK hynix, Samsung Electronics and ASE Technology Holding. TSMC leads foundry-based 3D integration through SoIC hybrid bonding combined with CoWoS and InFO packaging, and it supplies most of the AI accelerators that use stacked logic and HBM. SK hynix is the principal HBM supplier to the largest AI accelerator programmes and announced in September 2025 that HBM4 had completed development and was ready for mass production. Samsung Electronics combines memory production, a foundry and in-house advanced packaging, and in February 2026 began mass production and shipment of HBM4 built on its 1c DRAM process with a 4-nanometre foundry base die. ASE Technology Holding, including SPIL, is the largest OSAT and offers a broad portfolio covering fan-out, 2.5D and 3D assembly and test, with capacity additions in Taiwan in 2025 and 2026.
The challengers are Intel Foundry, Micron Technology, Amkor Technology and JCET Group. Intel has used Foveros 3D stacking in its own client and data-centre processors and is offering its advanced packaging to external foundry customers, although its external customer base for 3D stacking is still developing. Micron is the third HBM supplier, shipped HBM4 samples to key customers in June 2025 and is building an HBM packaging plant in Singapore, but its HBM share remains behind the two Korean producers. Amkor is the second-largest OSAT with a wide global footprint and is building an advanced packaging and test campus in Arizona, where it signed a 10-year agreement with TSMC in June 2026 to supply packaging and test services for shared customers. JCET is the largest OSAT in China, with strengths in wafer-level and memory packaging, but its access to the most advanced AI programmes is limited by trade restrictions.
The niche players are Powertech Technology, Tongfu Microelectronics, UMC and GlobalFoundries. Powertech is a memory-focused OSAT that is investing in fan-out panel-level packaging. Tongfu Microelectronics has a close relationship with AMD for processor packaging and is expanding memory, automotive and wafer-level packaging capacity in China. UMC offers wafer-to-wafer 3D IC solutions for edge AI through a partner ecosystem formed in 2023. GlobalFoundries is building an advanced packaging and photonics centre in New York aimed at secure and U.S.-based supply. Each of these companies has relevant capability, but in narrower device classes or regions than the leaders and challengers.
Competitor Dashboard
The ratings reflect the positioning described for each group. The leaders score Very High on at least two dimensions, reflecting their control of leading-edge stacking capacity and their role in the main AI and smartphone supply chains. The challengers score High on most dimensions, with Amkor's Very High regional presence reflecting its operations across Asia, Europe and the U.S. The niche players score Medium on product portfolio because their stacking services cover a narrower range of devices.
Porter's Five Forces framework is applied here to the provision of 3D stacking services, covering foundries, OSATs and IDMs or memory manufacturers that perform stacking either for external customers or as a distinct internal service. Each force is rated High, Medium or Low on the basis of structural conditions observed through 2025 and 2026.
Threat of New Entrants
The threat of new entrants is rated Low. Entry into 3D stacking services requires three assets that are difficult to acquire together: cleanroom capacity with front-end-grade contamination control, process know-how in fine-pitch bonding and thin-wafer handling, and qualified relationships with wafer suppliers and end customers. Hybrid bonding in particular demands planarisation, surface activation and alignment capabilities that have historically been developed inside wafer fabs rather than in packaging plants, so a conventional assembly house cannot move into the segment simply by buying bonders. Capital requirements are high and lumpy: a single advanced packaging site for AI-class products typically involves multi-year investment programmes, and equipment such as hybrid bonders and wafer-to-wafer bonders is supplied by only a handful of vendors with order backlogs.
Customer qualification adds a further barrier. An HBM stack or a logic-on-logic product is qualified as part of a specific accelerator or system, and the qualification cycle with a leading AI chip designer or a smartphone OEM can take one to two years. Once qualified, a supplier is rarely displaced within a product generation because requalification would delay the customer's own launch. Intellectual property also matters: the leading foundries and memory makers hold extensive patent portfolios in TSV formation, bonding interfaces and stack thermal management, and disputes between equipment suppliers over thermo-compression bonder patents in 2025 show how contested this area has become.
Entry is nonetheless not impossible, and the main sources of new capacity are state-supported. In China, packaging groups and memory makers have been expanding stacking capabilities with backing from national and provincial funds, partly in response to restrictions on access to foreign HBM. In India, approved assembly and test projects from Micron, Tata Electronics, CG Power with Renesas and Kaynes Semicon, among others, are building OSAT capability, although their initial focus is on conventional and memory packaging rather than fine-pitch 3D stacking. In the United States and Europe, public funding is supporting new sites from established players rather than true newcomers. Even where public money lowers the capital barrier, newcomers still have to recruit experienced process engineers, secure tool delivery slots behind established customers and persuade cautious buyers to qualify an unproven line, and each of these steps takes years rather than months. These developments add capacity at the edges of the market but do not change the core conclusion that the most technically demanding segments remain closed to new entrants for the foreseeable future.
Bargaining Power of Suppliers
The bargaining power of suppliers is rated High. Supplier power in this market arises from two directions. The first is equipment and materials. Hybrid bonding tools, wafer-to-wafer bonders, advanced CMP systems and high-resolution inspection tools are each supplied by a small number of vendors, and several of them have reported strong order books for advanced-packaging tools during 2025. When a single bonder vendor holds a dominant share of a tool category, the stacking provider has limited ability to negotiate price or delivery, and tool lead times directly determine when new capacity can come online. Materials such as non-conductive films, MR-MUF compounds, bonding dielectrics and temporary bonding adhesives are also concentrated among a small group of qualified suppliers, and switching a qualified material triggers costly customer requalification.
The second source of supplier power is unusual and specific to this market: the wafers being stacked often come from organisations that are themselves dominant players. HBM core dies can only be sourced from SK hynix, Samsung or Micron, and leading-edge logic wafers for chiplet stacking come overwhelmingly from TSMC, with Samsung Foundry and Intel Foundry as smaller alternatives. An OSAT that wishes to offer HBM stacking or SoIC-like logic stacking therefore depends on suppliers that also compete with it for the stacking step. Memory makers have kept HBM stacking in-house, and foundries have prioritised their own 3D platforms, which leaves OSATs with access mainly to overflow work or to formats the wafer owner chooses not to perform internally.
Some factors moderate this power. Equipment vendors depend on a small customer base as well, and large stacking providers co-develop tools with them, which creates mutual dependence. Leading foundries and memory makers have also begun qualifying multiple bonder suppliers for the same process, as seen in reports during 2025 of HBM producers placing thermo-compression bonder orders with more than one vendor. Large providers also hold a degree of countervailing power through scale: a leading foundry or memory maker can commit to multi-year tool purchases or co-fund development of a new bonder generation, terms that a smaller OSAT cannot offer. Even so, the structural concentration in tools, materials and wafers leaves suppliers with strong leverage across the forecast period.
Bargaining Power of Buyers
The bargaining power of buyers is rated Medium. The buyer base is concentrated: a small number of AI accelerator designers and hyperscale cloud operators account for a large part of demand for HBM and logic stacking, and a few smartphone OEMs dominate demand for stacked image sensors and fan-out stacked processors. Concentrated buyers placing very large orders normally hold strong negotiating power, and these customers use multi-sourcing where possible, for example qualifying HBM from more than one memory maker and splitting packaging work between a foundry and one or more OSATs.
During 2024 and 2025, however, the balance shifted toward providers because advanced stacking capacity, particularly for HBM and for foundry 3D and 2.5D integration, was scarce relative to AI demand. Buyers competed for allocation, signed longer-term supply agreements and in some cases prepaid or co-invested to secure capacity. In that environment, the ability of even the largest buyers to dictate price was limited. The power of buyers also differs by segment. In stacked image sensors and CMOS-bonded NAND, where the technology is mature and capacity is adequate, smartphone and storage customers apply steady price pressure and can shift share among suppliers between product generations. In automotive and industrial segments, buyers are smaller and their qualification requirements tie them to existing suppliers, which reduces their leverage.
Over the forecast period, buyer power is expected to rise gradually as new HBM, SoIC-type and OSAT capacity in Taiwan, Korea, the United States, Japan and Southeast Asia comes online and as standardised interfaces make designs somewhat more portable between providers. Custom HBM base dies and co-designed logic stacks will, however, deepen the technical lock-in between buyers and their chosen providers, which limits how far buyer power can increase. Buyer behaviour is also changing in ways that affect leverage. Hyperscale cloud operators that once bought finished accelerators are now designing their own chips with ASIC partners and engaging directly with memory makers and foundries on HBM configuration and stacking capacity, which gives them more information about cost structures and more influence over roadmaps. At the same time, the move to custom base dies for HBM4 means that each buyer's stack becomes more distinctive, which makes it harder for the buyer to switch suppliers mid-programme. The net result is a Medium rating, with higher pressure in mature formats and lower pressure in leading-edge AI stacking.
Threat of Substitutes
The threat of substitutes is rated Low. The main functional alternatives to vertical die stacking are monolithic integration on a single die, 2.5D integration on silicon interposers or bridges without vertical stacking, conventional multi-chip packages connected through organic substrates, and, in memory, non-stacked DRAM formats such as GDDR and LPDDR. Each of these substitutes is viable for some products, but none matches the bandwidth density and energy per bit that vertical stacking offers for the applications driving this market.
Monolithic scaling is constrained by reticle size limits, rising wafer cost per transistor at advanced nodes and lower yields for very large dies, which is precisely why chip designers have moved to disaggregated architectures. 2.5D integration is better described as a complement than a substitute: AI accelerators typically combine 2.5D interposers with 3D-stacked HBM and, increasingly, 3D-stacked logic or cache dies, so growth in 2.5D tends to pull 3D stacking demand with it. GDDR and LPDDR memory are used in inference cards, gaming graphics and edge devices where cost matters more than peak bandwidth, and they do compete with HBM at the lower end of the accelerator market, but they cannot provide the bandwidth required by large-model training systems. For image sensors and 3D NAND, wafer bonding has become the standard architecture at leading suppliers, and reverting to single-wafer designs would sacrifice pixel performance or array efficiency.
Longer-term technologies such as monolithic 3D integration, in which device layers are fabricated sequentially on one wafer, and optical interconnects between chips, including co-packaged optics, could eventually reduce the need for some forms of die stacking. These approaches remain in research or early deployment as of 2026, and co-packaged optics in particular tends to rely on stacking photonic and electronic dies, so it is as likely to create stacking demand as to displace it. Software and architectural approaches offer a partial substitute in some workloads. Model compression, quantisation and memory-efficient inference techniques can reduce the memory bandwidth needed per query, and some inference accelerators rely on large on-die SRAM rather than external stacked memory. These approaches change the mix of stacking demand, for example shifting some requirements from HBM towards SRAM-on-logic stacking, but they do not remove the underlying need for vertical integration. The threat of substitutes therefore remains Low through 2032.
Competitive Rivalry
Competitive rivalry is rated High. Rivalry is intense in every major segment, although it takes different forms. In HBM, SK hynix, Samsung and Micron compete on stack height, bandwidth, thermal performance and qualification timing with the leading AI accelerator vendors; market positions have shifted between product generations depending on which supplier first passed qualification, and the transition to HBM4 in 2025 and 2026 renewed that contest. In foundry-led logic stacking, TSMC, Samsung Foundry and Intel Foundry compete to attract chiplet-based designs to their integrated 3D platforms, using stacking capability as a lever to win wafer business at advanced nodes.
Among OSATs, ASE Technology Holding, Amkor Technology, JCET, Powertech Technology and Tongfu Microelectronics compete on cost, regional footprint, customer proximity and their ability to take on more advanced formats such as fan-out stacking, chip-on-wafer processes and, increasingly, hybrid bonding. Price competition is strongest in mature formats such as stacked memory modules for consumer devices and RF stacks, while competition in AI-related formats is based on capacity availability and yield rather than price. The rivalry is amplified by rapid technology cycles: the shift from micro-bumps to hybrid bonding, from 12-high to 16-high stacks and from DRAM-process base dies to foundry logic base dies forces repeated capital spending, and providers that fall one generation behind can lose a major customer for several years.
High fixed costs and the strategic importance of stacking to wafer business mean that providers are reluctant to cede share, and governments in several regions subsidise capacity, which adds further supply over the forecast period. At the same time, the structural growth of AI and data-centre demand has so far absorbed new capacity, which has kept rivalry focused on technology leadership and customer access rather than on destructive price cuts. Rivalry also extends across the boundaries between provider types. Foundries have moved into activities once performed by OSATs, memory makers are working with foundries on logic base dies, and leading OSATs are investing in hybrid bonding and wafer-level processes that bring them closer to front-end manufacturing. This blurring of roles means that each provider faces competitors from several directions at once, and partnerships, such as foundry-memory alliances for HBM4 and foundry-OSAT arrangements for overflow capacity, have become a competitive tool in their own right. Taken together, these conditions support a High rating for competitive rivalry.
Threat of New Entrants: Low; High capital needs, fine-pitch bonding know-how and long customer qualification cycles block entry.
Bargaining Power of Suppliers: High; Bonding tools, key materials, HBM DRAM wafers and leading-edge logic wafers come from very few suppliers.
Bargaining Power of Buyers: Medium; Buyers are concentrated, but scarce AI stacking capacity and deep co-design lock-in limit their leverage.
Threat of Substitutes: Low; Monolithic scaling, 2.5D-only designs and GDDR/LPDDR cannot match stacked bandwidth density for key uses.
Competitive Rivalry: High; Foundries, memory makers and OSATs race on stack height, bonding pitch and qualification timing.
