Introduction
The CoWoS-like advanced packaging services market is highly consolidated. A single pure-play foundry, TSMC, created the chip-on-wafer-on-substrate process family and still performs the large majority of interposer and bridge integration for merchant AI GPUs and hyperscaler accelerators, while a short list of OSATs and integrated device manufacturers competes for the remaining demand. Concentration follows from the nature of the work. Interposer fabrication uses wafer-fab processes such as lithography, through-silicon via etching and chemical-mechanical polishing, chip-on-wafer assembly requires fine-pitch micro-bump bonding of dies that are among the most expensive in the semiconductor industry, and qualification by a GPU vendor or cloud operator is a lengthy, multi-stage process. Few companies have the cleanroom space, process history and customer trust to run these flows at volume.
Competition takes place on capacity, yield, technology roadmap and supply-chain position rather than on price alone. Throughout 2024–2026 demand for CoWoS-type capacity exceeded supply, which allowed the leading provider to allocate capacity among customers and, according to October 2026 press reports, to consider raising prices. In this setting, the main competitive question for other providers has been how to win second-source and overflow work, either by taking specific process steps from the foundry or by offering an alternative platform. ASE Technology Holding and its subsidiary SPIL have expanded CoWoS-type lines in Taiwan and are moving towards full-process service; Amkor Technology is building the largest OSAT advanced packaging campus in the United States; Intel Foundry markets EMIB and EMIB-T as a lower-cost bridge alternative to large interposers; and Samsung Electronics offers a combined memory, foundry and packaging service.
The structure is also shaped by regional policy. Export controls limit the access of Chinese providers such as JCET Group and Tongfu Microelectronics to the most advanced AI devices, so their 2.5D activity is directed mainly at domestic chip designers and at server and networking products. Incentive programmes in the United States, Japan, India and Europe are drawing new capacity, including GlobalFoundries' interposer supply agreement with TSMC announced on 8 October 2026, but these projects reach volume only from 2027–2028 onward. Competitive intensity is therefore rising, yet the market remains anchored on a small number of Taiwanese and Korean production clusters.
Key Player Positioning
The leading companies can be grouped into leaders, challengers and niche players according to the breadth of their CoWoS-like platforms, their production scale, their customer relationships and their ability to supply complete, tested modules.
The leaders are TSMC and ASE Technology Holding. TSMC is the clear technology and volume leader. Its 3DFabric portfolio spans CoWoS-S, CoWoS-L and CoWoS-R, together with SoIC hybrid-bonded stacking and the SoW-X wafer-scale system announced in April 2025. On its third-quarter 2026 earnings call, management stated that five-reticle packaging was in mass production with strong yields and that nine- and fourteen-reticle solutions were in development. The company is adding capacity at Chiayi, where, according to Taiwanese government statements reported in July 2026, two advanced packaging facilities began mass production in June 2026 and a second phase broke ground in July 2026, and it began construction of its first Arizona packaging facility in 2026. ASE Technology Holding, including SPIL, is the largest OSAT and the most important partner for the chip-on-wafer and on-substrate steps that TSMC outsources. Its VIPack platform covers FOCoS, FOCoS-Bridge and FOCoS-Bridge with TSV, and in October 2026 it raised its 2026 guidance for leading-edge advanced packaging and test revenue to US$4 billion while lifting capital expenditure to US$11.5 billion. ASE's scale across Taiwan, Malaysia, China and Korea, its new K28 and Douliu plants, and its selection by AMD in May 2026 as a development partner for Elevated Fanout Bridge packaging place it firmly in the leadership group.
The challengers are Amkor Technology, Intel Foundry and Samsung Electronics. Amkor combines a broad 2.5D and high-density fan-out portfolio with the widest geographic footprint among OSATs, with sites in Korea, Taiwan, Vietnam, Portugal and Japan. Its partnerships with TSMC for CoWoS and InFO in Arizona (October 2024) and with Intel for EMIB assembly (April 2025), together with the US$7 billion Peoria campus announced in October 2025, make it the principal non-Asian source of these services from 2028. Intel Foundry has deep packaging experience from its own products and a differentiated bridge platform, including EMIB-T introduced in April 2025, but as of its October 2026 earnings call it had not yet named an external EMIB customer, which keeps it in the challenger group despite its technical capability. Samsung Electronics can supply logic, HBM and I-Cube packaging under one contract, began mass production of HBM4 with a 4 nm logic base die in February 2026, and committed KRW 56 trillion to HBM packaging facilities in July 2026; its turnkey CoWoS-like wins with external logic customers, such as the Preferred Networks order of July 2024, remain fewer than those of the leaders.
The niche players are JCET Group, Tongfu Microelectronics, Powertech Technology, UMC and GlobalFoundries. JCET is the largest OSAT in mainland China and offers 2.5D and chiplet integration through its XDFOI platform, with 2026 capital expenditure raised to RMB 17.31 billion in October 2026; its addressable market is constrained by export controls on leading AI devices. Tongfu Microelectronics serves AMD and Chinese HPC customers with chiplet and high-density packaging, and its 2026 private placement funds additional HPC packaging capacity. Powertech Technology is building a specialist position in panel-level RDL interposers, having agreed to buy an AUO plant in Hsinchu in November 2025 and formed a joint venture with Broadcom in Singapore in July 2026. UMC and GlobalFoundries participate as interposer suppliers rather than full-flow packaging providers: UMC has long supplied silicon interposer wafers to the ecosystem, and GlobalFoundries will begin volume supply of interposers for TSMC's CoWoS ecosystem from New York in the first half of 2028.
Competitor Dashboard
The dashboard rates each company on four dimensions. Product Portfolio reflects the breadth of silicon interposer, silicon bridge and RDL interposer platforms offered and the ability to deliver complete modules. Regional Presence reflects the spread of production and customer-support locations. Strategic Alliances reflects partnerships with chip designers, memory makers, foundries and governments. Industry Experience reflects the depth of the company's track record in high-volume, high-value advanced packaging. The ratings are consistent with the positioning of the leaders, challengers and niche players.
TSMC and ASE Technology Holding score highest across the dashboard, reflecting complete platform portfolios and long histories in interposer packaging. Amkor's very high regional presence reflects its multi-country footprint, while Intel Foundry and Samsung Electronics combine strong portfolios and experience with alliances that are still developing for external customers. The niche players score lower on portfolio because they either focus on one platform, as Powertech does with panel-level RDL, or supply a sub-process, as UMC and GlobalFoundries do with interposers.
Competitive conditions in CoWoS-like advanced packaging services are shaped by heavy capital requirements, a short list of qualified providers, concentrated upstream inputs and a small, powerful customer base. Demand for large interposer and bridge packages has exceeded qualified supply since 2023, which strengthens incumbent providers against both buyers and potential entrants, while scarcity of HBM, substrates and bonding tools gives certain suppliers temporary pricing influence. Each force is assessed from the standpoint of a provider of 2.5D integration services across silicon interposer, silicon bridge and RDL interposer platforms.
Threat of New Entrants: Low
Entry requires a combination of cleanroom space, front-end-grade tools and back-end assembly capability that few organisations can fund. ASE raised its 2026 capex in steps to US$11.5 billion by October 2026, with much of the equipment increase directed to leading-edge packaging; Amkor expanded its Peoria, Arizona campus plan to US$7 billion over two phases in October 2025; and JCET's board raised its 2026 capex from RMB 9.98 billion to RMB 17.31 billion in October 2026. Spending at this scale is undertaken by established firms with existing customer relationships, not by greenfield entrants, and each new site takes two to three years from groundbreaking to volume output. ASE alone was running 13 new fab construction projects and 8 expansion projects in parallel in July 2026, a programme that depends on existing land, utilities, engineering staff and supplier queues that a newcomer would have to assemble from the start. State-backed capital can ease the financial barrier in some regions, as when JCET committed RMB 4.038 billion in December 2025 for a 30% stake in a RMB 13.46 billion chip fund, but such funding flows mainly to incumbents rather than to new providers.
Process know-how forms a second barrier. TSV formation and reveal, sub-micron RDL, micro-bump joining at pitches of 45 µm or below and warpage control across packages above 100 mm per side depend on accumulated learning that is not transferable through equipment purchase alone. Even the market leader's main customer faced this problem: in August 2024 Nvidia changed the Blackwell GPU mask to improve production yield and moved its volume ramp to the fourth quarter of 2024.
Qualification cycles lengthen the timeline further. Intel introduced EMIB-T in April 2025, yet no named external AI customer was in EMIB or Foveros volume production as of June 2026, and its chief executive said only in October 2026 that a couple of customers would be ready to announce within two quarters. Powertech, already an experienced OSAT, scheduled customer validation of its panel-level line for the second half of 2026 and mass production for the first half of 2027. If firms with this depth of experience need multi-year paths to volume, an outside entrant faces a still higher hurdle. Customers also weigh delivery record heavily, because a failed package can strand several leading-edge logic dies and a full set of HBM stacks, so an unproven provider would struggle to win a production slot on a flagship accelerator even after completing qualification.
Bargaining Power of Suppliers: Medium
Several inputs are supplied by very few firms. HBM comes from SK hynix, Samsung and Micron, and SK hynix stated in October 2026 that its HBM and DRAM output is sold out through 2029, with long-term agreements covering more than half of its 2027–2028 capacity across 14 customers. Low-CTE glass cloth is even more concentrated: Nittobo held about 90% of global T-glass supply in March 2026, prices had risen 20–30%, and copper-clad laminate lead times had stretched from 8–10 weeks to more than 20. Counterpoint estimated in August 2026 that the ABF substrate supply gap would be about 10% in the second half of 2026 and widen to about 20% in 2027.
Bonding equipment adds a further pressure point. Thermo-compression bonders for HBM stacking and fine-pitch die attach come from a handful of vendors, and supplier relationships have been affected by litigation, with SK hynix reportedly placing HBM4 bonder orders with ASMPT in December 2025 during the Hanmi–Hanwha patent dispute. Such episodes show both the influence a single tool vendor can hold and the readiness of large buyers to qualify a second source. Inside the 2.5D flow itself, OSATs working on split CoW and oS programmes depend on the foundry that supplies the interposer modules, which gives TSMC supplier power over its outsourcing partners as well as competitive power over its rivals.
Countervailing measures keep supplier power at a medium level. Large providers and their customers sign multi-year supply agreements and qualify more than one vendor: by June 2026 Nvidia stated that all three HBM vendors were qualified for Rubin. Intel said in October 2026 that it had secured substantial substrate capacity for the next two years, and Nvidia was reported in March 2026 to have gone directly to Nittobo to secure glass cloth. Because packaging providers and their largest customers buy at a scale no other segment matches, suppliers gain price increases during shortages but cannot dictate allocation or terms. Supplier capacity is also expanding: Micron targeted 15,000 HBM4 wafers per month by the end of 2026, as reported in January 2026, and Samsung committed KRW 56 trillion in July 2026 to HBM packaging facilities in Onyang and Cheonan, measures that should gradually reduce the scarcity premium attached to memory.
Bargaining Power of Buyers: Medium
Demand is concentrated in a small number of buyers. Nvidia reportedly booked 800,000–850,000 CoWoS wafers for 2026, according to supply-chain reports from December 2025, and Broadcom, which designs custom accelerators for several hyperscalers, reported AI revenue of US$16.7 billion for its third fiscal quarter of 2026. A handful of hyperscalers stands behind most custom ASIC volume. Such buyers negotiate multi-year volume commitments, influence roadmap priorities and can redirect large programmes between platforms. Their scale is considerable: Nvidia reported Data Center revenue of US$89 billion for the quarter ended July 2026, and a buyer of this size can fund dedicated capacity, prepay for materials or co-invest in tooling, terms that smaller customers cannot obtain.
Buyers are also building alternatives. AMD named ASE and SPIL in May 2026 as development partners for its Elevated Fanout Bridge 2.5D packaging and announced that Powertech had qualified a panel-based version of the interconnect. Intel's pursuit of external EMIB-T customers gives hyperscalers a second platform to negotiate with, and the reported widening of TSMC's outsourcing to OSATs creates additional qualified capacity outside the turnkey flow. Hyperscalers that design their own accelerators can also change the mix of silicon interposer, silicon bridge and RDL interposer platforms between generations, which allows them to place programmes with the provider offering the best combination of availability and cost.
Scarce qualified capacity limits how far buyers can press these options. before customer demand could be met. TrendForce estimated in June 2026 that the CoWoS supply-demand gap was about 20% in mid-2026, narrowing to about 10% by year-end, and Nvidia's CFO said in August 2026 that supply would remain a bottleneck through FY2028. Switching providers also requires requalifying interposer design, substrate and test flow, so buyers secure volume and delivery commitments more readily than price concessions.
Threat of Substitutes: Low
The main substitute would be a larger monolithic die, but lithography caps a single die at about 858 mm². Accelerator designers already exceed this limit by large margins; Nvidia's Rubin places two near-reticle compute dies and two I/O dies on a single interposer, an arrangement that cannot be produced as one die. Memory bandwidth reinforces the dependency: the JEDEC HBM4 standard published in April 2025 specifies a 2,048-bit interface per stack and up to 2 TB/s, a wire count that only silicon interposers, embedded bridges or fine-line RDL can route between logic and memory at package scale.
Alternative integration routes do not yet replace 2.5D at volume. Standard fan-out packaging on organic RDL handles mobile and mid-range parts but lacks the line density and package area for multiple HBM stacks at accelerator scale. Wafer-scale designs such as Cerebras' WSE-3, announced in March 2024, rely on on-wafer SRAM rather than HBM and serve a specialist niche, while TSMC's SoW-X, announced in April 2025 for volume production in 2027, is itself built on CoWoS technology. Glass core substrates, which could change substrate economics, had no commercial product by August 2026, and most supplier timelines had slipped to 2027–2030. At the lower end of AI compute, GDDR-based accelerator cards, such as Nvidia's RTX PRO 6000 Blackwell announced in March 2025 with 96 GB of GDDR7, avoid an interposer altogether, but they offer far less memory bandwidth per package and do not compete for large-model training or high-throughput inference.
Hybrid bonding and 3D stacking act mainly as complements. TSMC's SoIC stacks are placed on CoWoS in so-called 3.5D packages, and TSMC's panel-level CoPoS, with pilot production expected in 2027 and mass production in the second half of 2028 according to August 2026 reports, extends the same chip-on-substrate architecture to larger formats. These developments shift demand between platforms within the market rather than drawing it away. Co-packaged optics behaves in a similar way: TrendForce noted in July 2026 that TSMC's COUPE-based optical engines compete with AI processors for the same 2.5D and 3D capacity, adding demand for the services instead of displacing them.
Competitive Rivalry: Medium
One pure-play foundry holds a clear technology and capacity lead. TSMC said on its Q3 2026 call in October 2026 that 5-reticle packaging was in mass production with strong yields, and its April 2026 roadmap targets a 9.5-reticle interposer in 2027, 14 reticles in 2028 and more than 14 reticles with up to 24 HBM5E stacks in 2029. Reported CoWoS capacity rose from about 35,000 wafers per month at the end of 2024 to about 80,000 at the end of 2025, with a target of about 130,000 at the end of 2026. Few rivals can match this combination of interposer scale, leading-edge logic and integrated test on a single customer engagement.
Competition for the remaining demand is active. ASE raised its 2026 guidance for leading-edge advanced packaging and test revenue to US$4 billion in October 2026 and expects that business to double in 2027; Amkor expected its 2.5D and high-density fan-out revenue to nearly triple in 2026, according to its February 2026 call; and Samsung won a turnkey 2 nm and I-Cube S order from Preferred Networks in July 2024. Chinese providers JCET and Tongfu Microelectronics compete mainly for domestic and regional demand shaped by US export controls on advanced computing chips first imposed in October 2022, with JCET reporting heterogeneous integration for co-packaged optics in October 2026 and Tongfu raising funds from January 2026 for chiplet packaging at 5 nm and 7 nm. Powertech's US$400 million fine-line RDL joint venture with Broadcom, approved in July 2026, adds a panel-level route to second-source competition. Product differentiation is also widening, as ASE's FOCoS-Bridge with TSV, unveiled in May 2025, demonstrated an 85×85 mm test vehicle with two ASICs and eight HBM3 stacks, giving OSATs a platform that competes directly with CoWoS-L for new designs.
Rivalry is held at a medium level because capacity shortage turns many competitors into partners. TSMC hands oS and increasingly CoW work to ASE, SPIL and Amkor, and Amkor also assembles EMIB packages for Intel under a partnership formed in April 2025. Providers therefore compete on capacity availability, cost per package and turnaround for second-source and overflow programmes rather than on price for the leading accelerator platforms.
Threat of New Entrants: Low; Multi-billion-dollar cleanroom and tool investment, TSV and fine-pitch process know-how, and long customer qualification cycles restrict entry to established foundries, IDMs and top-tier OSATs.
Bargaining Power of Suppliers: Medium; HBM, ABF substrates, low-CTE glass cloth and thermo-compression bonders come from a few suppliers, but long-term agreements and dual sourcing by large providers limit their leverage.
Bargaining Power of Buyers: Medium; A small group of GPU vendors and hyperscalers accounts for most demand and can negotiate volume terms, yet scarce qualified capacity limits their ability to switch providers.
Threat of Substitutes: Low; Monolithic dies are capped by the reticle limit and alternatives such as fan-out or wafer-scale integration cannot yet match the bandwidth and memory capacity of interposer packages at volume.
Competitive Rivalry: Medium; One pure-play foundry holds a clear lead, while OSATs, IDM foundries and Chinese providers compete for second-source, overflow and regional demand on capacity, cost and turnaround.
