Introduction
The panel-level packaging services market is moderately consolidated. A small number of companies in Taiwan and South Korea operate most of the panel lines that are in volume production and hold most of the qualified customer programmes, while a wider group of companies from the display, substrate and foundry industries is building capacity for large-format and glass-based packaging. The structure differs by segment. In Chip-First (Mold-First) Fan-Out PLP for small mobile and power packages, competition is between established outsourced assembly and test providers and display makers that have converted LCD lines, and price per unit is the main basis of competition. In RDL-First (Chip-Last) Fan-Out PLP and Panel-Level Interposer & Glass-Core Packaging for AI and data-centre devices, competition is between foundries and the largest outsourced assembly and test companies, and the basis of competition is wiring density, package size, yield and the ability to integrate logic dies and high-bandwidth memory for a few very large customers. In Panel-Level Embedded Die Packaging, substrate and printed circuit board specialists compete on reliability and thermal performance for automotive and industrial power modules.
Competition is shaped by three factors. The first is capital intensity: a large-format automated panel line requires lithography, plating, moulding, die placement, inspection and handling equipment configured for a specific panel size, and only companies with large advanced packaging budgets can fund several such lines. ASE stated in June 2026 that it and its subsidiary SPIL planned about 15 new fab and expansion projects during the year. The second is customer access: packaging programmes for AI accelerators are awarded by a small number of chip designers and system companies, and providers that already supply these customers with wafer-level packaging have an advantage in winning panel-level programmes. The third is technology licensing and partnerships: fan-out and adaptive patterning technology from Deca Technologies has been licensed to several manufacturers, and partnerships with equipment and materials suppliers are needed to solve warpage and fine-line patterning on large panels. New entrants, particularly display makers and glass-substrate companies, have used existing large-area manufacturing experience to enter the market, which has increased competition in the early stages of large-format adoption.
Key Player Positioning
Leaders are the companies with qualified panel-level production, broad process portfolios and established relationships with the largest chip customers. ASE Technology Holding, including SPIL, is positioned as a leader because it offers the widest range of advanced packaging services, has invested in 600 x 600 mm fan-out panel capacity, announced an automated 310 x 310 mm panel line for its FOCoS and FOCoS-Bridge platforms in May 2026, and supplies many of the chip designers that are moving to large packages. TSMC is a leader because of its position as the main packaging partner for AI accelerators through its wafer-based CoWoS platform; its chip-on-panel-on-substrate development, which its chairman described in July 2024 as being supported by a dedicated research group and pilot line, is expected to extend this position to panels. Samsung Electronics is a leader because it was among the first companies to use fan-out panel-level packaging in volume consumer products, including wearable processors such as the Exynos W1000 introduced in July 2024, and because it combines memory, logic foundry and packaging capabilities. Powertech Technology is a leader in volume panel fan-out on 510 x 515 mm panels, where it has worked with equipment suppliers on yield improvement, including the underfill process improvement reported with Nordson in June 2025.
Challengers are companies that bring strong capabilities from adjacent industries and are building panel-level capacity but do not yet have the breadth of customer programmes held by the leaders. Innolux is a challenger because it converted a Gen 3.5 LCD line into a fan-out panel line, offers very large glass panels and announced volume production of fan-out panel-level packaging in August 2025, but its customer base and process range are still developing. Intel is a challenger because it announced glass substrates for next-generation packaging in September 2023 and offers advanced packaging through its foundry business, although glass-core packages are not yet in volume. Samsung Electro-Mechanics is a challenger because it operates a glass-substrate pilot line in Sejong and signed a memorandum of understanding with Sumitomo Chemical and Dongwoo Fine-Chem in November 2025 for a glass-core joint venture. Rapidus is a challenger because it began pilot production of panel-based packaging in Chitose in 2025 and showed a prototype glass interposer cut from a 600 x 600 mm panel in December 2025, but it is a new company with limited production history.
Niche players are companies that focus on a specific technology, customer group or business model. nepes is a niche player with long experience in 600 mm panel fan-out for power management and mobile packages, but with a narrower customer and geographic footprint than the leaders. Deca Technologies is a niche player because it licenses its M-Series fan-out and Adaptive Patterning technologies rather than operating large-scale capacity itself; its agreements with SkyWater, announced in January 2024, and with IBM, announced in May 2025, give it a strong alliance position in North America. Absolics, a subsidiary of SKC, is a niche player focused on glass substrates, building a dedicated plant in Covington, Georgia, supported by a CHIPS Act award finalised in December 2024.
Competitor Dashboard
The dashboard rates each company on product portfolio, regional presence, strategic alliances and industry experience, using a four-level scale consistent with the positioning of leaders, challengers and niche players. Table 10.1 presents the competitor dashboard.
The five forces framework is applied here to the provision of panel-level packaging services, meaning the commercial activity of converting dies into finished packages on panel carriers for third parties or for in-house product lines. The assessment considers the period from 2025 to 2032 and reflects the market's early-commercial status, in which technology readiness, customer qualification and access to specialised tools matter as much as price. Each force is rated High, Medium or Low on the basis of its expected influence on the profitability and strategic freedom of established service providers.
Two features of the market shape the analysis. First, the customer base is concentrated in a few large chip and system companies, while the supply base for panel-capable tools and materials is also narrow, so service providers sit between two concentrated groups. Second, the boundary between panel-level and wafer-level packaging remains fluid for many package sizes, which keeps substitution pressure present even as demand for very large packages grows.
Threat of New Entrants: Medium
The threat of new entrants is rated Medium. Entry into panel-level packaging is costly and slow. A credible line requires panel-capable lithography, molding, plating, inspection and handling equipment, cleanroom space suited to large carriers, and a team experienced in warpage and yield engineering. Customer qualification adds further time, since chip companies typically require extended reliability data and pilot production before committing volume, and automotive customers add their own approval cycles. These requirements keep out small or undercapitalised entrants and favour companies that can absorb several years of investment before revenue reaches scale.
The rating is not Low, however, because the companies most likely to enter already possess much of the required capability. Display manufacturers own large-panel cleanrooms, panel handling automation and photolithography expertise, and several have redeployed older display lines toward fan-out panel packaging. Innolux in Taiwan is the most visible example, having converted former liquid crystal display capacity to panel-level packaging and begun shipments of fan-out panel products. Printed circuit board and substrate makers such as AT&S, Unimicron and Samsung Electro-Mechanics bring laminate processing, laser drilling and plating know-how that maps closely onto embedded die and glass-core processes. Foundries, too, are extending their packaging operations into panel formats, which brings new capacity into a market previously served mainly by OSATs.
Government programmes lower entry barriers in specific regions. The CHIPS for America National Advanced Packaging Manufacturing Program, for which the Department of Commerce announced final awards in January 2025, included support for Arizona State University to assess the commercial viability of 600 mm panel-level manufacturing, and for Absolics to develop a glass-core packaging ecosystem. Similar support in India, Japan, Korea and the European Union reduces the private capital required for a new line, although it does not remove the need for customer qualification.
Taken together, these factors mean that new capacity will continue to appear, but most of it will come from adjacent industries and from established semiconductor companies rather than from start-ups. Incumbent OSATs therefore face entry pressure from well-resourced companies with different cost structures, which limits how far pricing can rise even during periods of capacity tightness.
Entry barriers also differ by panel technology. Chip-first fan-out on smaller panels is within reach of several regional OSATs, whereas large panel interposers and glass-core packages require capabilities held by only a few companies, so new entrants tend to begin with simpler products.
Bargaining Power of Suppliers: High
The bargaining power of suppliers is rated High. Equipment for panel-level processing comes from a small set of vendors, and in several process steps only two or three companies offer tools that are proven in production on large panels. Panel lithography is the clearest case, where the need to pattern fine redistribution lines with accurate overlay across a warped panel limits the field to a handful of stepper and direct-imaging suppliers. Compression molding, panel plating and panel inspection show similar concentration. When a packaging provider plans a new line, lead times for these tools and the vendor's willingness to support process development can determine the start-up date.
Materials add to supplier power. Ajinomoto Build-up Film holds a leading position in build-up dielectrics for high-density substrates, and switching to an alternative dielectric requires requalification of the entire package. Mold compounds tuned for low warpage, photosensitive dielectrics for fine-line RDL, and specialty glass for carriers and cores are each supplied by a limited number of Japanese, American and European companies. Because these materials directly affect yield and reliability, packaging providers are reluctant to switch suppliers once a process is qualified, and suppliers are aware of this.
Known-good die represent a further dependency. Packaging providers do not control die supply, and for AI accelerators the foundry that makes the die often also offers packaging. This gives leading foundries a form of supplier power over independent OSATs, since the foundry can influence how much of the packaging work leaves its own facilities.
Some factors moderate supplier power. Equipment and material vendors need panel-level packaging to succeed in order to recover their own development costs, and many participate in joint development programmes, consortia and pilot lines where risk is shared. Large packaging providers with significant purchasing volumes, such as ASE, Amkor and the leading foundries, can negotiate co-development terms and priority allocation. Nonetheless, while panel formats remain only partly standardised and tool portfolios are still maturing, suppliers retain substantial influence over cost, schedule and technical direction.
Supplier influence is also visible in schedules. When several packaging providers expand panel capacity at the same time, demand for the same lithography, molding and inspection tools rises together, and vendors can allocate delivery slots to their largest or most strategic customers. Smaller providers and new entrants are most exposed to these allocation decisions.
Bargaining Power of Buyers: High
The bargaining power of buyers is rated High. Demand for advanced panel-level packaging is concentrated among a small number of large customers. AI accelerator programmes from a few fabless companies and hyperscale cloud operators, flagship smartphone platforms from a handful of device makers, and automotive power and control devices from a limited group of integrated device manufacturers account for most volume. Each of these buyers is large enough to fill or empty a panel line, and each runs formal multi-sourcing and cost-reduction programmes for its back-end supply chain.
Buyers also hold technical leverage. Chip companies define the package architecture, including die count, interposer size and interconnect pitch, and they can choose between panel-level, wafer-level and substrate-based solutions for many designs. For mid-range mobile and consumer products, a buyer that considers panel-level pricing too high can keep the product in wafer-level fan-out or a conventional flip-chip package. This option of staying with a mature format restrains price increases for panel-level services in high-volume, cost-sensitive applications.
The balance shifts in the AI and HPC segment during periods of capacity shortage. When demand for large interposer-based packages exceeds available capacity, buyers compete for allocation, accept capacity reservation fees or prepayments, and may co-fund equipment. In these circumstances the provider's position is stronger than the general rating suggests. Automotive customers likewise accept higher prices in return for long-term supply commitments and qualified processes, because the cost of requalifying a safety-relevant component is high.
Over the forecast period, buyer power is expected to remain High overall. As more capacity comes online from foundries, OSATs, display makers and substrate makers, buyers will gain more alternatives and will use them to negotiate on price and yield guarantees. Switching costs after qualification protect incumbents on running products, but each new product generation gives buyers a fresh opportunity to re-tender the work, and large buyers use these transitions to rebalance supply among providers.
Buyers increasingly extend their influence into technical specifications. Large chip companies now define preferred panel sizes, material sets and test flows for their suppliers, and in some cases they audit process data directly. Providers that cannot meet these common requirements risk exclusion from the approved supplier list for an entire product family.
Threat of Substitutes: Medium
The threat of substitutes is rated Medium. Panel-level packaging competes with several established alternatives that deliver similar functions. Wafer-level fan-out packaging, offered at high volume by TSMC through its InFO platform and by OSATs, is mature, well characterised and supported by depreciated equipment. For small and medium package bodies, the cost advantage of panels is narrower, and many customers prefer the lower technical risk of the wafer format. Silicon interposer-based 2.5D packaging, such as TSMC's CoWoS family, remains the reference solution for large AI accelerators, with extensive design support and a proven record in high-bandwidth memory integration.
Conventional flip-chip packaging on organic build-up substrates is a further substitute for many applications, particularly where fine-pitch redistribution is not required. Embedded bridge solutions, such as Intel's Embedded Multi-die Interconnect Bridge and local silicon bridge approaches offered by OSATs, provide high-density die-to-die connections without a full interposer and can be built on either wafer or substrate formats. For power and automotive devices, traditional leadframe and module packaging continues to meet many requirements at low cost.
The threat is not High because these substitutes face limits that panel-level formats address. Silicon interposers are constrained by the reticle and wafer area, and as AI packages grow beyond several reticle sizes, the share of a round wafer that can be used for rectangular interposers declines. Panels offer more usable area per carrier and a path to larger package bodies. Wafer-level fan-out faces the same geometric limits on large packages. Embedded die on panels offers shorter interconnects and better thermal and electrical performance than wire-bonded modules for power applications.
Substitution also works in both directions. Many of the substitutes are offered by the same companies that offer panel-level services, so providers can steer customers between formats according to capacity and cost. For the market, this means that the boundary between panel-level and wafer-level demand will remain flexible for medium-sized packages, while very large AI packages and certain embedded power modules are more firmly tied to panel formats.
For customers, the existence of substitutes is also a form of insurance. Many chip companies maintain a qualified wafer-level or substrate-based version of a design while a panel-level version ramps, which limits the volume that panel providers can capture until their yields and delivery records are established.
Competitive Rivalry: High
Competitive rivalry is rated High. The market includes foundries with integrated packaging (TSMC, Samsung and Intel), large OSATs (ASE Technology, Amkor Technology, Powertech Technology, JCET and Tongfu Microelectronics), and adjacent entrants from display, substrate and printed circuit board manufacturing (Innolux, AT&S, Unimicron and Samsung Electro-Mechanics among them). Each group pursues the same high-value customers, particularly in AI and HPC, and each has announced panel-level development lines, pilot lines or production capacity in 2024 and 2025.
Rivalry is driven mainly by technology and capacity rather than by price alone. Providers compete on the panel size they can process, the finest redistribution line and space they can achieve, the number of RDL layers, interposer area, warpage control and demonstrated yield. Announcements of larger panel formats and finer features serve as signals to customers about future capability. Because the first provider to qualify a package for a major AI or mobile platform tends to retain that business for the life of the product, rivalry is intense during the design-in phase.
Several structural features add to rivalry. Fixed costs are high, so providers need high utilisation to recover investment, which encourages aggressive pursuit of volume. Panel formats are not fully standardised, so providers that select different panel sizes compete partly by persuading customers and suppliers to align with their format. Government incentives in the United States, Europe, Japan, Korea, Taiwan, China and India support domestic capacity, which can lead to parallel investments in similar technology and a risk of regional overcapacity in specific formats.
Rivalry is moderated by rapid demand growth and by the technical difficulty of the work, which limits the number of providers able to serve the most demanding packages at any given time. In the near term, capacity for advanced AI-related panel packages is expected to remain tight, allowing leading providers to keep pricing discipline in that segment. In mobile, consumer and industrial packages, where several providers can offer comparable panel-level fan-out services, competition on cost is already stronger and is likely to intensify as new capacity comes online.
Threat of New Entrants: Medium; High capital and qualification barriers, offset by display, substrate and PCB makers redeploying existing large-panel capability and by public incentives.
Bargaining Power of Suppliers: High; Few proven panel lithography, molding and plating tool vendors; qualified dielectrics, mold compounds and glass are hard to switch.
Bargaining Power of Buyers: High; Demand concentrated in a few AI, smartphone and automotive programmes with multi-sourcing and mature wafer-level alternatives.
Threat of Substitutes: Medium; Wafer-level fan-out, silicon interposers and bridges are mature, but face area limits on very large packages.
Competitive Rivalry: High; Foundries, OSATs and adjacent entrants compete on panel size, RDL density and yield for a small set of design wins.
