Market Size (2025)
$8.95B
Vertical: SEMIBase Year: 2025
Market Size (2025)
$8.95B
Projected (2032)
$19.76B
CAGR (2022–2032)
7.7%
Key Players
11+
Market Overview
The global ABF packaging substrates market was valued at USD 8.950 Billion in 2025 and is projected to reach USD 19.760 Billion by 2032, expanding at a CAGR of 11.9% over 2026–2032. This corresponds to an absolute increase of USD 10.810 Billion between 2025 and 2032, which means the market is expected to more than double in value over the forecast horizon. ABF substrates are the organic build-up package substrates that sit between a flip-chip die and the printed circuit board in FC-BGA packages, and they are used in central processors, graphics processors, AI accelerators, network switch chips, automotive system-on-chips and game-console processors.
The historic period shows how strongly the market is tied to the electronics cycle. The market stood at USD 9.420 Billion in 2022, when substrate makers were still working through the capacity tightness that followed the pandemic-era surge in notebook and server demand. It fell to USD 7.160 Billion in 2023 as PC makers, consumer device brands and their chip suppliers cut inventories and substrate utilization dropped across the industry. Recovery began in 2024, when the market reached USD 7.980 Billion, and continued into 2025 as AI accelerator and server programs absorbed a growing share of high-layer, large-body capacity.
The forecast growth is driven less by unit volume than by substrate content per package. AI accelerators and high-performance computing packages use larger substrate bodies, more build-up layers and tighter line and space than notebook processors, so each package carries considerably more substrate value. The shift toward chiplet designs and 2.5D interposer packages adds to this effect, because multi-die packages need dense routing between dies and larger substrates to carry interposers and high-bandwidth memory stacks.
Key Findings
By layer count, 4–8 Layers was the largest segment in 2025 at USD 5.101 Billion, a 57.0% share, reflecting the large installed base of notebook, desktop and mainstream server processors built on these substrates. Above 16 Layers is the fastest-growing segment, with a CAGR of 21.0% over 2026–2032, rising from USD 1.298 Billion in 2025 to USD 5.138 Billion in 2032. It also records the largest absolute gain of the three layer-count segments, at USD 3.840 Billion, as AI accelerators and large switch chips move to substrates with very high layer counts.
By package architecture, Single-Die FC-BGA led the market in 2025 with USD 5.460 Billion and a 61.0% share. 2.5D Interposer-Based Packages is the fastest-growing architecture at a CAGR of 17.7%, increasing from USD 1.879 Billion in 2025 to USD 6.126 Billion in 2032, closely followed by Multi-Die / Chiplet FC-BGA at a CAGR of 17.0%. The two multi-die architectures together account for most of the forecast increase, which shows how far package design has moved away from the single monolithic die.
By application, PCs & Notebooks was the largest segment in 2025 at USD 2.775 Billion, a 31.0% share. AI Accelerators & HPC is the fastest-growing application, with a CAGR of 18.5%, and is projected to grow from USD 1.969 Billion in 2025 to USD 6.916 Billion in 2032. On the values in the dataset, AI Accelerators & HPC overtakes PCs & Notebooks in 2027, when it reaches USD 3.099 Billion against USD 3.071 Billion for PCs & Notebooks, and it becomes the largest application for the rest of the forecast period. Automotive Electronics is the second-fastest application at a CAGR of 15.9%.
By region, Asia Pacific is the leading region, with USD 7.303 Billion in 2025 and an 81.6% share, because substrate production, chip packaging and system assembly are concentrated there. North America is the fastest-growing region, with a CAGR of 14.8% over 2026–2032, followed by Middle East & Africa at 14.3%.
At country level, China is the largest individually reported country, with USD 1.534 Billion in 2025, equal to 17.1% of the global market, and it is projected to reach USD 3.877 Billion in 2032 at a CAGR of 14.0%. The Rest of Asia Pacific grouping, which includes Taiwan, South Korea and Southeast Asia, is larger as an aggregate. India is the fastest-growing country, with a CAGR of 23.7%, rising from USD 0.161 Billion in 2025 to USD 0.725 Billion in 2032 from a small base.
Segmentation Summary
The segmentation summary brings together the largest and the fastest-growing segment in each segmentation, so that the structure of current demand can be compared with the direction of future growth. In every segmentation the largest segment in 2025 is not the fastest-growing one. The segments that lead today are those tied to high-volume, mature products such as notebook processors and single-die packages, while the fastest-growing segments are tied to AI and data center silicon, multi-die architectures and very high layer counts.
The pattern in the table matters for capacity planning. Substrate lines built for four to eight layer notebook substrates cannot simply be redirected to the largest AI accelerator substrates, because the latter need larger panels handling, more lamination cycles, finer patterning and stricter warpage control. Suppliers that already run high-layer, large-body lines are therefore better placed to capture the fastest-growing segments, while suppliers concentrated on mainstream products face slower growth and more price competition.
Regional and Country Highlights
Asia Pacific is projected to grow from USD 7.303 Billion in 2025 to USD 15.759 Billion in 2032 at a CAGR of 11.5%. Within the region, Rest of Asia Pacific, which covers Taiwan, South Korea and Southeast Asia, held USD 4.791 Billion in 2025 and is projected to reach USD 9.613 Billion in 2032. China follows with USD 1.534 Billion in 2025 and a CAGR of 14.0%, supported by domestic AI chip programs and the expansion of local substrate makers. Japan held USD 0.818 Billion in 2025 and is projected to grow at a CAGR of 9.4%, while India, from a much smaller base of USD 0.161 Billion, is the fastest-growing country in the region at 23.7%.
North America grows from USD 0.931 Billion in 2025 to USD 2.450 Billion in 2032. The U.S. accounts for most of the regional market, with USD 0.820 Billion in 2025 rising to USD 2.144 Billion in 2032 at a CAGR of 14.6%, reflecting the concentration of AI accelerator and hyperscale data center demand. Mexico is the fastest-growing country in North America at a CAGR of 17.9%, as AI server and electronics assembly for the U.S. market expands there, while Canada grows at 13.8%.
Europe is projected to rise from USD 0.474 Billion in 2025 to USD 0.968 Billion in 2032 at a CAGR of 10.7%. Germany is the largest individually reported European country at USD 0.136 Billion in 2025, while Spain is the fastest-growing at 12.2%. European demand is weighted toward automotive, industrial and telecommunications electronics, which explains its slower growth relative to regions with larger AI accelerator programs.
Latin America is expected to increase from USD 0.134 Billion in 2025 to USD 0.306 Billion in 2032 at a CAGR of 12.5%, with Brazil the largest country at USD 0.061 Billion in 2025 and the fastest-growing at 13.0%. Middle East & Africa grows from USD 0.107 Billion to USD 0.277 Billion at a CAGR of 14.3%; Saudi Arabia is its fastest-growing country at 18.6%, followed by the UAE at 17.8%, as both countries build large AI data center campuses.
Competitive Landscape Summary
Supply of high-end ABF substrates is concentrated among a small group of Japanese, Taiwanese, South Korean and Austrian producers, and the market behaves as a consolidated industry at the top end and a more contested one in mainstream layer counts. Ibiden, Unimicron Technology, Shinko Electric Industries and AT&S form the leading group, based on their qualification on flagship server, AI accelerator and client processor programs and their ability to produce large-body, high-layer substrates at acceptable yield. Samsung Electro-Mechanics, Nan Ya PCB, Kinsus Interconnect Technology and TOPPAN are established challengers with broad FC-BGA portfolios and growing exposure to AI and networking programs, while LG Innotek, Daeduck Electronics, Zhen Ding Technology and Shennan Circuits hold narrower positions or are still building their ABF capability.
Competition rests on qualification rather than price alone. A substrate maker must co-develop designs with chip companies years before volume production, secure ABF film and low thermal expansion glass cloth, and hold yield on very large panels with many build-up layers. Between 2024 and 2026 the dominant pattern has been capacity expansion underwritten by customers. AT&S started high-volume production at Kulim, Malaysia, in May 2025 for AMD data center processors and announced a further Kulim expansion in June 2026. Ibiden opened its Ono plant in October 2025 for AI server substrates and approved a three-year investment program in February 2026. TOPPAN's joint venture with Broadcom opened an FC-BGA plant in Singapore in September 2026, and Samsung Electro-Mechanics announced a large FC-BGA investment for AI servers in South Korea and Vietnam in the same month.
Ownership and technology positioning are also changing. Shinko was taken private by a consortium led by JIC Capital, with Dai Nippon Printing and Mitsui Chemicals, after a tender offer completed in March 2025. Glass core substrates have become the main next-generation contest, with Samsung Electro-Mechanics, Shinko, LG Innotek and AT&S among the companies developing or showing glass core products. Mainland Chinese suppliers, led by Shennan Circuits, are moving from lower-layer products toward higher layer counts with support from domestic chip designers that want local supply.
Challenges and Opportunities
The main challenge for the industry is the cost and risk of building capacity for the most demanding substrates. Each additional build-up layer adds lamination, drilling, plating and inspection steps, and yield losses compound across layers, so a large AI accelerator substrate can carry a much higher scrap cost than a notebook substrate. New lines take years to plan, equip and qualify, which exposes suppliers to the risk of building capacity just as a demand cycle turns, as happened after 2022 when several expansion plans were slowed or deferred.
Material supply is a second constraint. ABF build-up film is supplied by Ajinomoto Fine-Techno, and low thermal expansion glass cloth for substrate cores comes from a small number of Japanese producers, led by Nittobo. Tightness in these inputs can limit how quickly substrate makers convert capacity to high-end products, and qualifying alternative materials requires long reliability testing with chip customers.
Demand in the PC and consumer segments also remains cyclical, and the arrival of new mainland Chinese suppliers targeting mainstream layer counts adds price pressure in the four to eight layer range, where competition is broadest.
The opportunities lie in the same technology shifts that create the challenges. Glass core substrates, which pair a glass core with build-up layers, are being developed by several substrate makers and chip companies for the largest packages after the middle of the decade. Hyperscaler custom AI chips and co-packaged optics for network switches create new large-body substrate programs and new qualification slots for suppliers beyond the established leaders. Government programs in the U.S., Japan, India, Europe and Southeast Asia are supporting new packaging and substrate capacity, which opens room for suppliers that can localize production near customers.
Future Outlook
Over 2026–2032 the market is expected to shift its center of gravity from client computing to data center computing. AI Accelerators & HPC is projected to become the largest application during the forecast period, and the high-layer and multi-die segments are expected to account for most of the absolute growth. This shift raises the average value of each substrate, increases the importance of yield and engineering capability, and favors suppliers that can co-develop substrates with chip designers years before volume production.
The 4–8 Layers, Single-Die FC-BGA and PCs & Notebooks segments will remain large in absolute terms through 2032, supported by notebook replacement cycles, AI-capable client processors and steady demand from mainstream servers and consumer devices. Their growth is expected to be slower, and their share of supplier capacity is expected to decline as lines are converted to higher-value products.
Regionally, production will remain concentrated in Asia Pacific, but new capacity in Southeast Asia, Japan and, over time, North America and India will make the supply base less dependent on a few locations. The pace at which glass core substrates, panel-level processing and embedded power delivery move from development into production will shape the later years of the forecast, as these technologies determine how large and how complex the next generation of AI packages can become.
The ABF Packaging Substrates Market market is projected to grow at a CAGR of 7.7% from 2022 to 2032.
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View Subscription PlansDefinition
ABF packaging substrates are organic, multilayer integrated circuit package substrates in which the insulating layers between copper wiring levels are formed from Ajinomoto Build-up Film, an epoxy-based dielectric film supplied by Ajinomoto Fine-Techno. The substrate sits between a flip-chip semiconductor die, or a group of dies, and the printed circuit board of the end system. Its function is to redistribute the very fine array of die connections into the much coarser array of solder balls that a motherboard or line card can accept, while delivering stable power to the silicon, carrying high-speed signals with controlled impedance and providing a mechanically stable platform during assembly and field operation. In the industry, ABF substrates are most closely associated with flip-chip ball grid array packaging, and they are the standard carrier for central processing units, graphics processors, AI accelerators, server processors, network switch ASICs, field-programmable gate arrays, high-end automotive system-on-chip devices and game-console processors.
A typical ABF substrate is built symmetrically around a core. The core is a rigid laminate of glass-fiber cloth impregnated with resin and clad with copper on both faces. For large and thin packages, makers increasingly specify low-thermal-expansion glass cloth, often referred to as T-glass, supplied by companies such as Nittobo, because the core sets much of the coefficient of thermal expansion and stiffness of the finished part. Plated through holes are mechanically or laser drilled through the core and metallized with copper, so that wiring on the top half of the substrate can connect electrically to wiring on the bottom half. The through holes are then filled with resin or paste and planarized before build-up begins.
The build-up stage gives the substrate its name. Sheets of ABF are vacuum laminated onto both sides of the core and cured. Microvias are formed in each dielectric layer by laser drilling, typically with carbon dioxide or ultraviolet lasers, and the via holes are desmeared to remove resin residue. Copper wiring is then produced by the semi-additive process: a thin seed layer of electroless copper is deposited across the dielectric surface, a photoresist pattern is imaged on it, copper is electroplated only in the open areas to form traces and fill the vias, and the resist and exposed seed copper are stripped and etched away. Because copper is added only where it is needed rather than etched from a thick foil, the semi-additive process can produce much finer line and space dimensions than the subtractive etching used for conventional circuit boards, and the smooth, adhesion-promoting surface of ABF after desmear treatment is a central reason the film became the industry reference for this process.
The film itself is a thin, filler-loaded epoxy composite engineered for low thermal expansion, low dielectric loss and good laser drillability, and successive grades have reduced film thickness and surface roughness to support finer wiring and faster signals. The lamination, drilling and plating sequence is repeated for each wiring level, so a finished substrate commonly carries an equal number of build-up layers on each side of the core. Total layer counts range from four to eight layers for mainstream client processors to well beyond sixteen layers for the largest data center and AI packages.
The two faces of the substrate serve different purposes. The die side carries a dense array of pads that receive the controlled-collapse chip connection solder bumps or the copper-pillar micro-bumps of the die, or, in an interposer package, the bumps of the interposer. These pads sit at the bump pitch of the silicon, which is far finer than anything a board can use. The opposite face carries ball grid array lands at board pitch, to which solder balls are attached for mounting on the motherboard. Between these two faces, the build-up layers progressively fan out the connections, with the finest lines on the layers closest to the die and coarser routing toward the board side. Dedicated layers and copper planes are allocated to power and ground, which lowers the impedance of the power delivery network and limits voltage droop when a processor switches large currents. Signal layers are arranged as striplines or microstrips with reference planes to control impedance and crosstalk for high-speed interfaces such as memory buses, PCI Express and SerDes links. Land-side and die-side capacitors may be mounted on the substrate, and some designs embed passive components within the build-up stack.
The role of the substrate expands when a package contains more than one die. In multi-die and chiplet designs, the substrate must route die-to-die links between compute, input-output and cache chiplets in addition to fanning out to the board, which raises the number of fine-line layers and the share of the substrate area that must meet tight line and space rules. Some architectures embed small silicon bridges in a cavity within the build-up layers to provide very short, dense connections between adjacent dies, so the substrate maker must hold tight registration and planarity around the embedded component. When the dies sit on an interposer, the substrate supports a much larger footprint, carries the full power demand of the logic dies and memory stacks, and must remain flat across a body size far larger than that of a conventional processor package. These requirements tie the value of an ABF substrate closely to its layer count, body size, line density and yield rather than to the number of units shipped.
The outer surfaces are coated with a solder resist layer that defines the openings over the bond pads and protects the outer copper. A surface finish is then applied to the exposed pads to preserve solderability and support reliable joints; common finishes include electroless nickel with immersion gold, electroless nickel with electroless palladium and immersion gold, and organic solderability preservatives, with pre-solder or micro-ball placement on the die-side pads in many flows. After electrical testing and inspection, substrates are shipped as singulated units or strips to outsourced semiconductor assembly and test providers, integrated device manufacturers or foundry packaging lines, where the die is attached, underfilled, lidded or fitted with a stiffener, and balled. Flatness through these reflow steps is a defining quality attribute, since warpage of a large substrate can cause open or bridged joints at either the die side or the board side, and it is one of the main yield constraints as body sizes grow.
ABF substrates differ from adjacent interconnect technologies in material, process and application. BT substrates use bismaleimide triazine resin laminates and are predominantly made by modified semi-additive or subtractive processes. They are well suited to memory packages, mobile application processors and chip-scale packages, including flip-chip chip-scale packages, where body sizes are small and layer counts are modest, but they do not usually reach the line density, layer count and large-body flatness required by high-performance processors. Silicon interposers are thin slices of silicon carrying through-silicon vias and very fine back-end-of-line wiring made in a wafer fab; they connect logic dies to high-bandwidth memory stacks at extremely fine pitch, but they are themselves mounted on an ABF substrate, which then connects the whole assembly to the board. Redistribution-layer and fan-out wafer-level or panel-level packaging builds thin polymer and copper wiring directly on a reconstituted wafer or panel of dies, eliminating or replacing part of the substrate in smaller packages; in the largest AI packages, organic redistribution interposers still sit on an ABF substrate. Glass core substrates replace the glass-fiber-reinforced organic core with a solid glass panel, offering better dimensional stability, flatness and through-glass via density for very large packages; they are an emerging next-generation core technology, and build-up layers on glass cores continue to use ABF-type dielectrics.
For the purpose of this study, the ABF packaging substrates market includes all organic build-up package substrates that use ABF dielectric and are sold for use in flip-chip ball grid array packages. This covers substrates for single-die FC-BGA packages, in which one monolithic processor or ASIC die is mounted on the substrate; substrates for multi-die and chiplet FC-BGA packages, in which several logic, input-output or cache dies are placed side by side and interconnected through the substrate wiring or through embedded bridges; and substrates that carry 2.5D interposer-based packages, such as GPU and custom AI accelerator assemblies built on TSMC CoWoS-S, CoWoS-L and CoWoS-R platforms or comparable interposer architectures from other foundries and outsourced assembly providers. All layer counts are included, from four to eight layers through the highest-layer-count server and accelerator designs, as are all body sizes, core types and surface finishes, and ABF substrates using glass cores once they enter commercial supply. Substrates are included irrespective of whether the end customer is a fabless chip designer, an integrated device manufacturer, a foundry, an outsourced assembly provider or a hyperscale cloud company designing its own silicon.
Several adjacent products are excluded. BT-based substrates and FC-CSP substrates for memory devices, mobile application processors, radio-frequency modules and similar small-body packages fall outside the product scope, as do wire-bond substrates and lead frames. Silicon interposers, organic redistribution interposers and silicon bridges are excluded as standalone items; only the ABF substrate that carries them is counted. Printed circuit boards, motherboards, server boards and accelerator baseboards on which finished packages are mounted are excluded, as is ABF film itself when sold as a raw material to substrate makers. Packaging and assembly services, test services, dies, lids, stiffeners and other bill-of-materials items in the finished package are likewise outside the scope. The value counted is that of the ABF substrate as sold by the substrate maker to its customer.
Scope of the Study
The study covers the global market for ABF packaging substrates, defined as organic build-up integrated circuit package substrates that use Ajinomoto Build-up Film dielectric and are used in flip-chip ball grid array packages. Market value is measured as the value of ABF substrates sold, that is, the revenue realized by substrate makers on shipments of finished ABF substrates to chip designers, integrated device manufacturers, foundries and outsourced semiconductor assembly and test providers. Package assembly value, die value and the value of the boards on which packages are mounted are not included. All values are expressed in USD Billion.
The timeline of the study is divided into three periods. The historic period covers 2022 to 2024 and captures the high demand of 2022, the inventory correction across PCs and consumer devices that followed, and the recovery that began in 2024. The base year is 2025, the most recent full year for which market values are estimated. The forecast period runs from 2026 to 2032, and compound annual growth rates are calculated for the period 2026 to 2032.
The market is segmented by layer count into three categories: 4–8 Layers, 8–16 Layers and Above 16 Layers. The 4–8 Layers category corresponds largely to client processors and mainstream consumer devices, while the 8–16 Layers category covers mid-range and high-end processors, networking ASICs and many automotive and server parts. The Above 16 Layers category captures the highest-complexity substrates used for large-body server CPUs, AI accelerators and high-performance computing packages, where routing density, power delivery and signal integrity requirements are greatest. Layer count refers to the total number of copper wiring layers in the finished substrate, including the copper layers on the core, and each substrate is assigned to a single layer count category according to its design.
The market is segmented by package architecture into Single-Die FC-BGA, Multi-Die / Chiplet FC-BGA and 2.5D Interposer-Based Packages. Single-Die FC-BGA covers substrates that carry one monolithic die. Multi-Die / Chiplet FC-BGA covers substrates on which several dies are placed and interconnected through the substrate or through embedded bridges, without a full silicon or organic interposer. 2.5D Interposer-Based Packages covers ABF substrates that carry an interposer assembly, including logic dies and high-bandwidth memory stacks, with the substrate counted and the interposer excluded. Each substrate is classified by the architecture of the package it carries, so that a chiplet processor mounted directly on the substrate and a chiplet assembly mounted on an interposer fall into different categories even when they serve the same application.
The market is segmented by application into PCs & Notebooks, Servers & Data Center CPUs, AI Accelerators & HPC, Networking & Communications, Automotive Electronics and Gaming Consoles & Consumer Devices. PCs & Notebooks includes desktop and notebook CPUs, client GPUs and chipsets. Servers & Data Center CPUs includes general-purpose server processors, including Arm-based processors from cloud operators. AI Accelerators & HPC includes data center GPUs, custom AI ASICs and supercomputing processors. Networking & Communications includes switch, router and network interface ASICs, FPGAs and telecom infrastructure processors. Automotive Electronics includes advanced driver-assistance, cockpit and central compute system-on-chip devices. Gaming Consoles & Consumer Devices includes console processors and other high-performance consumer silicon in FC-BGA packages.
The geographic scope covers five regions and their constituent countries. North America comprises the U.S., Canada and Mexico. Europe comprises Germany, the U.K., France, Italy, Spain and Rest of Europe. Asia Pacific comprises China, India, Japan and Rest of Asia Pacific. Latin America comprises Brazil, Argentina and Rest of Latin America. Middle East & Africa comprises the UAE, Saudi Arabia, South Africa and Rest of MEA. Taiwan and South Korea, which host major substrate makers and packaging operations, are included within Rest of Asia Pacific. Regional values are allocated by where ABF substrates are consumed, reflecting the location of the chip designers, system builders and packaging operations that procure substrates.
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View Subscription PlansOverview of the Research Process
The study of the global ABF packaging substrates market followed a structured research process that combined secondary research, primary research with participants across the substrate value chain, quantitative market modeling and a multi-stage validation of results. The process was designed around the specific economics of ABF substrates, in which value depends less on the number of packages shipped than on the layer count, body size, line and space capability and yield of each substrate, and in which a small number of high-value processor and accelerator programs can shift the market in a single year. The research also had to account for the long qualification cycles between substrate makers and their customers, which mean that capacity decisions taken several years in advance shape the supply available in any given year.
The work began with the definition of the product scope and segmentation, separating ABF substrates for flip-chip ball grid array packages from BT and FC-CSP substrates, silicon interposers, printed circuit boards and ABF film itself. Secondary research was then used to build an initial understanding of supply capacity, supplier revenues, customer programs and technology roadmaps. This was followed by primary interviews with substrate makers, material and equipment suppliers, chip designers, packaging providers and system builders, which tested the secondary findings and filled gaps in segment-level information.
Market sizing combined a bottom-up model, built from processor and accelerator shipments and the substrate content of each package, with a top-down model based on the substrate revenues of the leading suppliers. The two results were reconciled through data triangulation. The forecast was developed from driver models and scenario analysis, and the final estimates for each segment, region and country were reviewed for internal consistency before publication.
Secondary Research
Secondary research formed the foundation of the study and drew on sources that cover the semiconductor packaging and printed circuit industries in detail. Industry associations provided context on semiconductor demand, packaging capacity and substrate production. These included SEMI, which tracks semiconductor equipment, materials and packaging activity; IPC, which develops standards and industry studies for electronics manufacturing; JEDEC, whose package outline and reliability standards shape substrate design rules; the Semiconductor Industry Association and World Semiconductor Trade Statistics, which provide data on semiconductor sales by product category; and the national printed circuit associations, namely the Taiwan Printed Circuit Association, the Japan Electronics Packaging and Circuits Association and the Korea Printed Circuit Association, whose publications describe the output and investment plans of IC substrate makers in the principal producing economies.
Company disclosures were a central source because the ABF substrate supply base is concentrated and largely listed. Annual reports, quarterly results, investor presentations and earnings call materials of substrate makers such as Ibiden, Unimicron Technology, Shinko Electric Industries, AT&S, Samsung Electro-Mechanics, LG Innotek and TOPPAN were reviewed for segment revenue, capacity expansion, capital expenditure and customer commentary. The monthly revenue disclosures that Taiwan-listed companies, including Unimicron Technology, Nan Ya PCB and Kinsus Interconnect Technology, publish through the Taiwan stock exchange reporting system were used to track the timing of demand corrections and recoveries at a finer interval than annual data allow. Disclosures from upstream suppliers such as Ajinomoto, Nittobo, Resonac and Mitsubishi Gas Chemical gave indications of ABF film, glass cloth and laminate demand, while results and presentations from chip designers, foundries and outsourced assembly providers indicated end-market volume trends and the ramp of interposer-based and chiplet packaging.
Government and regulatory sources were reviewed for policy measures affecting substrate supply and demand, including semiconductor incentive programs, investment approvals, export control rules on advanced computing chips and tariff actions on electronic components. Customs and trade statistics were analyzed using the Harmonized System tariff lines that cover printed circuits and related parts, recognizing that IC substrates are typically reported together with other printed circuit products and therefore served as directional indicators of trade flows between producing and consuming economies rather than as direct measures of ABF substrate value.
Technical literature provided the basis for segment definitions and content assumptions. Proceedings of the IEEE Electronic Components and Technology Conference and of IMAPS events, together with trade journals covering semiconductor packaging and printed circuit manufacturing, were reviewed for information on layer counts, body sizes, line and space roadmaps, warpage control, glass core development and the substrate requirements of chiplet and interposer packages. Patent databases were searched to identify the technology focus of leading substrate makers and material suppliers, including filings on build-up dielectrics, embedded bridges, fine-line semi-additive processing and glass core structures. Paid industry databases, company databases and news archives were used to supplement public sources with financial, shipment and transaction information. Press releases and announcements on plant construction, capacity expansion, customer qualification and supply agreements were compiled into a supply-side tracker, which recorded the location, timing and target product of each substrate capacity project and was used to assess the supply base available in each year of the study period.
Primary Research
Primary research was conducted to validate the secondary findings, obtain information that is not publicly disclosed and refine the assumptions used in the market models. Interviews were carried out by telephone, video call and email using semi-structured discussion guides tailored to each respondent group, and covered both the supply side and the demand side of the ABF substrate value chain.
On the supply side, respondents included executives, product managers, sales personnel and technical staff at ABF substrate makers, as well as personnel at suppliers of ABF film and other build-up dielectrics, low-expansion glass cloth, core laminates, copper plating chemistry and surface finish chemistry. Equipment suppliers, including providers of laser drilling, direct imaging, plating and inspection systems, were consulted on capacity additions, tool lead times and the equipment intensity of fine-line and high-layer-count production. These discussions focused on capacity utilization, yield on large-body substrates, pricing trends by layer count and body size, customer qualification cycles and the timing of new plant ramps. Material suppliers were also asked about allocation practices for ABF film and T-glass cloth during periods of tight supply, and about the qualification of alternative dielectric and core materials by substrate makers.
On the demand side, respondents included packaging and procurement personnel at chip designers developing CPUs, GPUs, AI accelerators, networking ASICs and automotive system-on-chip devices; packaging engineering teams at foundries operating interposer-based packaging lines; outsourced semiconductor assembly and test providers that procure substrates for flip-chip assembly; original equipment manufacturers and original design manufacturers building servers, notebooks and networking equipment; and infrastructure teams at hyperscale cloud companies that design custom silicon. These interviews addressed substrate specifications for current and upcoming programs, sourcing strategies, dual-sourcing practices, expected volume ramps and the outlook for chiplet adoption and glass core substrates.
The objectives of primary research were to confirm the allocation of supplier revenues to layer count, package architecture and application segments, to validate average selling prices and substrate content per package, to assess the regional location of substrate consumption and to test the forecast drivers and scenarios. Primary research also captured qualitative views on competitive positioning, including which suppliers hold qualified positions on leading server and AI accelerator programs and how customers weigh technology capability, capacity assurance, price and geographic diversification when awarding substrate business. Responses were cross-checked between respondents and against secondary data, and differences were resolved through follow-up discussions. Information obtained in interviews was used in aggregated form only, and individual respondent views were weighted according to the respondent's position in the value chain and direct exposure to each subject area.
Market Size Estimation
Market size was estimated using both bottom-up and top-down approaches, and the results were reconciled to produce the base year estimate and the historic series.
The bottom-up approach started from unit shipments of the semiconductor devices that use ABF substrates. Shipment estimates were developed for desktop and notebook CPUs, client GPUs, server CPUs, data center GPUs and custom AI ASICs, network switch and router ASICs, FPGAs, automotive compute system-on-chip devices and game-console processors. Each device category was mapped to its typical package architecture, whether single-die FC-BGA, multi-die or chiplet FC-BGA, or interposer-based packaging, and to its typical substrate characteristics, including layer count, body size and line and space requirement. Average selling prices were then assigned by layer count and body size, informed by supplier disclosures and primary interviews, with adjustments for yield-related pricing on the largest substrates. Multiplying unit volumes by substrate content and average selling price produced segment values, which were summed to give application, architecture and layer count totals. Where a single product family uses substrates of different specifications across its variants, such as client processors offered in several package sizes or accelerators with different numbers of memory stacks, the mix of variants was estimated separately so that substrate content reflected the actual product range shipped. Shipments were also adjusted for inventory movements in the supply chain, which were material during the correction that followed 2022, so that substrate demand was aligned with the timing of substrate purchases rather than with end-device sell-through.
The top-down approach started from the revenues of ABF substrate makers. IC substrate or electronics segment revenues reported by the leading suppliers were collected, and the portion attributable to ABF substrates was estimated by separating BT, FC-CSP, printed circuit board and other businesses using company disclosures, capacity data and interview input. The resulting ABF substrate revenues were aggregated across the reference company set and adjusted for the share of smaller and regional producers. Supplier revenues were then allocated to segments according to each company's known customer mix, technology position and capacity by layer count.
Regional and country values were derived by mapping substrate consumption to the location of chip designers, packaging operations and system assembly, using primary research, trade flow indicators and the geographic revenue disclosures of suppliers and customers.
The bottom-up and top-down results were compared at total and segment level. Where differences arose, the underlying assumptions on unit volumes, substrate content, pricing and supplier revenue allocation were reviewed and revised. The final estimates were validated through data triangulation, which combined the two modeling results with primary research feedback, so that the market total, the segment values and the regional values agree with one another and with observed supplier performance.
Forecasting Methodology
The forecast was built with driver-based models that link ABF substrate demand to the volume and mix of the devices it supports. The principal demand drivers considered were shipments of AI accelerators and data center GPUs, custom AI ASICs designed by hyperscale cloud companies, server CPU shipments and core count trends, PC and notebook unit volumes and refresh cycles, networking ASIC demand linked to data center bandwidth upgrades, adoption of centralized compute architectures in vehicles and the console product cycle.
Content drivers were modeled separately from volume drivers. These included the migration of processors from monolithic dies to chiplet designs, the growth of interposer-based packages that integrate high-bandwidth memory, the resulting increase in substrate body size and layer count, and changes in line and space requirements. The forecast tracked the shift of the layer count mix toward 8–16 Layers and Above 16 Layers and the associated rise in average substrate value per package. For each application, the forecast distinguished between the number of packages and the substrate area and value per package, so that growth in high-content AI and server products was not offset or overstated by changes in lower-content client volumes.
Pricing assumptions reflected the balance between demand and capacity. Announced and expected capacity additions by substrate makers, the time required to qualify new plants with major customers, yield learning on large-body substrates and the supply of ABF film and low-expansion glass cloth were assessed to judge whether average selling prices would rise, hold or decline in each period and segment. Technology transitions, particularly the introduction of glass core substrates and the extension of organic interposers and embedded bridges, were considered for their effect on substrate value and on the boundary of the market.
Scenario analysis was used to test the sensitivity of the forecast to the pace of AI infrastructure investment, the strength of the PC replacement cycle, trade and export control measures and capacity timing. Supply-side checks were applied in each forecast year by comparing modeled demand with the effective output of existing and announced ABF substrate capacity, adjusted for typical utilization and yield, so that the forecast does not imply shipments beyond what the supply base can deliver. The base case forecast reflects the most likely combination of these factors, and the scenario ranges were used to check that the base case remains consistent with supplier capacity plans and customer program expectations.
Base Year
2025
Historical Period
2022 – 2024
Forecast Period
2026 – 2032
Primary Interviews
150+
Historical data (2022–2025) and forecast period (2025–2032)
Our research process spans primary interviews with industry stakeholders combined with comprehensive secondary data analysis, validated through triangulation across multiple independent sources.
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Supply of ABF packaging substrates is concentrated in a small group of manufacturers headquartered in Japan, Taiwan, South Korea and Austria, and the tier that can build large-body, high-layer-count units for server processors, AI accelerators and switch ASICs is narrower still. Ibiden, Shinko Electric Industries and TOPPAN form the Japanese base; Unimicron Technology, Nan Ya PCB and Kinsus Interconnect Technology make up the Taiwanese cluster; Samsung Electro-Mechanics, LG Innotek and Daeduck Electronics represent South Korea; and AT&S is the only European-headquartered supplier of scale, with substrate plants in China, Malaysia and Austria. Mainland Chinese companies, led by Shennan Circuits, are building FC-BGA capability with support from domestic chip designers that want local supply, while Taiwan-listed Zhen Ding Technology is adding ABF substrate capacity at its sites in mainland China and Taiwan. Ownership has also changed: a consortium led by a fund managed by JIC Capital, with Dai Nippon Printing and Mitsui Chemicals, completed its tender offer for Shinko in March 2025, and TOPPAN opened its first FC-BGA plant outside Japan, in Singapore with Broadcom, in September 2026.
Competition is decided first by qualification rather than price. A new substrate source for a server CPU or GPU passes through design-in, reliability testing and OSAT assembly trials before volume orders, and the cycle restarts with each processor generation. Incumbency on a product family is therefore valuable, and entry is slow even for well-funded firms; Shennan Circuits told investors in January 2025 that customer certification for its packaging substrates takes longer than for its other PCB and substrate products.
Technical capability is the second axis. AI accelerators and chiplet processors push substrates toward larger body sizes, more build-up layers, finer SAP line/space, denser bump pitch and tighter warpage control, and LG Innotek exhibited an AI-accelerator FC-BGA with a side length exceeding 100 mm in September 2026. Yield on these units sets cost, because one defect in any build-up layer scraps the whole substrate. Suppliers with mature control of laser via formation, copper plating and lamination on thick, low-CTE cores gain both margin and allocation advantages from the same tooling.
The third axis is commercial: capacity reservations and customer co-development. High-end capacity is increasingly underwritten by buyers. AT&S linked its June 2026 Kulim expansion to long-term commitments from AMD and another leading technology company; Samsung Electro-Mechanics cited customer funding support and mid- to long-term volume commitments for its September 2026 FC-BGA investment; and NVIDIA was reported in October 2026 to be securing substrate capacity in Taiwan, Japan and South Korea through reservation agreements and upfront payments. Suppliers also work with chip designers, TSMC and OSATs at the package-definition stage, matching core thickness, stack-up and power delivery to the die layout of CoWoS and multi-die designs, and they compete on roadmaps for glass core, embedded-die and coreless structures. Secure access to ABF film from Ajinomoto Fine-Techno and to T-glass cloth, which remained tight in 2026, gives an added edge to suppliers with long upstream relationships.
Key Player Positioning
The positioning assigns each supplier to one of three groups, Leaders, Challengers and Niche Players, according to its presence in high-layer, large-body production, its depth of qualification on leading processor and accelerator programs, the breadth of its manufacturing footprint and its ability to fund capacity ahead of demand.
Ibiden, Unimicron Technology, Shinko Electric Industries and AT&S are the Leaders. Ibiden is the reference supplier for server and AI GPU substrates, a long-standing source for Intel processors and a member of the TSMC 3DFabric Alliance. It opened its Ono plant in Gifu Prefecture in October 2025 with staged mass production for AI servers, and in February 2026 approved electronics capital spending of about ¥500 billion over fiscal 2026 to 2028, centered on further capacity at Ono after a first phase at Gama. Unimicron is the largest Taiwanese ABF producer and supplies NVIDIA, Intel and Apple. Its Guangfu plant entered mass production in late 2024 for high-end AI GPU work, part of its Yangmei capacity was redirected to CoWoS customers in 2025, and in July 2026 it raised its 2026 capital budget with most of the spending assigned to ABF substrates. Much of its ABF output ships under long-term contracts, which gives volume visibility in exchange for less pricing flexibility. Shinko brings decades of high-layer server CPU experience and, since its 2025 privatization, a shareholder base that includes the materials and printing groups Mitsui Chemicals and Dai Nippon Printing; it showed a 22-layer glass-core build-up substrate in July 2026.
AT&S qualifies as a Leader through its position on AMD data center processors, served from Kulim, where high-volume manufacturing began in May 2025, alongside its long-established substrate operations in Chongqing. It extended the Kulim build-out in June 2026, added Marvell as a long-term customer for advanced IC substrates in September 2026, and opened an IC substrate plant and competence center in Leoben, Austria, in June 2025, the first such site in Europe.
The Challengers are Samsung Electro-Mechanics, Nan Ya PCB, Kinsus Interconnect Technology and TOPPAN. Each has qualified high-end products and meaningful capacity but trails the Leaders in either breadth of AI-class programs or scale of large-body output. Samsung Electro-Mechanics described itself in September 2025 as the only Korean company mass-producing server FC-BGA, runs FC-BGA lines in Korea and Vietnam, and is developing 2.1D substrates that connect chips without a silicon interposer. Its September 2026 investment plan for Sejong and Vietnam, whose Sejong portion is the largest single-product investment in its history and is due to reach mass production in September 2028, would move it closer to the Leaders if customer volumes follow. Its glass substrate program, run partly through a joint venture with Dongwoo Fine-Chem, targets glass core material in the second half of 2027 and finished substrates in 2028. Nan Ya PCB, part of the Formosa Plastics group, has heavy exposure to high-end ABF products and keeps part of its output outside long-term contracts, which analysts expected in 2026 to let it gain more than peers from rising prices; in 2026 it also outlined a smart factory dedicated to large-size, high-layer substrates.
Kinsus, affiliated with the Pegatron group, was reported in January 2026 to have reserved most of its advanced lines for AI customers, and a March 2026 report said it aims to match rivals such as Ibiden in ABF substrates by 2028. TOPPAN has a concentrated but valuable position in large, high-layer substrates for networking and AI ASICs, with Broadcom as its largest FC-BGA customer. Its Niigata base is now complemented by the Singapore plant of Advanced Substrate Technologies, its joint venture with Broadcom, which opened in September 2026 and targets high-value manufacturing by late 2026.
The Niche Players are LG Innotek, Daeduck Electronics, Zhen Ding Technology and Shennan Circuits, whose ABF activity is either recent, narrow in application or focused on a home market. LG Innotek entered FC-BGA by acquiring a Gumi plant from LG Electronics in 2022 and converted it into a highly automated "Dream Factory" that began mass production in February 2024. It ships PC FC-BGA substrates to North American technology customers, plans to move into server and AI products, and in 2026 announced plans for a substrate plant in Haiphong, Vietnam, whose product range includes FC-BGA. Its exhibit of a 100 mm-class AI-accelerator substrate in 2026 marks the boundary it intends to cross toward the Challenger group. Daeduck Electronics competes mainly in memory and mobile package substrates, with a smaller FC-BGA presence, so its ABF positioning rests on selected customers rather than flagship processor programs. Zhen Ding Technology is the largest PCB group in the reference set and brings scale in manufacturing and procurement; its June 2026 entry into the NVIDIA MGX ecosystem as a board supplier shows access to AI server customers that it can extend into substrates, though its ABF portfolio is still being built.
Shennan Circuits describes itself as the largest Chinese-owned packaging substrate supplier. Its Guangzhou project brought phase-one capacity online in the fourth quarter of 2023, and by May 2026 it reported mass production of FC-BGA at 22 layers or fewer, with products of 24 layers or more in development and sampling. Its prospects depend on domestic CPU, GPU and AI accelerator demand and on export-control conditions rather than on qualification at U.S. processor vendors.
Movement between the groups is most likely where capacity and qualification arrive together. Samsung Electro-Mechanics and Kinsus have the clearest paths to the Leader tier if their new lines are filled by AI accelerator programs, while LG Innotek and Shennan Circuits could rise within the Challenger group if their large-body products pass customer certification.
Competitor Dashboard
The dashboard compares the twelve suppliers on four qualitative dimensions, with ratings that follow the Leader, Challenger and Niche Player grouping. Product Portfolio reflects layer-count and body-size range, Regional Presence reflects manufacturing footprint, Strategic Alliances reflects customer and partner ties, and Industry Experience reflects years in high-end FC-BGA production.
Competitive forces in the ABF packaging substrate industry are shaped by an unusual combination of concentrated upstream materials, concentrated downstream buyers and a manufacturing tier that requires heavy capital and long customer qualification. The balance of power between these groups shifts with the semiconductor cycle: in the 2023 inventory correction, buyers held the advantage and substrate utilization fell, whereas the AI-driven demand for large, high-layer-count substrates in 2025 and 2026 has moved bargaining strength toward material suppliers and the fabricators able to deliver qualified capacity. The assessment that follows reflects conditions at the end of 2026 and their likely direction over the forecast period. Ratings apply to the industry as a whole; where conditions differ sharply between mainstream products such as 4–8 Layers substrates and high-end products such as Above 16 Layers and 2.5D interposer-based substrates, the difference is explained within each force.
Threat of New Entrants
The threat of new entrants is Low. Entry requires a dedicated fab with clean-room build-up lines, laser drilling, laser direct imaging, SAP plating and inspection capacity, and the entry ticket rises with each technology node because high-layer-count products need tighter registration, finer line/space and larger panel handling. Incumbent expansion programs now run to hundreds of billions of yen or tens of billions of New Taiwan dollars for a single business line, which sets the scale an entrant would have to match. Capital alone is not sufficient. A new fabricator must also secure ABF film and T-glass allocation from suppliers that are already rationing output among existing customers, recruit process engineers with SAP experience, and achieve yields that make large-body substrates economic.
The most durable barrier is customer qualification. A CPU, GPU or AI accelerator vendor qualifies a substrate source for each product, a process that includes reliability testing to JEDEC conditions, warpage characterization and pilot production, and that typically runs across multiple quarters before volume orders are placed. Once qualified, a source tends to supply the product for its life, so entrants must win new design slots rather than displace incumbents on running products. The entrants that do appear tend to be adjacent players: Chinese PCB and substrate groups expanding from BT substrates into ABF with domestic customer support, and existing substrate makers moving into the highest-layer-count tier. Glass-core substrate developers, including the SK group's Absolics in the United States, represent a different kind of entry through a new core technology, but they remain at low-volume or pilot scale. Their eventual success would add competitors in the largest package formats rather than in mainstream products.
Government support lowers the financial barrier in some regions without removing the technical ones. Industrial policy in China, India, the United States and Europe offers capital grants, tax credits and land for packaging projects, and new packaging investments in these regions are being planned around such incentives. Even with subsidized capital, a new site must still pass the same qualification and yield thresholds as an incumbent, and the most advanced chip customers have tended to place new programs with established suppliers that are adding capacity rather than with first-time producers. Entry is therefore more plausible in the mainstream tier, where the technology is mature and customers are price-sensitive, than in the highest-layer-count products, where an entrant would compete against suppliers that have co-developed substrates with the chip designer over several generations. Chinese entrants face an additional constraint: their access to build-up film and to advanced Japanese and Western process tools depends on supplier allocation and on the possibility of tighter export rules, while limits on foundry access for China's most advanced AI chips restrict domestic demand for the highest-layer-count substrates.
Bargaining Power of Suppliers
The bargaining power of suppliers is High. Build-up film for CPU, GPU and accelerator substrates comes almost entirely from one company, Ajinomoto Fine-Techno, and production-grade low-CTE T-glass is similarly concentrated at Nittobo. Both materials are qualified at the level of the specific grade and the specific chip program, so a substrate maker cannot switch supplier without the chip customer's agreement and requalification. This concentration became visible in 2026, when film and laminate producers raised prices and allocated output among substrate makers rather than simply expanding shipments to meet orders.
Supplier power also differs by input. Copper foil, standard laminates, plating chemicals and dry films are available from several qualified sources, and their producers have less pricing power. The most acute constraint arises where a material is both effectively single-sourced and consumed in proportion to substrate area and layer count, because demand for such inputs grows faster than substrate unit volumes as AI packages become larger. Build-up film and low-CTE glass cloth meet both conditions, which explains why their suppliers have been able to raise prices and allocate output while suppliers of more standardized inputs have not.
Equipment suppliers add to this power. Laser drilling systems, laser direct imaging tools, plating lines and automated optical inspection systems for fine-line SAP come from a limited group of makers, and the simultaneous expansion programs at Ibiden, Unimicron, Samsung Electro-Mechanics, Kinsus and others have lengthened lead times for long-lead tools. Some substrate makers have placed equipment orders well ahead of building completion to secure delivery slots, which ties capital to supplier schedules.
Two factors moderate supplier power over the forecast horizon. Ajinomoto and Nittobo are both expanding capacity, and both depend on the substrate industry as their main outlet for these products, which gives them a commercial interest in avoiding supply disruption to their largest customers. Alternative suppliers of build-up dielectrics and low-CTE glass cloth are also working toward qualification, and chip designers have an incentive to sponsor second sources for risk reasons. Upstream producers also hold an information advantage: because they receive orders from every substrate maker, they can judge aggregate demand more accurately than any single fabricator and set allocation and price terms accordingly, while their own expansion schedules set the outer limit on how fast the industry can grow. Even so, the time needed to qualify alternatives means supplier power is likely to remain high through most of the forecast period, particularly for materials used in Above 16 Layers substrates and 2.5D interposer-based packages.
Bargaining Power of Buyers
The bargaining power of buyers is Medium. The buyer base is highly concentrated: a small number of CPU, GPU and accelerator vendors, a group of hyperscalers with custom silicon programs, and the foundry and OSAT assembly houses that procure on their behalf account for most high-end substrate demand. These buyers set specifications, control design wins and can shift future programs between qualified suppliers, and during downturns such as 2023 they used this position to secure price reductions and defer volume.
Conditions in 2025 and 2026 have reduced that bargaining strength in the high-end segments. Large AI and server substrates are capacity-constrained, and buyers have moved from negotiating price to securing allocation through deposits, long-term agreements and co-investment in dedicated lines, commitments that tie the buyer to a particular supplier's capacity for several years. Qualification lock-in also limits a buyer's ability to switch suppliers within a product generation. In mainstream segments, by contrast, buyer power remains strong. Substrates for notebook processors in the 4–8 Layers segment are produced by many qualified suppliers, including Chinese entrants, and PC demand is sensitive to consumer spending, so buyers retain pricing power there.
The foundry and OSAT channel adds a further dimension. TSMC, ASE, SPIL and Amkor influence substrate selection through their packaging design rules, assembly capacity and qualification data, and when they procure on a turnkey basis they act as large, informed buyers able to compare suppliers across many customers. For CoWoS-class packages the chip designer generally keeps control of substrate selection, so the assembly house's purchasing influence is greatest in mainstream flip-chip products. Hyperscalers are emerging as an additional buyer group with substantial volume and a willingness to commit capital, which strengthens their hand in allocation talks but also deepens their dependence on specific suppliers. Chip designers fund capacity through deposits and co-investment but have not moved into volume substrate fabrication themselves, so the threat of backward integration remains limited and does not add materially to buyer power.
The overall rating of Medium reflects this split: strong positions for buyers of standard substrates, limited influence for buyers of the most advanced substrates, and a shift back toward buyers if capacity additions outpace AI demand toward the end of the decade.
Threat of Substitutes
The threat of substitutes is Low. Within the FC-BGA package format, there is no commercially established alternative to an organic build-up substrate for carrying large, high-pin-count logic die onto a printed circuit board. BT-based substrates serve memory, mobile application processors and flip-chip chip-scale packages, but they do not offer the fine-line SAP capability, low-loss build-up layers and large-body flatness needed for server CPUs or AI accelerators. Silicon interposers and embedded silicon bridges increase interconnect density between die, but they sit on top of an ABF substrate rather than replacing it, so their adoption raises substrate complexity rather than displacing demand. Switching costs reinforce this position: a chip designer that moved a product from an organic build-up substrate to a different carrier technology would have to redesign the package, requalify reliability and often change the assembly flow, which is practical only at a new product generation.
The substitutes most relevant over the forecast period are technologies that move routing or structural functions out of the organic build-up stack. Fan-out redistribution layers and panel-level packaging can absorb some fine-pitch routing, which may reduce build-up layer count for certain products. Glass-core substrates, which replace the glass-fibre-reinforced organic core with a glass panel, are the more significant long-term substitute because they target the very large body sizes where organic cores face warpage and dimensional limits. Intel, Samsung Electro-Mechanics and Absolics are among the companies developing glass-core technology, and Ibiden has placed a glass core on its roadmap around 2030. These substrates still require build-up dielectric layers, so even their adoption may retain demand for ABF-type films while changing the core. Panel-based variants of interposer packaging under development at TSMC change the format of the interposer rather than the carrier beneath it, and they continue to rely on a build-up substrate to connect the module to the board. Because glass-core volume production is not expected at scale until near the end of the decade, the threat remains low for most of the forecast period but rises toward 2032 for the largest AI packages.
Competitive Rivalry
Competitive rivalry is Medium. The industry is concentrated, with a top tier of Japanese, Taiwanese, Korean and Austrian fabricators supplying the most demanding CPU, GPU and accelerator programs, and a second tier, including the major Chinese makers, competing in mainstream products and expanding upward. Rivalry in the high-end tier is driven by technology rather than price: suppliers compete on line/space, layer count, body size, warpage control and yield on products such as large 2.5D packages, and the reward is a multi-year design win. Under current capacity constraints, these suppliers are largely sold out on qualified high-end lines, which reduces price competition for those products.
Rivalry is far more intense in the standard segments. The 2023 correction left substantial idle capacity for 4–8 Layers substrates, and new capacity from Chinese makers supported by domestic chip and PC customers has added pressure on pricing for notebook and consumer products. Fixed costs are high, so utilization drives profitability, and suppliers compete to keep standard lines loaded while converting what they can to higher-layer-count output. The large expansion programs announced in 2026 by Ibiden, the Taiwanese makers and Samsung Electro-Mechanics could raise rivalry once that capacity comes online, particularly if AI demand growth slows relative to the added supply.
Ownership structures add to the competitive dynamics. Several substrate makers sit within larger groups, such as Samsung Electro-Mechanics in the Samsung group, LG Innotek in the LG group, Kinsus in the Pegatron group and Nan Ya PCB in the Formosa Plastics group, which gives them access to group capital and in some cases to related demand. Exit barriers are high because substrate lines have little alternative use, so suppliers tend to remain in the market through downturns, which sharpens price competition whenever demand weakens. Chinese makers add a further layer of rivalry because domestic chip designers increasingly prefer local sources for strategic reasons, which gives them a protected base from which to expand into higher-layer-count products. The Medium rating balances strong rivalry in mainstream products against capacity-limited, technology-led competition at the high end.
Threat of New Entrants: Low; Heavy capital needs, scarce ABF film and T-glass allocation, SAP yield know-how and multi-quarter customer qualification keep entry limited to adjacent players.
Bargaining Power of Suppliers: High; Build-up film and low-CTE T-glass are effectively single-sourced and program-qualified, letting suppliers raise prices and allocate output during the AI-driven shortage.
Bargaining Power of Buyers: Medium; Concentrated chip designers and hyperscalers hold strong positions in standard substrates, but capacity tightness and qualification lock-in limit them at the high end.
Threat of Substitutes: Low; No established alternative carries large FC-BGA logic packages; interposers sit on ABF substrates, and glass cores reach volume only near 2030.
Market estimates by geography (2032)
InsightAsia Pacific leads with $15.76B by 2032, while Middle East & Africa is projected to grow fastest at a 10.3% CAGR.
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View Subscription Plans| REGION | 2022 | 2025 | 2032 | CAGR | SHARE |
|---|---|---|---|---|---|
| North America | $923.20M | $1.23B | $2.45B | 10.3% | 12% |
| Europe | $527.50M | $584.00M | $968.20M | 6.3% | 5% |
| Asia Pacific | $7.71B | $9.21B | $15.76B | 7.4% | 80% |
| Latin America | $150.70M | $170.10M | $306.30M | 7.4% | 2% |
| Middle East & Africa | $103.60M | $142.90M | $276.60M | 10.3% | 1% |
| Total | $9.42B | $11.34B | $19.76B | 7.7% | 100% |
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View Subscription PlansTotal Market Size
$19.76B
| APPLICATION | REVENUE ($B) | GROWTH RATE | MARKET PENETRATION |
|---|---|---|---|
| 4–8 Layers | $8.69B | 3.7% | 44% |
| 8–16 Layers | $5.93B | 9.2% | 30% |
| Above 16 Layers | $5.14B | 18.5% | 26% |
* Revenue projections based on 2025 estimates. Growth rates represent CAGR 2024–2030. Market penetration indicates current adoption rate within addressable market segments.
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Analytical insights on ABF Packaging Substrates Market covering market dynamics, competitive landscape, and strategic outlook.
The ABF Packaging Substrates Market market is projected to reach $19.76B by 2032, growing at 7.7% CAGR. The 4–8 Layers segment holds the largest share.
Demand for ABF packaging substrates depends less on the number of chips shipped than on the size and complexity of the flip-chip ball grid array (FC-BGA) packages those chips require. A mainstream notebook processor, a general-purpose server CPU and a rack-scale AI accelerator each sit on a single substrate, yet the body size, build-up layer count, line/space and via density of those substrates differ widely, and so does the substrate value per unit. The market therefore responds to two kinds of change at the same time: how many high-performance logic devices are shipped into PCs, servers, networking equipment, game consoles and vehicles, and how much substrate area and layer intensity each device carries as designers move to chiplets, larger package bodies and 2.5D interposer assemblies such as TSMC CoWoS.
Supply is shaped by a narrow production base. ABF dielectric film comes predominantly from Ajinomoto Fine-Techno, low-CTE glass cloth for substrate cores relies heavily on Nittobo, and semi-additive process (SAP) fabrication is concentrated among a small group of Japanese, Taiwanese, Korean, Austrian and Chinese manufacturers. New capacity requires long-lead equipment for laser via drilling, plating, lithography and inspection, followed by months of yield learning on each new body size and layer stack. Supply consequently responds to demand with a lag, and pricing tends to alternate between tightness and surplus, as the 2023 correction in PC and consumer substrates and the AI-led recovery that followed from 2024 illustrated.
The factors that shape the market combine macro influences, namely data center capital spending, industrial policy, trade measures, the PC replacement cycle and vehicle electronics, with industry-level influences, including chiplet adoption, materials availability, manufacturing yield, capacity additions and glass core development. Together they explain why growth is weighted toward high-layer, large-body substrates for AI and high-performance computing, while PC-related packages continue to provide the largest volume base.
Market Growth Factor Analysis
The growth factor analysis assesses ten factors, five macro and five micro, that influence the Global ABF Packaging Substrates Market. The scores are analyst assessments of each factor's impact on market growth, rated on a scale of 0 to 10, where a higher score indicates a stronger influence, for three periods: 2026–2027, 2028–2030 and 2031–2032. Each factor is also classed by the direction of its effect as Promoting, Inhibiting or Steady, so a high score on an Inhibiting factor signals a strong restraining influence rather than a favorable one. The assessments reflect product roadmaps, materials supply, capacity programs and trade policy as of November 2026.
AI data center capital spending carries the highest macro score in every period because it sets the volume of accelerators, custom ASICs, host CPUs, switch chips and network adapters, all of which use large, high-layer FC-BGA substrates. Multi-year commitments support this rating: the agreement between AMD and OpenAI announced in October 2025 covers 6 gigawatts of AMD GPUs, with the first 1-gigawatt deployment of MI450 series GPUs scheduled to begin in the second half of 2026. The slightly lower score for 2031–2032 reflects an expected maturing of the build-out rather than a contraction. Industrial policy scores moderately and rises over time as subsidized packaging and substrate projects, such as the up to USD 75 million CHIPS award finalized for Absolics' Covington, Georgia substrate facility in December 2024, move from construction toward output.
Export controls and tariff measures are rated as Inhibiting. In January 2026 the U.S. Department of Commerce allowed NVIDIA H200 exports to China only on a case-by-case basis with testing and volume conditions, and a 25% U.S. tariff on a narrowly defined category of advanced computing chips took effect on 15 January 2026. Such measures fragment accelerator demand by region and complicate substrate allocation, although their weight eases as supply chains adjust. The PC replacement cycle linked to the end of Windows 10 support on 14 October 2025 scores well in 2026–2027, supporting 4–8 Layers volumes, and fades thereafter. Vehicle electrification and software-defined vehicles gain weight steadily as central computers adopt FC-BGA packaging.
Among micro factors, chiplet and 2.5D packaging adoption scores highest, since it raises substrate area, layer count and routing density per device across CPUs, GPUs and AI ASICs. ABF film and low-CTE glass cloth supply is the strongest near-term Inhibiting factor; Nittobo's expansion at its Fukushima site is not expected to deliver new T-glass supply until mid-2027, and Ajinomoto plans a 50% increase in ABF output by 2030 backed by an investment of at least JPY 25 billion, announced in 2025. The score therefore declines as these programs mature.
Yield on high-layer, large-body substrates remains an Inhibiting factor throughout, because each additional build-up layer and each increase in body size compounds defect and warpage risk. Capacity additions and pricing are rated Steady: Ibiden's board approved an electronics investment of about JPY 500 billion for fiscal 2026–2028 in February 2026, including the Ono Plant, but new lines carry a risk of surplus in standard grades. Glass core substrate readiness is also rated Steady, with a score that rises toward 2031–2032 as glass cores enter limited production while still relying on build-up dielectric layers.
Rising Substrate Area and Layer Count per AI Accelerator
An AI accelerator is the most substrate-intensive device that the ABF supply chain produces. A notebook processor may need a compact body with a modest build-up stack, whereas a current data center GPU combines two reticle-sized compute dies, a silicon or bridge-based interposer and multiple stacks of high-bandwidth memory, all of which must be carried by one organic substrate that fans out power, ground and high-speed signals to the system board. The substrate under such a package is several times larger in area than a client CPU substrate, carries layer counts in the Above 16 Layers range, and must hold flatness across its full body while the interposer, memory stacks and lid are attached. For the substrate industry, this means that growth in AI accelerator shipments translates into a much larger increase in consumed panel area and build-up cycles than the unit count alone would suggest. Each additional pair of build-up layers adds a further cycle of ABF lamination, laser via drilling, desmear, seed-layer deposition, lithography and copper plating, and each cycle introduces another opportunity for defects. A larger body also means fewer substrates per production panel.
Both effects concentrate value in a narrow band of high-end products and make AI accelerators the main reason why the Above 16 Layers and 2.5D Interposer-Based Packages segments are expanding faster than the market as a whole. The same packages also raise the electrical demands on the substrate. Accelerators draw very high currents at low core voltages, so the substrate must provide wide, low-resistance power planes and dense via arrays beneath the interposer, while simultaneously routing hundreds of high-speed lanes for chip-to-chip links and networking. Meeting both requirements within one stack usually means more layers, thicker copper in power planes and tighter control of dielectric thickness, all of which add process steps and lengthen cycle times on SAP lines. Thermal management adds another constraint, since the lid and thermal interface materials attached over very large dies transmit mechanical stress into the substrate, which must therefore combine stiffness with dimensional stability across repeated heating during assembly and test.
NVIDIA's product cadence shows how quickly these requirements are rising. The Blackwell generation placed two reticle-limited GPU dies on TSMC CoWoS-L, which uses local silicon bridges inside an interposer that is itself mounted on an ABF substrate, and the Blackwell Ultra GB300 began volume shipments in the second half of 2025. At CES in January 2026, NVIDIA stated that its Vera Rubin platform was in full production, with Rubin GPUs carrying 288 GB of HBM4 per package and systems scheduled for the second half of 2026. The roadmap published at GTC in March 2025 describes Rubin Ultra for the second half of 2027 with four reticle-sized GPU dies per package and 1 TB of HBM4E. Each step increases interposer size, memory stack count and power delivery, and therefore the body size, layer count and coplanarity requirements of the substrate beneath. An annual product rhythm also means that substrate suppliers must qualify a new, larger design roughly every year rather than amortizing one design over a multi-year platform life.
That rhythm favors suppliers with established engineering relationships, mature large-body process windows and spare capacity on high-layer lines, and it explains why leading substrate suppliers have directed recent investment toward substrates for AI servers. Rack-scale system design adds further substrate content around each accelerator. A Vera Rubin NVL72 system combines 72 GPUs with 36 Vera CPUs, NVLink switch chips and network adapters, and every one of those devices is packaged on an FC-BGA substrate. Growth in accelerator deployments therefore pulls through demand for several other large substrates per rack, extending the effect beyond the GPU package itself and into the 8–16 Layers segment used for many host CPUs and network devices. The pace of these launches also compresses the period in which a substrate design remains in high-volume production. Blackwell, Blackwell Ultra and Rubin overlapped in the supply chain during 2025 and 2026, so substrate makers have had to run ramp-up, peak and end-of-life phases for successive designs in parallel, adding to the capacity tied up in engineering lots and qualification builds.
AMD and the hyperscalers widen this demand base. AMD began shipping its Instinct MI350 series in the third quarter of 2025, combining 3D-stacked compute and I/O dies with eight HBM3E stacks in a single package. At CES 2026 AMD presented the MI455X as the GPU at the center of its Helios rack, alongside the MI440X for standard eight-GPU servers, with Helios scheduled for 2026 and the first 1-gigawatt deployment of MI450 series GPUs for OpenAI beginning in the second half of 2026. Custom AI ASICs developed by Google, AWS, Microsoft and Meta, typically designed with partners such as Broadcom and Marvell and packaged on CoWoS or comparable 2.5D platforms, add further large-body designs. Each ASIC family has its own die arrangement, memory configuration and ball map, so the substrate industry must support a growing number of distinct high-layer designs, each requiring its own tooling, qualification and yield ramp. This diversity has two consequences. It spreads demand across more substrate suppliers, because hyperscalers and their design partners commonly qualify more than one source to secure supply, and it increases engineering workload per unit of output, which keeps large-body capacity tighter than nominal panel capacity figures would indicate.
Hyperscaler programs also tend to run in multi-generation sequences, so a qualified supplier often gains visibility over successive designs, which supports investment decisions in high-layer lines. The addition of OSAT capacity for 2.5D assembly at ASE, SPIL and Amkor alongside TSMC broadens the number of assembly sites that substrate makers must qualify with, adding further process and logistics requirements to each new accelerator program. Accelerators designed for inference add yet another layer of demand. As AI deployment shifts from training models toward serving them to users, cloud providers and enterprises are installing accelerators in a wider range of configurations, from rack-scale systems to standard eight-GPU servers and smaller inference cards. Each configuration uses its own package variant, and lower-cost inference designs often adopt large single-die or multi-die FC-BGA packages rather than full 2.5D integration, which spreads accelerator-related substrate demand across the Above 16 Layers and 8–16 Layers segments and across both interposer-based and direct-attach architectures.
The manufacturing implications explain why accelerator demand dominates investment decisions in the ABF substrate industry. Large bodies are sensitive to warpage during reflow and interposer attach, so substrate makers must balance copper distribution across layers, use thicker or stiffer cores and depend on low-CTE glass cloth to keep expansion compatible with the silicon interposer. Thousands of fine-pitch bumps under the interposer require tight registration between layers and precise via placement, while the large number of layers raises the probability that one defect scraps an entire unit. As a result, a single accelerator substrate can absorb production capacity that would otherwise yield many client CPU substrates, and incremental accelerator demand removes capacity from the market at a faster rate than it adds units. This dynamic supports pricing for high-end substrates, encourages suppliers to dedicate lines to AI and HPC customers, and shifts the product mix of the market toward the AI Accelerators & HPC application. It also changes how capacity is planned. Substrate makers increasingly secure multi-year volume commitments, prepayments or co-investment from accelerator customers before committing to new high-layer lines, because the equipment, cleanroom and materials required for large-body production are costly and specific to this class of product.
Demand from accelerators thus influences not only the volume of the market but also its contractual structure, tying substrate capacity more closely to the product roadmaps of a small number of AI chip designers. Materials consumption follows the same pattern. Because each build-up layer requires its own sheet of ABF film and each large core requires low-CTE glass cloth, the move to bigger, thicker accelerator substrates raises materials demand per unit as well as per panel, which is why tightness in T-glass during 2026 has been felt first in AI-related substrate programs. Substrate makers have responded by prioritizing allocation of constrained materials to their highest-value accelerator products. For the forecast period, the combination of more GPUs and ASICs shipped, larger packages per device and higher layer counts per package makes this the single largest source of value growth for ABF substrates.
Chiplet Disaggregation in Multi-Die Processors
Splitting a processor into several smaller dies improves wafer yield and lets designers mix process nodes, but it moves a large share of the interconnect burden from the silicon into the package. When a monolithic CPU becomes a set of compute chiplets and an I/O die, the wiring that once ran inside the chip must instead pass through the package, either across a silicon bridge or interposer or through the build-up layers of the organic substrate itself. AMD has used this approach in its EPYC server processors since 2017, routing die-to-die links through the substrate rather than through an interposer, and the scale of that routing has grown with each generation. The EPYC 9005 series, launched in October 2024, offers up to 192 Zen 5c cores and places as many as 16 compute dies around a central I/O die on a single organic substrate. The sixth-generation EPYC family, codenamed Venice, which AMD introduced commercially in July 2026, moves to the new SP7 socket with 16 memory channels and offers up to 256 cores built from eight 32-core Zen 6c chiplets.
The larger socket and higher memory channel count increase the body size and pin count of the package, and with them the substrate area and number of signal layers required to escape all die-to-die, memory and I/O connections. AMD's Ryzen desktop processors follow the same multi-die principle at a smaller scale, which means chiplet routing requirements are present across consumer and server products alike. Each of these devices is a Multi-Die / Chiplet FC-BGA package, and the substrate is part of the processor's interconnect fabric rather than a passive carrier. Its electrical performance, including signal integrity on die-to-die links and impedance control on memory channels, directly influences the processor's achievable bandwidth and power. That role makes substrate design an early part of the processor development program and ties substrate suppliers more closely to the CPU roadmap. Because AMD reuses the same compute chiplet across many server and client products, a single chiplet design can generate demand for a wide family of substrate designs with different die counts, body sizes and socket formats.
Intel's client and server roadmaps show a different route to the same outcome. Meteor Lake, introduced in December 2023, was Intel's first high-volume client processor built from separate tiles stacked on a Foveros base die, and Lunar Lake and Arrow Lake extended tile-based designs across its notebook and desktop ranges in 2024. Panther Lake, launched as the Core Ultra Series 3 at CES in January 2026 and built on the Intel 18A process, continues this approach. In all of these products the tiled assembly is ultimately mounted on an ABF substrate that must deliver power to several dies of different heights and route high-speed I/O from each of them. On the server side, the Xeon 6900P series launched in September 2024 with up to 128 performance cores spread over multiple compute tiles and two I/O tiles connected through EMIB, Intel's embedded multi-die interconnect bridge. Because EMIB bridges are embedded inside cavities in the organic substrate, every EMIB-based product adds process steps to substrate fabrication itself.
The Xeon 6+ processor codenamed Clearwater Forest, detailed in March 2026, combines 12 compute chiplets on Intel 18A with three active base tiles on Intel 3 and two I/O tiles on Intel 7, using Foveros Direct stacking and EMIB connections. Designs of this kind require substrates with more layers, embedded features and tighter dimensional tolerances than the single-die packages they replace. The shift also affects the PCs & Notebooks application. Even where notebook unit shipments are flat, the move from monolithic dies to tiled assemblies raises substrate content per device, so the value of client substrates can grow without an increase in the number of PCs sold. Intel's practice of producing different tiles on different process nodes, including nodes from external foundries, adds to the variety of die heights and bump structures that the substrate must accommodate within one package. The combination of Foveros stacking for compute and EMIB for lateral connections also means that a single Intel package can contain silicon bridges embedded in the substrate, active base dies and multiple top dies, which makes the substrate supplier one of the most technically demanding links in the product's supply chain.
Glass Core Substrates as the Next Platform for ABF Build-Up
The most significant technology-led opportunity for ABF substrate suppliers over the forecast period is a change in the substrate core, rather than in the dielectric, from glass-fiber-reinforced epoxy laminate to solid glass. In a conventional FC-BGA, the core built from low-CTE T-glass cloth and resin provides mechanical stiffness, while ABF build-up layers formed by the semi-additive process carry the fine-line routing. As AI accelerator and 2.5D interposer packages move toward body sizes approaching 100 mm per side, the thermal expansion mismatch between an organic core and silicon dies, combined with dimensional movement of the core during repeated lamination and cure cycles, becomes a principal source of warpage, layer-to-layer registration error and yield loss. Glass offers a coefficient of thermal expansion that can be tuned closer to that of silicon, higher flatness and greater dimensional stability, which permits finer via pitch through the core and tighter alignment between layers. Published descriptions of the leading glass core structures, including Intel's reference stack of build-up layers on both sides of a glass core, show that the redistribution layers laminated onto the glass still use ABF or a comparable build-up film.
Glass therefore changes the core material, the core drilling and metallization process and the panel handling infrastructure, but it retains the build-up dielectric, SAP plating and microvia formation steps that define ABF substrate manufacturing. Ajinomoto has publicly described glass and ABF as technologies that can coexist rather than as substitutes. For substrate makers this means that glass core capability is an extension of an existing ABF line, and that value per package can rise because glass cores are aimed at the largest and highest-layer-count designs, which fall in the Above 16 Layers and 2.5D Interposer-Based Packages segments. Suppliers that qualify an ABF-on-glass process early can expect to hold positions in the flagship AI and HPC packages that move to glass first, while continuing to supply organic-core ABF substrates for mainstream CPUs and notebooks. The transition also protects ABF film demand per package, since a glass core substrate for a large accelerator still requires multiple build-up layers on each side of the core.
Intel set the direction for the industry in September 2023, when it announced a glass substrate program aimed at products in the second half of the decade, backed by more than one billion U.S. dollars of investment in glass substrate research and development capability at its Chandler, Arizona site. The program has produced a series of technical milestones since then. In early 2025 Intel demonstrated a system booting an operating system on a glass core substrate, and at NEPCON Japan in January 2026 Intel Foundry showed a thick-core glass substrate of about 78 mm by 77 mm with two EMIB silicon bridges embedded in the glass, reporting no micro-cracking in testing. Intel's commercial posture has shifted over the same period. Industry reporting in 2026 describes the company as emphasizing patent licensing and demonstration vehicles rather than committing to a dated high-volume product, and market analysts place broad commercialization of glass core substrates around 2030. Its glass substrates are reported to be produced only on the Chandler pilot line, with its Rio Rancho, New Mexico site discussed as a possible first volume location. For the ABF substrate market, the significance of Intel's path is twofold.
A licensing-oriented strategy can make glass core process knowledge available to substrate makers and foundry customers that lack Intel's internal data, lowering the cost of entry for suppliers seeking to add glass capability, and it moves glass from a captive Intel technology toward an industry platform that multiple chip designers can specify. The embedding of silicon bridges inside the glass also shows that chiplet packages built on glass will require substrate suppliers to manage cavity formation, bridge placement and ABF lamination over mixed glass and silicon surfaces, adding process steps and engineering content to each substrate. Intel's foundry strategy points in the same direction, since advanced packaging services offered to external customers create demand for substrate partners able to build ABF layers on glass to Intel's design rules and to supply them at volumes that a single internal pilot line cannot support.
The Korean supply base is moving fastest toward commercial glass core output, and its progress sets the qualification window for the wider industry. Absolics, the SKC subsidiary, is building a dedicated glass substrate plant in Covington, Georgia. The U.S. Department of Commerce finalized up to USD 75 million in CHIPS incentives for the facility on 6 December 2024, and in January 2025 Absolics was one of three recipients of USD 100 million each under the National Advanced Packaging Manufacturing Program substrate funding round, supporting its glass-core packaging research. The original goal of mass production in the first half of 2024 was not met; in the first quarter of 2026 the company produced mass-production samples and entered customer qualification, and it is targeting mass production by the end of 2026. Samsung Electro-Mechanics began sampling from a glass substrate pilot line at its Sejong plant in late 2024, moved its glass program into a business-execution organization in February 2026, and in July 2026 formalized a joint venture with Dongwoo Fine-Chem, a Sumitomo Chemical Group company, to produce glass cores at Pyeongtaek, with Samsung Electro-Mechanics holding 66% and operations planned for the second half of 2027.
LG Innotek has produced glass substrate prototypes at its Gumi plant and is reported to target production in 2027 to 2028. TSMC is evaluating glass within its panel-level CoPoS roadmap, for which pilot production is targeted in 2027. The structure that is emerging separates the glass core, which may be made by specialist glass processors or joint ventures, from the build-up, finishing and test steps that remain with substrate makers. This division creates room for established ABF suppliers in Japan and Taiwan, such as Ibiden, Unimicron and Shinko Electric Industries, as well as second-tier producers, to source or co-develop glass cores and apply their own ABF build-up, SAP and electrical test capability rather than building complete glass lines alone. It also gives glass and specialty materials companies a new role in the substrate supply chain alongside the existing T-glass cloth and laminate suppliers.
The technical barriers that remain are themselves a source of opportunity, because they reward the suppliers that solve them first. Through-glass via formation requires laser modification and etching of the glass followed by seed deposition and copper fill; vias of about six microns with aspect ratios greater than 15:1 were demonstrated at ECTC 2025, but reliable metallization of vias smaller than ten microns at production yields is still unresolved. Glass panels chip and crack during drilling, singulation and transport, and early production runs at Absolics were reported in March 2026 to have broken hundreds of panels every few days before edge coating and handling changes reduced measured edge stress. Holding flatness across large panels, achieving adhesion between ABF and the smooth glass surface, and controlling stress during repeated build-up cure cycles add process steps that organic cores do not need, and low-temperature dielectrics that cure under 180°C have been developed specifically to limit thermal stress during build-up.
Each of these issues creates demand for new process modules, including laser via systems, edge treatment, panel transport adapted to brittle substrates, adhesion promoters and modified ABF grades, and it gives substrate makers that invest in pilot lines a learning lead that competitors cannot close quickly. As of August 2026 no glass core substrate had entered a commercially shipping product, which means that qualification slots on the first AI accelerator, network ASIC and server CPU programs to adopt glass remain open. Suppliers that combine an established ABF build-up process with proven glass handling and TGV yield are in a position to win these early programs, and the same capability supports the move of large-body 2.5D packages toward panel-level formats over the forecast period. Because glass core adoption will be selective and concentrated in the highest-value designs, it adds a premium tier to the market without displacing the organic-core ABF substrates that continue to serve the larger volume of PC, server and automotive packages. Early glass programs will also run in parallel with organic-core versions of the same designs during qualification, which adds engineering work for suppliers that support both.
Regional Diversification of Substrate Capacity
Customer demand for geographic diversification of substrate supply is creating a capacity-location opportunity that did not exist when FC-BGA production was concentrated in Japan, Taiwan, South Korea and mainland China. Chip designers and cloud operators now weigh supply resilience, tariff exposure and proximity to packaging and test sites alongside line/space capability and yield when they award substrate business. Because an ABF substrate is qualified for a specific package at a specific plant, a supplier that brings a new site through customer certification can secure multi-year demand from programs that require a second geographic source. Southeast Asia is the first region where this shift is visible at production scale. AT&S started high-volume manufacturing at its Kulim campus in Kedah, Malaysia, in May 2025, with AMD as anchor customer and the site holding AMD certified high-volume manufacturing status; the company reported about EUR 1 billion invested in the campus and stated that further customers would join during the financial year. Kulim places high-end ABF substrate output close to the established semiconductor assembly and test base in northern Malaysia, shortening logistics between substrate delivery and package assembly.
Samsung Electro-Mechanics built an FC-BGA plant in Vietnam in 2021 and, in April 2026, committed about USD 1.2 billion to a new large-scale FC-BGA factory there, stating that its Vietnam and Busan FC-BGA lines were running at maximum output and that customer demand exceeded available capacity. Ibiden operates a plant in the Philippines that the company indicated in 2025 would remain focused on PC-related substrates while its new AI-oriented capacity is concentrated in Japan. These moves show two separate routes for suppliers: new sites can carry leading-edge server and AI substrates directly, as at Kulim and in Vietnam, or they can absorb mainstream PC and notebook volumes and release home-country capacity for Above 16 Layers and 2.5D interposer-based designs. Both routes generate linked demand for ABF film, T-glass cloth, plating chemistry and SAP equipment in each new location.
India is the fastest-developing new location for advanced packaging, and its build-out of assembly and test sites creates a pull for substrate supply within the region. Under the India Semiconductor Mission, the government has approved a series of OSAT and ATMP projects. Micron's assembly and test facility at Sanand, Gujarat, began commercial operations in 2026; CG Semi, the joint venture of CG Power with Renesas and Stars Microelectronics, began commercial production at Sanand in July 2026; Kaynes Semicon inaugurated its Sanand OSAT plant for wire-bond and substrate-based packages in March 2026; and Tata Semiconductor Assembly and Test is building an advanced packaging and test site in Assam. In August 2025 the Union Cabinet approved a 3D Glass Solutions unit in Odisha for advanced packaging and glass substrate technologies, and in May 2026 the Government of Odisha signed a memorandum of understanding with Intel and 3D Glass Solutions for a glass core and high-density interconnect substrate facility in the Bhubaneswar-Khurda region, planned for construction over five to six years. Most first-wave Indian OSAT output targets memory, power, automotive and industrial devices that use leadframe or BT-based packages rather than ABF FC-BGA.
The opportunity for ABF suppliers lies in the next stage, when flip-chip lines for processors, networking chips and automotive SoCs are added and customers ask for substrates delivered from within the region under domestic manufacturing incentives. Substrate makers that establish warehousing, technical service or finishing operations in India at an early stage, or that partner with Indian electronics groups already operating printed circuit board plants, can be positioned to supply that demand as it forms. The approval of a glass substrate project also signals that Indian policy is willing to fund substrate technology directly rather than only assembly, which lowers the investment hurdle for a substrate supplier considering an Indian site. India's position as the fastest-growing country in the market reflects this starting point: demand rises quickly from a small base as packaging capability is installed, and it rewards suppliers that commit before volumes are established and before qualification slots with local OSATs are allocated to competitors.
Capital Intensity, Long Lead Times and Yield Risk in High-Layer Substrates
An ABF substrate line is one of the most equipment-dense investments in the electronics supply chain. A single plant combines clean-room panel handling, vacuum lamination of build-up film, CO2 and UV laser via drilling, desmear, electroless seed deposition and electrolytic copper plating for the semi-additive process, laser direct imaging, automated optical inspection and full electrical test, all sized for large panels and sub-10 µm features. Each of these steps must be duplicated for every additional build-up layer that a product requires, so the equipment content per unit of output rises with layer count. The time between a board decision and saleable volume is long. Ibiden's Ono plant in Gifu Prefecture illustrates the cycle: the site was acquired in September 2021, construction began in December 2022, the building was completed in January 2025, and the opening ceremony was held in October 2025, with mass production for AI server products phased in one line at a time. Nearly four years therefore separated land purchase from first volume, and full output depends on further line-by-line ramp and customer qualification. The scale of current commitments shows how much capital is now at risk.
Reports in August 2026 indicated that Ibiden plans to invest about ¥500 billion over three years from fiscal 2026, and that Unimicron raised its 2026 capital expenditure plan from NT$34 billion to more than NT$53.7 billion, with most of the increase directed to ABF substrates. These budgets are committed against accelerator programs whose final body size, layer count and volume are often not fixed when tools are ordered. A substrate maker that builds for a 16-layer, 75 mm design and is then asked for a 20-layer, 100 mm-class design may find that its lamination presses, plating cells and test fixtures fit the new product poorly, which lowers effective capacity just as demand peaks. Capacity of this kind also cannot be added in small increments: a lamination, plating and inspection line is economic only at a minimum scale, so expansions arrive in large steps that can swing the supply balance from shortage to surplus within one or two years. Smaller producers, which cannot carry several such bets at once, are effectively excluded from the Above 16 Layers tier, so the industry's ability to respond quickly to demand shifts rests on a handful of balance sheets.
Yield on high-layer, large-body substrates is a second constraint, and it compounds with every layer. Each build-up cycle involves film lamination, curing, via ablation, desmear, seed deposition, resist patterning, plating, resist strip and flash etch, and a defect in any one of these steps on any layer normally scraps the entire unit, because a finished substrate cannot be reworked internally. A process with high yield per layer therefore produces a much lower cumulative yield on a 20-plus-layer stack than on a 4–8 Layers PC substrate, and the loss is concentrated at the end of the line where the most value has been added. Electrical test catches opens and shorts, but latent defects such as marginal via interfaces or thin dielectric spots can pass test and fail during the customer's assembly, which extends the cost of a yield problem beyond the substrate plant. Body size makes the arithmetic harsher. As accelerator packages move past 100 mm per side, fewer units fit on each production panel, so every random particle, open or short removes a larger share of panel output.
Zhen Ding, for example, stated in its 2025 results that its ABF substrates reach up to 28 layers and a maximum body size of 158 × 158 mm, which places the industry's leading products at the edge of panel utilization. Warpage is the most persistent technical failure mode. Copper, filled epoxy dielectric, glass-reinforced core and the silicon or interposer assembly expand at different rates, and the mismatch grows with body size, so a substrate that is flat at room temperature may bow during reflow and leave bumps in the center or corners unconnected. Stacked microvias add a separate reliability risk: interfaces at via bottoms can separate under repeated thermal cycling, a failure that may surface only in qualification or in the field. New package formats carry their own learning curve. Reports in August 2026 stated that Unimicron's substrates for Intel's EMIB packaging, slated for mass production in 2027, carry an initial yield target of about 50%. Until yields mature, a portion of installed capacity produces scrap rather than revenue, so nominal capacity overstates the deliverable supply of the most advanced substrates.
The 2023 downturn demonstrated how expensive idle capacity becomes in this industry. Expansion programs launched during the 2021–2022 shortage were sized for continuous growth in PC, server and consumer demand; when inventory correction cut orders, the depreciation on new buildings and tools continued regardless of utilization. Several producers responded by deferring projects. In January 2024 Ibiden postponed the start of operations at its Gama plant in Ogaki from fiscal 2024 to fiscal 2026 and put its medium-term capacity target on hold. AT&S opened the first building at its Kulim site in Malaysia in January 2024 and announced series production of IC substrates for AMD there in May 2025, but kept the second building on hold, with management stating that it would start once the market recovered; the company had also sold its Ansan plant in South Korea to Somacis in autumn 2024. At Unimicron's Yangmei plant in Taoyuan, demand for the EMIB-related technology the site was originally prepared for fell short of projections, and idle capacity was reallocated to CoWoS customers in 2025. These cases show that the cost of misjudging the cycle is borne for years, not quarters.
A deferred building still carries land, utilities and maintenance costs, and tools ordered for one product family may need modification before they can serve another. Process teams assembled for a ramp are hard to retain when lines sit idle, and restarting a mothballed line requires requalification of tools and materials before customer lots can run. Producers whose expansion was weighted toward PC and consumer FC-BGA formats were hit hardest, because those products had absorbed the largest share of new capacity during the shortage and faced the steepest decline in orders. The experience has made boards more cautious about committing to new lines without long-term agreements, customer prepayments or co-investment, which slows the industry's response when demand returns and can turn a demand upswing into a shortage of high-layer, large-body capacity.
Equipment and skilled labor availability lengthen the cycle further. The tool set for advanced ABF substrates comes from a relatively small group of specialist suppliers, including Via Mechanics and Schmoll for drilling, Ushio and SCREEN for exposure, and Orbotech, part of KLA, for direct imaging and inspection. When multiple substrate makers expand simultaneously, as Ibiden, Unimicron, Samsung Electro-Mechanics and LG Innotek all did in 2025–2026, delivery slots for laser drills, plating lines and large-format exposure tools become contested, and installation and acceptance testing must then be completed before qualification lots can run. Plant start-up also requires process engineers experienced in SAP, fine-line etching and warpage control, a skill set concentrated in Japan, Taiwan and South Korea. New sites in Southeast Asia, Europe or North America must either transfer staff from established plants or train local teams, both of which take time and can depress yields during the first production phases. Utilities add a further constraint, since SAP plating and wet processing consume large volumes of ultrapure water and require stable power, and securing these at a new site can take as long as constructing the building itself.
Customer qualification adds another layer of delay: a new plant producing a qualified design must still pass the chip vendor's package-level reliability tests, and accelerator customers frequently require qualification on each new product generation. The result is that the effective lead time for meaningful new capacity in the 8–16 Layers and Above 16 Layers categories is measured in years, while accelerator product cycles are measured in roughly twelve to eighteen months. This mismatch forces substrate makers to choose between building ahead of uncertain demand, with the risk of stranded assets, and waiting for firm orders, with the risk of losing share to competitors that moved first. Either path restrains the rate at which supply can expand, and it encourages customers to secure capacity through long-term contracts that limit the flexibility of both parties.
Concentrated Upstream Supply of Build-Up Film and Low-CTE Glass Cloth
The dielectric that gives the product its name comes, in practice, from one supplier. Ajinomoto Fine-Techno, a subsidiary of Ajinomoto, is reported to hold more than 95% of the global market for build-up film used in FC-BGA substrates, and its film is specified in the qualified material stacks of virtually every high-performance CPU, GPU and AI accelerator package. Production is concentrated at a small number of Japanese sites, currently the Kawasaki headquarters and the Gunma plant. Ajinomoto has committed to expansion: in March 2025 reports stated that the company would invest at least ¥25 billion through 2030 to raise ABF capacity by 50%, and in May 2026 Ajinomoto Fine-Techno announced the purchase of land in Kani City, Gifu Prefecture, for a third production base, with construction scheduled to begin in 2028 and operations in 2032. The timetable shows that a major step in film supply is still several years away, while substrate demand from AI accelerators is rising now. Pricing power has followed the concentration.
Reports in May 2026 stated that Ajinomoto had informed substrate makers of a film price increase of about 30%, expected to take effect from the third quarter of 2026, and the company's electronic materials business reported an operating margin exceeding 50% for the fiscal year ended March 2026. For substrate makers, single sourcing creates three distinct exposures. Supply allocation becomes a commercial lever that favors the largest buyers and the highest-value products. In periods of tight supply, smaller substrate makers and those serving lower-layer programs may receive less film than they request, which caps their output regardless of their own equipment capacity. Any disruption at a Japanese film plant, whether from equipment failure, contamination or natural disaster, would affect the entire industry at once, with no qualified alternative available in volume. Finally, cost increases arrive as an industry-wide shock that substrate makers must negotiate with chip customers who are themselves under cost pressure, which is difficult for producers whose order books lean toward PCs & Notebooks and other price-sensitive applications. The new Gifu plant will add a third site once it operates, but until then the industry's build-up dielectric supply rests on two locations in one country.
Low-CTE glass cloth has become a second chokepoint, and in 2025–2026 a more acute one. The glass-fiber cloth reinforcing the core laminate and prepreg in large-body substrates must have a low coefficient of thermal expansion to limit warpage, and the preferred material for advanced packages is T-glass from Nittobo, which is reported to produce roughly 90% of the world's supply. Larger accelerator packages consume more cloth per unit, and the same material is also used in thin substrates for smartphone memory and system-in-package devices, so demand from several segments converged on one source. T-glass matters most for the thick, large-area cores used in AI accelerator and server packages, where conventional E-glass lacks the thermal stability needed to keep warpage within assembly limits; E-glass remains adequate mainly for lower-end products. In January 2026 reports stated that Apple, NVIDIA, AMD, Google and Amazon had approached Nittobo directly to secure larger allocations, and that Qualcomm had visited Unitika, a smaller Japanese glass cloth developer. By March 2026 prices for the material were reported to have risen by 20–30%, while lead times for copper-clad laminates using it had lengthened from 8–10 weeks to more than 20 weeks.
Nittobo is tripling capacity at its Fukushima facility, but new supply from that expansion is not expected to reach the market until mid-2027; it is also doubling raw yarn capacity in Taiwan and partnering with Nan Ya Plastics, which is expected to weave about 20% of Nittobo's glass cloth by 2027. Industry analysts quoted in March 2026 expected the supply-demand imbalance to persist until at least the second half of 2027. Glass cloth production depends on furnaces operating at 1,600–1,700°C and on proprietary glass compositions, so new entrants cannot add capacity quickly. Until the Fukushima expansion arrives, substrate makers face a ceiling on core laminate output for large-body products regardless of how much plating or lamination capacity they install, and customers with direct relationships with Nittobo may secure supply ahead of others. The constraint therefore falls hardest on the Above 16 Layers and 2.5D Interposer-Based Packages categories on which the market's growth depends most.
Finer Patterning and Lower-Loss, Lower-CTE Build-Up Dielectrics
Line and space dimensions on ABF substrates are shrinking to keep pace with the bump pitch and escape-routing density of chiplet-based processors. Each additional compute tile, I/O die or memory interface adds hundreds or thousands of signals that must fan out from the die shadow through the top build-up layers, and the narrower the lines that can be placed between vias, the fewer layers are needed to route them. For years, volume production of high-end FC-BGA substrates has used semi-additive process features in the range of roughly 8–10 µm line and space, with leading products moving toward 5/5 µm and development programs targeting finer geometries still. Reaching these dimensions requires changes throughout the SAP sequence. Seed layers must be thinner and more uniform so that flash etching removes them without undercutting the plated lines. Build-up film surfaces must be smoother after desmear, because the micro-roughness that once anchored electroless copper becomes comparable in size to the features themselves. Dry-film photoresists must resolve narrower openings with straighter sidewalls, and laser direct imaging tools must hold alignment across large panels that distort during lamination and cure.
Plating uniformity becomes a yield issue in its own right, since thickness variation on a 5 µm line affects both resistance and impedance. Substrate makers are also adopting hybrid stacks in which only the top one or two layers carry the finest features, while lower layers use coarser rules that are cheaper and more tolerant. The trend has direct consequences for the Above 16 Layers and 8–16 Layers segments. Finer rules can slow the growth in layer count for a given routing load, but they raise the process difficulty of each layer, so the value per substrate increases even where layer count stabilizes. LG Innotek's presentation at KPCA Show 2026 of an AI accelerator FC-BGA larger than 100 mm per side with denser circuitry than standard versions, planned for mass production in 2027, reflects how producers are positioning finer patterning as a differentiator for large-body products.
Via formation is following the same path toward smaller dimensions and higher density. Microvias connecting adjacent build-up layers are formed by laser ablation, and their diameter, together with the surrounding capture pad, sets a floor on how closely routing channels can be spaced. Producers are reducing via diameters by moving from conventional CO2 lasers toward UV and short-pulse laser sources for the finest layers, which produce cleaner holes with less heat damage in thin dielectric films, and by tightening registration so that smaller pads can be used without breakout. Stacked via structures, in which vias in successive layers are placed directly on top of one another, save routing area but demand reliable copper fill and strong interfaces, because any void or weak bond becomes a fatigue point under thermal cycling. Staggered via arrangements remain common in reliability-sensitive designs because they spread stress, but they consume more area, so the choice between stacked and staggered structures has become a trade-off negotiated layer by layer. A further direction is the use of photo-imageable dielectrics in the top layers of the build-up stack.
With a photosensitive dielectric, vias are opened lithographically in a single exposure rather than drilled one at a time, allowing smaller and more uniform vias at fine pitch, a technique familiar from wafer-level redistribution layers. The trade-off is that photo-imageable materials have historically offered less favorable mechanical, thermal and dielectric properties than filled ABF-type films, so they are typically confined to the layers where density matters most. The boundary between substrate and interposer is becoming less distinct as a result. TSMC's CoWoS-R uses a polymer and copper redistribution-layer interposer, and as substrate makers bring finer lines and lithographic vias into the top of the build-up stack, some routing that would otherwise require a silicon interposer may move onto the organic substrate. That prospect affects the balance between Multi-Die / Chiplet FC-BGA and 2.5D Interposer-Based Packages, and it requires substrate plants to adopt equipment, cleanliness standards and process control practices closer to those of wafer-level packaging lines.
Electrical requirements are shifting dielectric development toward lower dissipation factor and lower dielectric constant. Network switch ASICs, AI accelerators and the retimers and optical engines around them are moving from 112G to 224G-class SerDes signalling. At 224 Gb/s using PAM4 modulation, the symbol rate is 112 GBaud and the Nyquist frequency is 56 GHz, so the dielectric and conductor losses accumulated across a few centimeters of substrate routing consume a meaningful part of the channel's total loss budget. Dielectric loss rises with both frequency and dissipation factor, which pushes material suppliers to formulate build-up films with lower Df. Glass cloth in the core also contributes to loss and skew, so low-Dk glass and spread-weave cloth are being considered for the layers that carry the fastest signals. Signal integrity analysis also has to account for material variation between lots, because small shifts in Dk change impedance on narrow traces. Lower Dk helps by reducing capacitance and allowing narrower traces at a given impedance, which fits the move to finer line and space. Conductor loss raises a parallel challenge.
At these frequencies current crowds into the outer skin of the copper, so surface roughness, which traditionally provided mechanical adhesion between plated copper and dielectric, now adds measurable loss. Low-loss dielectrics usually rely on less polar resin chemistry, and less polar resins bond less readily to copper, so maintaining adhesion and peel strength on smooth surfaces is a central formulation and process problem. Ajinomoto has supplied successive generations of ABF with progressively lower loss characteristics, and its pricing power in electronic materials reflects demand for these advanced grades. For substrate makers, each new low-loss grade brings new lamination, laser and desmear conditions to learn. The impact is most direct in Networking & Communications, where switch packages carry large numbers of high-speed lanes, and in AI Accelerators & HPC, where scale-up links between accelerators run at similar rates. Co-packaged optics adds a further requirement, because routing between switch silicon and optical engines on a shared substrate must maintain signal integrity across a larger area.
Thermal and mechanical behavior is driving parallel development of lower-CTE build-up films and core materials. As package bodies grow and silicon content increases, the mismatch between the expansion of the organic substrate and that of the dies, interposer and stiffener becomes the main source of warpage during assembly and of solder joint fatigue during operation. Material suppliers reduce the CTE of build-up films chiefly by increasing the loading of fine silica filler and by adjusting resin chemistry, but higher filler content raises stiffness and changes how the film behaves under laser ablation and desmear, so each lower-CTE grade requires recalibration of via formation and copper adhesion. Producers also have to consider the interaction between low-CTE and low-loss requirements: fillers and resins that lower expansion may raise dielectric loss or complicate fine-line plating, and suppliers must balance these properties within one film. The core side of the substrate follows the same direction, with low-CTE glass cloth, higher-modulus laminates and thicker cores used to hold large panels flat, though core material supply is itself constrained.
Asymmetric stacks, in which the number or thickness of build-up layers differs between the die side and the board side, are being adjusted with these materials to balance stresses through the stack thickness. Underfill and stiffener choices made by OSATs interact with these substrate properties, so material selection is increasingly coordinated across the full package bill of materials rather than optimized by the substrate maker alone. Simulation and metrology are changing as well. Substrate makers increasingly model warpage across the full assembly temperature profile with customer and OSAT data, and measure flatness at multiple temperatures rather than at room temperature alone. These developments raise the engineering content of each design, deepen joint development among film suppliers, substrate makers, OSATs and chip vendors, and increase the switching cost once a material stack is qualified. They also define the performance that organic cores must reach to remain competitive with glass core alternatives, which promise lower CTE and better flatness, so improvements in organic dielectrics and core laminates remain central to the roadmap of established ABF producers.
Embedded Passives and Power-Delivery Integration in the Substrate
Kilowatt-class accelerators are turning the substrate into an active part of the power-delivery network rather than a passive carrier of signals. A processor drawing around 1,000 W at a core voltage under 1 V draws more than 1,000 A, and that current must pass from the board through BGA balls, through-core vias, power planes and microvias to the bumps under each die. Every milliohm of resistance in that path produces voltage drop and heat, and every picohenry of loop inductance limits how quickly the supply can respond when the workload changes abruptly, as it does when thousands of compute units start or stop together. Conventional designs handle these transients with decoupling capacitors mounted on the land side of the substrate or on the board beneath the package. As accelerators add power, the number of capacitors needed rises, and they compete for surface area with the BGA balls that carry power in. Their distance from the die also sets a floor on loop inductance that no amount of additional capacitance can overcome.
Land-side capacitors also occupy the area directly beneath the die, which is the shortest path for current from the board, so designers face a direct conflict between decoupling and power entry. The industry response is to move charge storage closer to the silicon, into the interposer, the bridge dies and the substrate itself. For substrate makers this changes the product definition: power-integrity performance becomes a specification they are accountable for, alongside routing density and warpage, and the substrate's internal structure is increasingly designed around current flow. The trend touches every architecture in scope, from Single-Die FC-BGA server CPUs to 2.5D Interposer-Based Packages for AI accelerators, but its pace is set by the highest-power AI Accelerators & HPC products, where power-delivery limits can cap achievable clock speed and sustained performance. Substrate design is therefore becoming a joint exercise among chip architects, power-delivery engineers, OSATs and substrate makers, with power maps and transient load profiles exchanged at the start of the design cycle rather than after the die floorplan is fixed, as was customary for conventional packages.
Embedded silicon capacitors are moving from development into production. Silicon capacitors, built with deep trench structures on silicon wafers, offer high capacitance density in very thin form factors and can be placed inside a substrate cavity, directly under the die, where their connection path is short. Compared with multilayer ceramic capacitors of similar footprint, silicon devices offer stable capacitance across temperature and voltage and a thin, flat profile that suits lamination inside a build-up stack, although their cost per unit of capacitance remains higher. In June 2026 Samsung Electro-Mechanics stated that it had started ramping production of silicon capacitors embedded in FC-BGA substrates for AI data centers and PC CPUs, as part of a strategy combining its MLCC, silicon capacitor and substrate businesses; reported customers include Marvell for AI ASICs, and the company disclosed a KRW 1.5 trillion supply agreement with an unnamed global technology company, expected to contribute revenue from 2027. In September 2026 LG Innotek showed FC-BGA substrate samples with embedded silicon capacitors for AI semiconductors, placed either in the core layer, which accommodates thicker, higher-capacitance devices, or in a build-up layer, which uses thinner devices to limit total substrate thickness.
LG Innotek described the benefits as shorter electrical paths to the chip, potentially lower parasitic inductance during fast load transients, and freed surface area for routing and other components. Embedding introduces process steps that conventional substrates do not require: forming precise cavities, placing components with tight positional accuracy, laminating build-up film over them without voids, and drilling microvias that land on the capacitor terminals. Each step adds yield risk, and a defective embedded component cannot be replaced, so incoming component testing and in-process inspection become more important. Test strategy changes as well, since the electrical behavior of the embedded network must be verified after lamination rather than component by component. The approach also blurs traditional supply boundaries, because the substrate maker now sources or manufactures active-looking silicon parts and must qualify their reliability inside its own laminate structure. Substrate makers with in-house capacitor businesses, such as Samsung Electro-Mechanics, may gain an advantage from controlling both the component and the embedding process.
The value chain for ABF packaging substrates runs from a small group of specialty material and equipment suppliers, through a concentrated tier of substrate fabricators, to chip designers, assembly houses and system builders. Each stage is technically coupled to the next: a change in die size, bump pitch or package architecture at the chip designer flows back into the substrate's layer count, line/space and core design, and from there into the grade and volume of build-up film, glass cloth and copper foil that must be qualified. Because almost every input is specific to fine-line semi-additive processing, the chain is short in the number of participants but long in qualification time, and its economics are set mainly by yield, material allocation and capacity commitments rather than by logistics or channel margins. Three flows run through the chain at the same time: materials and finished panels moving downstream, design and reliability requirements moving upstream from chip designers, and, increasingly, capital moving upstream in the form of customer deposits and co-investment. The balance among these flows determines which participants capture margin at each point in the semiconductor cycle.
Raw Materials and Inputs
The defining input is Ajinomoto Build-up Film, an epoxy-based resin system filled with fine silica that is supplied as a thin film on a carrier and vacuum-laminated onto the substrate core. ABF provides the dielectric for every build-up layer: it must accept laser via drilling, survive desmear, bond to an electroless copper seed layer, and hold its dimensions through repeated thermal cures. Ajinomoto Fine-Techno, the electronic materials subsidiary of Ajinomoto Co., supplies more than 95% of the film used for CPU and GPU substrates, according to TrendForce reporting in April 2025. The company was reported in March 2025 to plan at least JPY 25 billion of further investment by 2030 to raise ABF capacity by about half, and in May 2026 it announced the purchase of land in Kani City, Gifu Prefecture, for a third production base scheduled to begin construction in 2028 and operations in 2032. In May 2026 Ajinomoto also informed substrate makers of a price increase of roughly 30%, effective in the third quarter of 2026. Sekisui Chemical and Resonac offer build-up and related dielectric materials, but qualification of an alternative film on a high-volume FC-BGA program takes multiple product cycles, so the film supplier's allocation decisions directly shape how much substrate capacity can be loaded.
The core is the second major material stream. ABF substrates use copper-clad laminate cores reinforced with woven glass cloth, and for large-body server and AI packages the cloth increasingly has to be low-coefficient-of-thermal-expansion T-glass to limit warpage during die attach and reflow. Nittobo holds an estimated share of around 90% of production-grade T-glass, and industry reporting in 2026 described a commitment of about JPY 80 billion to roughly triple its T-glass output by the fiscal year ending March 2029 compared with the fiscal year ended March 2026, including a doubling of capacity in Taiwan. Core laminates themselves come from Resonac, Mitsubishi Gas Chemical and a few other resin and laminate producers, several of which were reported to have raised copper-clad laminate prices in 2026. Thick cores of the type used in 2.5D packages also call for hole-plugging resins and through-hole fill materials matched to the core's expansion behavior.
Metallization inputs complete the bill of materials. Copper foil is used on the core, while build-up layers are metallized by electroless copper seed deposition followed by electrolytic pattern plating, which requires plating chemistry from specialist suppliers such as Atotech (part of MKS Instruments), JCU and Uyemura. Dry-film photoresists from Asahi Kasei and Resonac define the pattern, solder resist from suppliers such as Taiyo Ink protects the outer layers, and surface finishes such as ENEPIG or OSP prepare bump pads. The process equipment layer is equally specialized: CO2 and UV laser drilling systems from Via Mechanics and Schmoll form microvias; laser direct imaging and projection exposure tools from Orbotech (KLA), SCREEN and Ushio set fine line/space; vacuum laminators, horizontal and vertical plating lines, and automated optical inspection systems from Orbotech and others control registration and defect density. The value added at this stage lies in materials science and process consistency, and the main dependency is concentration: a handful of Japanese material firms and a limited set of tool makers supply inputs that cannot be substituted quickly without requalification by both the substrate maker and the chip customer.
Substrate Manufacturing
Substrate fabrication is where most of the chain's value is created. The process starts with core preparation: mechanical or laser drilling of through-holes, copper plating of the hole walls, resin plugging, planarization and patterning of the core's outer copper. The build-up sequence then repeats for each layer pair on both sides of the core: ABF lamination and cure, laser drilling of blind microvias, desmear, electroless copper seed, dry-film lamination, exposure, electrolytic pattern plating, resist strip and flash etching of the seed layer. A substrate described as 10-2-10, for example, has ten build-up layers on each side of a two-layer core, and each of those layers is a full SAP cycle that must register to the layer beneath it. After build-up, the panel receives solder resist, surface finish and, for many designs, pre-solder or micro-bump formation, followed by electrical testing, warpage measurement and final optical inspection.
Process control is the core of a fabricator's know-how. Build-up lines run on standard working panels of roughly half a square meter, which are carried through lamination, imaging and plating with registration tolerances of a few micrometers across the panel. Dimensional change in the core and in each ABF layer during cure has to be predicted and compensated in the imaging data, and plating thickness has to stay uniform across the panel so that fine lines on outer layers are neither under-plated nor bridged. Electrical testing uses fixture-based or flying-probe systems to detect opens and shorts in every unit, and units are mapped so that only good substrates reach assembly. Experience accumulated over several product generations, rather than equipment alone, is what separates high-yield producers from the rest of the field.
The economic logic of this stage is driven by yield. A defect in any layer scraps the whole unit, so cumulative yield falls as layer count rises, and large body sizes reduce the number of units per working panel, which raises the cost of each scrapped panel. This is why substrates in the Above 16 Layers segment and those carrying 2.5D interposer-based packages command far higher unit values than the 4–8 Layers substrates used in mainstream notebook processors: they consume more ABF area, more SAP passes, more inspection time and more panel area per good unit. Fabricators add value through line/space capability, via-on-via stacking reliability, warpage control on thin or very thick cores, and the ability to hold electrical test yield on very large packages.
The manufacturing tier is concentrated in Japan, Taiwan and South Korea, alongside Austria's AT&S and a growing group of mainland Chinese makers. Ibiden, Unimicron, Shinko Electric Industries, AT&S, Nan Ya PCB, Kinsus Interconnect Technology, Samsung Electro-Mechanics, LG Innotek, TOPPAN, Daeduck Electronics, Zhen Ding Technology and Shennan Circuits make up the reference supplier set. Capacity decisions are capital-intensive and lumpy. Ibiden's board approved about JPY 500 billion of electronics capital expenditure for fiscal 2026 through fiscal 2028 in February 2026, extending a first phase at its Gama plant with a further build-out at its Ono plant for high-performance server substrates. Taiwanese makers and Samsung Electro-Mechanics have announced their own multi-year equipment and building programs. The dependencies at this stage run in both directions: fabricators depend on ABF and T-glass allocation and on long-lead tool deliveries, while each new chip program depends on a fabricator completing product-specific qualification, which ties a chip generation to a short list of substrate sources for its life.
Distribution and Channels
ABF substrates are not sold through distributors. They move directly from the fabricator to the party that assembles the package, under one of two commercial models. In the first, the chip designer selects and qualifies the substrate supplier, negotiates price and volume, and contracts directly with the fabricator; the substrates are then delivered on consignment to the foundry or outsourced semiconductor assembly and test (OSAT) provider that performs die attach and package assembly. Large x86 and GPU vendors such as Intel, AMD and NVIDIA have historically operated this way for their flagship products because the substrate is a design-critical component. In the second model, the OSAT or foundry procures the substrate on a turnkey basis and bills the chip customer for the finished package, an arrangement more common for smaller fabless companies, networking ASICs and lower-layer-count products where the assembly house already carries qualified substrate sources. In both models, pricing is negotiated per product and usually per unit, with volume bands and periodic resets, and for high-end FC-BGA packages the substrate is one of the most expensive items in the bill of materials after the die and memory.
Advanced 2.5D packages add a further layer to the channel. In TSMC's CoWoS flow, the chip-on-wafer assembly with HBM stacks on a silicon or organic interposer is completed at TSMC, and the interposer module is then mounted on the ABF substrate either at TSMC or at partner OSATs such as ASE and its subsidiary SPIL, and Amkor. The chip designer generally specifies the substrate supplier and design for these packages, so substrate volumes follow the designer's allocation of CoWoS capacity rather than the OSAT's own purchasing. This coupling means that substrate demand for the 2.5D Interposer-Based Packages segment is planned against interposer and HBM availability, and any constraint at one point shifts the timing of orders at the others.
Supply tightness has turned capacity reservation into part of the channel structure. Taiwanese financial press reported in 2026 that Intel, NVIDIA and AMD had paid deposits to reserve high-end substrate capacity, although the amounts were not confirmed by the companies. On 21 October 2026 NVIDIA and Samsung Electro-Mechanics announced a multi-year agreement to jointly invest in dedicated ABF substrate lines at Samsung Electro-Mechanics' Sejong and Busan sites, with supply to begin in 2026. Arrangements of this kind, whether prepayments, co-funded tools or dedicated lines, shift part of the capital risk from the fabricator to the customer in exchange for guaranteed allocation. Physical logistics are comparatively simple, with moisture-barrier packing, controlled storage and short lead distances to assembly clusters in Taiwan, South Korea, Malaysia and the Philippines, but the contractual terms that govern allocation are now as important as price.
End Users
The direct customers of ABF substrates are semiconductor companies that design FC-BGA packaged chips: Intel and AMD for client and server CPUs; NVIDIA and AMD for GPUs and AI accelerators; Broadcom and Marvell for networking switch ASICs and custom accelerators; Apple, Qualcomm and MediaTek for PC-class and high-performance SoCs; and Sony and AMD for game-console processors. Hyperscalers form a distinct and growing group of specifiers. Google, Amazon Web Services, Microsoft and Meta design custom accelerators, usually with a design partner such as Broadcom or Marvell, and increasingly engage substrate makers directly to secure supply and influence substrate roadmaps for their own programs.
Each application group places a different set of requirements on the substrate. Networking switch ASICs and FPGAs use large, high-layer-count substrates with demanding signal-integrity budgets, because SerDes channels running at 112G and 224G per lane need low-loss dielectrics and tightly controlled impedance across the package. AI accelerators combine several compute die and HBM stacks on an interposer, which raises body size, power delivery current and warpage sensitivity. Automotive SoCs for central compute and driver assistance require extended temperature-cycle reliability, strict change-notification discipline and long production lifetimes, which favors suppliers with automotive-qualified lines. Game-console processors are large packages built in high volume over a long product life, with price pressure increasing as each console generation matures. From the substrate maker's perspective these customers are not interchangeable: capacity and process windows tuned for one group cannot always be redirected to another without requalification.
Beyond the chip designers, original equipment manufacturers and original design manufacturers that build notebooks, servers, network switches, vehicles and consoles determine end demand and set reliability conditions. PC and notebook OEMs drive the largest volume of 4–8 Layers and Single-Die FC-BGA substrates, with demand tied to processor refresh cycles. Server makers and hyperscale operators determine the pace of demand for high-layer-count substrates through their data center build plans, while automotive Tier-1 suppliers and vehicle makers require substrates for central compute and advanced driver-assistance SoCs that meet automotive qualification and traceability rules. The end-user stage adds value by integrating packaged chips into systems, but it also feeds requirements back up the chain: larger AI packages, tighter warpage budgets and longer qualification for automotive products all translate into specific demands on substrate design, materials and capacity.
Regulation affects ABF substrates less through product-specific rules than through industrial policy, trade and export controls on the chips they carry, and environmental and quality frameworks that govern materials and manufacturing. The status of each instrument has shifted frequently since 2022, and the descriptions that follow reflect the position in late 2026 where it could be confirmed. For substrate makers, the practical questions are where incentives make new capacity economic, which customers can legally ship the chips their substrates carry, and which materials and processes will remain permissible over the life of a production line.
North America
The U.S. CHIPS and Science Act, signed in August 2022, created manufacturing incentives and research programs, including the National Advanced Packaging Manufacturing Program (NAPMP). The act provided about USD 39 billion for manufacturing incentives and about USD 11 billion for research and development. In January 2025 the Department of Commerce announced USD 1.4 billion in final NAPMP awards, including USD 300 million for substrates and materials research split equally among Absolics for glass-core substrates in Covington, Georgia, Arizona State University for fan-out wafer- and panel-level processing, and Applied Materials for silicon-core substrate technology, and USD 1.1 billion for an advanced packaging piloting facility in Tempe, Arizona. In August 2025 Commerce declared its agreement with Natcast void and placed the National Semiconductor Technology Center under direct NIST control, changing how the research programs are administered. The department has also renegotiated a number of manufacturing awards, and in August 2025 it converted grants previously awarded to Intel, one of the largest buyers of ABF substrates, into an equity stake of about 10% in the company. The advanced manufacturing investment credit for semiconductor facilities was raised to 35% by the One Big Beautiful Bill Act of July 2025, for projects that begin construction by 31 December 2026.
Export controls administered by the Bureau of Industry and Security shape demand for the most advanced substrates by limiting where high-end accelerators can be sold. Rules issued in October 2022, October 2023 and December 2024 set and tightened performance thresholds for advanced computing chips, expanded equipment controls and added high-bandwidth memory controls. The AI Diffusion Rule of January 2025 was rescinded in May 2025. An Affiliates Rule extending Entity List restrictions to companies at least 50% owned by listed parties was issued in September 2025 and suspended for one year from November 2025, with the suspension due to lapse in November 2026 unless extended. In January 2026 BIS moved license applications for chips at the H200 and MI325X class to China and Macau from a presumption of denial to case-by-case review, subject to supply, screening and third-party testing conditions.
On trade, the Section 232 investigation into semiconductors and derivative products began in April 2025. Proclamation 11002 of 14 January 2026 imposed a 25% tariff from 15 January on a narrow set of advanced logic chips and products containing them, with exemptions for uses including U.S. data centers, research and consumer electronics. A broader second phase covering finished products had been under consideration during 2026 but had not been proclaimed as of late October 2026. A U.S.–Taiwan arrangement announced in January 2026 links future duty-free import quotas to U.S. capacity investment. Canada and Mexico are linked to U.S. supply chains through the USMCA, with Mexico relevant mainly as a server and electronics assembly base.
Standards bodies headquartered in the region define the technical baseline for substrate qualification. IPC-4101 specifies base materials for laminates and prepregs, IPC-2221 sets generic design rules, and IPC-6012 governs qualification and performance of rigid boards and is often referenced for substrate acceptance. JEDEC's JESD22 series sets reliability test methods such as temperature cycling and highly accelerated stress testing, and J-STD-020 sets moisture and reflow sensitivity classification. IPC-A-600 provides visual acceptability criteria for printed boards that substrate makers and their customers often adapt for incoming inspection. For automotive applications, AEC-Q100 defines stress-test qualification for integrated circuits, which places demands on the substrate within each qualified package.
Europe
The European Chips Act entered into force in September 2023, establishing the Chips for Europe Initiative, a framework for first-of-a-kind production facilities and a crisis monitoring mechanism. On 3 June 2026 the European Commission proposed a Chips Act 2.0 as part of a Technology Sovereignty Package, adding strategic projects across the value chain from materials to advanced packaging, permitting decisions within 12 months and demand-side measures. The proposal is in the ordinary legislative procedure with the European Parliament and the Council and had not been adopted as of late 2026. Europe has limited ABF substrate production, with AT&S the main European-headquartered maker, so the practical effect of these instruments is to support packaging and materials projects that could anchor regional demand. In parallel, the Important Project of Common European Interest on Microelectronics and Communication Technologies, approved by the Commission in June 2023, authorized state aid for projects across the microelectronics value chain, which member states have used alongside Chips Act instruments.
Chemical and product rules apply to substrates as components of electronic equipment placed on the EU market. The RoHS Directive (2011/65/EU), with the four phthalates added by Delegated Directive (EU) 2015/863, restricts ten substances in homogeneous materials, which governs solder, surface finishes and resin additives. REACH (Regulation (EC) No 1907/2006) requires disclosure of substances of very high concern exceeding threshold concentrations, and the WEEE Directive (2012/19/EU) places end-of-life obligations on equipment producers. Halogen-free specifications based on IEC 61249-2-21, which limits chlorine and bromine to 900 ppm each and 1,500 ppm combined, are widely requested by European system makers and feed into ABF and laminate grade selection. The automotive quality management standard IATF 16949 governs supply to European vehicle makers and is required of substrate makers serving automotive programs.
The universal PFAS restriction proposed under REACH in 2023 is the most significant pending measure. ECHA's Risk Assessment Committee adopted its opinion in March 2026, the Socio-Economic Analysis Committee published a draft opinion that month, and a consultation closed in May 2026. A final committee opinion is expected by the end of 2026, Commission adoption is not expected before the third quarter of 2027, and restrictions would not apply before 2029. Fluoropolymers in process equipment, fluorinated surfactants in plating and etching chemistry, and fluorinated components in photoresists are among the substrate-relevant uses being assessed.
Product-level sustainability rules are also widening. The Ecodesign for Sustainable Products Regulation (EU) 2024/1781, in force since July 2024, allows information and performance requirements, including digital product passports, to be set for product groups through delegated acts. Requirements of this kind would reach substrate makers indirectly, through requests from equipment producers for material composition, recycled-content and carbon data, rather than as direct legal obligations.
Asia Pacific
Japan's Economic Security Promotion Act, enacted in 2022, under which semiconductors were designated a specified critical product in December 2022, allows the Ministry of Economy, Trade and Industry to support stable-supply plans for semiconductors and their key materials. In November 2024 the government announced a framework of more than JPY 10 trillion in public support for AI and semiconductors through fiscal 2030. These measures matter to ABF substrates because Japan hosts the main suppliers of build-up film and T-glass and major fabricators including Ibiden, Shinko and TOPPAN. Taiwan's Statute for Industrial Innovation was amended in 2023 to add Article 10-2, which provides a 25% tax credit on qualifying R&D spending and a 5% credit on investment in advanced process equipment for companies meeting scale and R&D intensity thresholds, for the period 2023 to 2029.
Taiwan's position was also shaped by the arrangement with the United States announced in January 2026, under which Taiwanese companies committed to at least USD 250 billion of direct investment in the United States, and companies building U.S. chip capacity may import up to 2.5 times that planned capacity free of the new U.S. semiconductor duties during construction and 1.5 times once it is complete.
South Korea's National Assembly passed an amendment to the Restriction of Special Taxation Act, known as the K-Chips Act, on 27 February 2025, raising tax credits for semiconductor facility investment from 15% to 20% for large and medium-sized companies and from 25% to 30% for small and medium-sized firms, and extending the semiconductor R&D credit to the end of 2031. Samsung Electro-Mechanics, LG Innotek and Daeduck Electronics are the Korean substrate makers most directly affected.
China's Export Control Law has applied since December 2020. Licensing controls on gallium and germanium took effect in August 2023, and an outright ban on exports of these metals to the United States followed in December 2024. In November 2025 China suspended the U.S.-specific ban until 27 November 2026, while the general licensing requirement remains. China's third national integrated circuit investment fund, registered in May 2024 with capital of RMB 344 billion, the largest of the three national funds to date, supports domestic packaging and materials, which benefits makers such as Shennan Circuits and others expanding into ABF products.
India's Semicon India Programme, approved in December 2021 with an outlay of INR 76,000 crore and run by the India Semiconductor Mission, has approved a fab and several assembly and test projects, including Micron's facility in Sanand and Tata Electronics' facility in Assam, creating future local demand for FC-BGA substrates. Malaysia, which hosts substrate and assembly operations including AT&S's Kulim site, launched a National Semiconductor Strategy in May 2024 with RM 25 billion of fiscal support, aimed at moving the country into advanced packaging and front-end activities.
Rest of the World
In Latin America, the relevant framework is mainly industrial incentive policy. Brazil's PADIS program offers tax incentives for semiconductor and display manufacturing activities, which currently center on memory and assembly rather than FC-BGA products, and Argentina has no substrate-specific regulation. Regional demand for ABF substrates arrives embedded in imported servers, PCs and vehicles, so product rules in destination markets matter more than local law.
In the Middle East and Africa, the main regulatory factor is U.S. export licensing for advanced accelerators destined for data centers in the UAE and Saudi Arabia, which has proceeded through individual licenses since the AI Diffusion Rule was rescinded in 2025. These licenses determine how many AI accelerators, and therefore how many high-layer-count substrates, are deployed in the region, so the large AI data center campuses planned in both countries depend on U.S. licensing policy rather than on local substrate regulation. South Africa's electronics regulation centers on product safety and end-of-life management and has little direct effect on substrate supply.
Since 2024, supplier activity has centered on new plants for AI server and accelerator substrates, customer-backed capacity agreements, ownership changes and early work on glass core substrates. The record covers announcements and completions confirmed by company releases or news reports.
12 Dec 2023: Shinko Electric Industries; Merger & Acquisition; A fund managed by JIC Capital, with Dai Nippon Printing and Mitsui Chemicals, announced a plan to acquire Shinko from Fujitsu through a tender offer and take it private.
24 Jan 2024: AT&S; Expansion; Opened its first Southeast Asian IC substrate plant in Kulim, Malaysia, with Plant 1 producing high-end substrates for AMD data center processors; investment to date exceeded EUR 1 billion.
14 Mar 2024: TOPPAN; Expansion; Subsidiary Advanced Substrate Technologies, supported by Broadcom, broke ground in Singapore on a plant for high-end FC-BGA substrates for network switches and AI devices.
23 Sep 2024: AT&S; Divestment; Signed an agreement to sell AT&S Korea, including its Ansan plant, to SO.MA.CI.S. S.p.A. at an equity value of about EUR 405 million.
18 Mar 2025: Shinko Electric Industries; Merger & Acquisition; JICC-04, funded by JIC Capital-managed funds, Dai Nippon Printing and Mitsui Chemicals, completed its tender offer for Shinko shares, clearing the way for delisting.
25 Mar 2025: LG Innotek; Investment; Signed an MOU with Gyeongsangbuk-do Province and Gumi City to invest KRW 600 billion through 2026 in expanded FC-BGA substrate lines and camera module facilities in Gumi.
5 May 2025: AT&S; Expansion; Started high-volume manufacturing of high-end IC substrates at its new plant in Kulim Hi-Tech Park, Malaysia.
3 Jun 2025: AT&S; Expansion; Opened Europe's first IC substrate plant and competence center in Leoben, Austria, combining R&D and IC substrate production within the IPCEI microelectronics framework.
3 Sep 2025: Samsung Electro-Mechanics; Product Launch; Unveiled a glass core package substrate about 40% thinner than existing products at KPCA Show 2025, alongside 2.1D substrates and high-end server FC-BGA for AI.
10 Oct 2025: Ibiden; Expansion; Opened its Ono plant in Gifu Prefecture, its largest domestic site, with staged mass production of IC package substrates mainly for AI servers starting in October 2025.
27 Feb 2026: Ibiden; Investment; Approved about JPY 500 billion of electronics capital investment for fiscal 2026 to 2028, mainly at Ono Plant (Cell8), for high-performance server IC package substrates.
15 Jun 2026: AT&S; Investment; Announced a EUR 1.5 to 2.0 billion Kulim expansion, fitting out Plant 2 and a new site for IC substrate cores, based on agreements with AMD and another technology company.
29 Jul 2026: Unimicron Technology; Investment; Raised its 2026 capital expenditure budget to about NT$53.7 billion, with most spending directed to ABF substrate capacity, including Guangfu and Yangmei plant expansions.
9 Sep 2026: LG Innotek; Product Launch; Showed publicly for the first time an FC-BGA substrate for AI accelerators with a side length over 100 mm at KPCA Show 2026.
22 Sep 2026: AT&S; Partnership; Expanded its collaboration with Marvell Technology under a long-term agreement adding advanced IC substrate capacity at Kulim for AI and cloud infrastructure.
29 Sep 2026: Samsung Electro-Mechanics; Investment; Announced about KRW 6.78 trillion of FC-BGA investment for AI servers: KRW 4.27 trillion at Sejong, with mass production from September 2028, and KRW 2.51 trillion in Vietnam.
29 Sep 2026: TOPPAN; Expansion; AST, its joint venture with Broadcom, opened Singapore's first high-end FC-BGA substrate facility for AI compute and networking, three months ahead of schedule.
Political
Political factors work mainly through supply-chain location. ABF substrate production and its upstream materials are concentrated in Japan, Taiwan, South Korea and China, and governments in the United States, Europe and India want more of the packaging chain within their own borders or allied territory. Chip designers have responded by asking substrate makers for multi-site supply, which has supported capacity in Malaysia, Japan and South Korea alongside Taiwan. Political tension between the United States and China creates a two-track market: Chinese chip designers increasingly qualify domestic substrate sources, while Western and Taiwanese designers favor suppliers outside China for their most advanced products. Trade negotiations that link tariff relief to investment add a political dimension to plant siting that did not exist before 2025.
The concentration of advanced substrate and CoWoS assembly capacity in Taiwan also draws political attention to cross-strait risk, which encourages customers to qualify Japanese, Korean and Southeast Asian capacity as a hedge. Governments have also become more directly involved in commercial decisions, attaching conditions on location, technology sharing and investment timing to subsidies and tariff relief, so that substrate customers' sourcing choices increasingly reflect policy as well as cost. Competition among governments for packaging investment also gives substrate makers bargaining power in site selection, since several jurisdictions now offer grants, tax credits or land for the same projects. Policy reversals following elections or trade negotiations remain a planning risk, because substrate plants take years to build and depend on incentive and tariff assumptions holding for much of their payback period.
Economic
The economics of the business are dominated by capital intensity and utilization. High-layer-count lines require large investments in clean rooms and SAP equipment, and the return depends on keeping them loaded through the semiconductor cycle. Hyperscale data center spending on AI infrastructure has become the main source of incremental demand, which makes substrate profitability more dependent on a small number of corporate capital budgets than in the PC-driven era. Input cost inflation in build-up film, laminates and copper is passed through unevenly: suppliers of high-end AI substrates can negotiate price increases, while makers of standard notebook substrates absorb more of the cost. Currency movements also matter, as a weak yen lowers costs for Japanese fabricators relative to Taiwanese and Korean rivals that buy Japanese materials.
Substrate demand also amplifies the underlying chip cycle. When processor inventories build up, as in 2023, assembly houses and chip designers cut substrate orders faster than end demand falls, and when demand recovers they rebuild inventory at the same time as they ramp new products. Depreciation on newly built high-layer-count lines weighs on margins in the early years of each expansion, so the timing of capacity additions relative to customer ramps has a direct effect on supplier earnings across the forecast period. Customer prepayments and co-investment change the financing economics of the industry: they lower the fabricator's cost of capital and reduce demand risk on new lines, but they also commit capacity to specific customers for several years and limit the supplier's freedom to reallocate output if more profitable demand appears. For automotive substrates the economics differ again: volumes are smaller and qualification is longer, but product lifetimes and pricing are more stable than in PCs or AI hardware.
Social
Workforce availability is the main social factor. SAP process engineering, laser and imaging tool maintenance and yield analysis require specialized skills that are concentrated in a few regions, and Japan and Taiwan face aging populations and competition for technical talent from wafer fabs. New substrate sites in Malaysia, India and the United States must build these skills from a smaller base, which affects ramp timing and early yields. Consumer behavior influences the volume end of the market: adoption of AI-capable notebooks and replacement cycles for gaming consoles determine demand for PCs & Notebooks and Gaming Consoles & Consumer Devices substrates. Local communities near new fabs also scrutinize water use, chemical handling and traffic, which can lengthen permitting.
Public attitudes toward AI infrastructure matter as well: local opposition to the power and water use of large data centers in some U.S. and European communities can slow hyperscale build-outs and, with them, demand for high-layer-count substrates. Labor and social conduct standards are also part of commercial qualification. Large chip designers and hyperscalers require their substrate suppliers to follow codes such as the Responsible Business Alliance Code of Conduct, covering working hours, recruitment practices and health and safety, and audit compliance at substrate sites. As new plants open in Southeast Asia and India, recruiting practices for migrant and contract workers receive closer review from customers and investors. Workforce development programs in India and Malaysia, often run jointly by governments, universities and investing companies, are intended to build the technician and engineer base that new substrate and assembly plants will need.
Technological
Technology change is the fastest-moving factor. AI accelerators are moving to larger body sizes and higher layer counts with each generation, and line/space on the finest build-up layers is shrinking toward single-digit micrometers. Ibiden's roadmap, as reported in 2026, moves from packages of about 90 mm by 90 mm in 2026 to about 110 mm by 110 mm in 2028, with build-up structures rising from 10-X-10 to 12-X-12. These changes raise demands on warpage control, via reliability and power delivery, which favors low-CTE core materials and thicker cores. Chiplet architectures increase the number of die on a single substrate and the density of die-to-die routing. Embedded passive and active components and new core materials are in development and will change substrate design over the forecast period, while advances in inspection, metrology and process control determine which suppliers can hold yields on the largest products.
Manufacturing technology is changing in parallel. Fabricators are adopting larger working panels, greater automation of panel handling, and machine-learning-assisted optical inspection to reduce defect escapes on layers with very fine line/space. The pace of this change creates a widening gap between suppliers that can fund new-generation lines and those limited to older equipment, which over the forecast period shapes which makers can participate in the fastest-growing segments. Co-packaged optics, in which optical engines are mounted beside switch or accelerator die on the same substrate, would add optical alignment, thermal and mechanical requirements to substrate design, and is under development by several networking chip vendors. Design practice is also changing, as substrate, interposer and die are increasingly co-designed in shared electronic design automation and thermal-mechanical simulation flows, with substrate makers placing application engineers alongside chip designers from the earliest stages of a program.
Environmental
Substrate manufacturing is energy- and water-intensive. Each build-up layer passes through wet chemical steps for desmear, electroless and electrolytic plating and etching, producing copper-bearing wastewater that must be treated, and clean rooms, curing ovens and laser tools draw substantial electricity. As hyperscalers and chip designers set supply-chain emission targets, substrate makers are asked to report product-level carbon data, increase renewable power purchases and improve water recycling. The growth in large AI substrates intensifies this pressure because each unit consumes more panel area, material and process time. Material choices also have environmental implications: halogen-free resin systems, lead-free finishes and the gradual replacement of fluorinated process chemicals all affect qualification work for substrate makers and their suppliers.
Physical climate and natural-hazard risks are also relevant because production is concentrated in seismically active regions of Japan and Taiwan and in areas exposed to periodic water stress. Customers increasingly ask suppliers to document business continuity plans, multi-site options and water-recycling capacity as part of supply qualification. Yield improvement has an environmental dimension as well: every scrapped large-body panel represents material, energy and chemical use with no saleable output, so yield gains reduce waste per good substrate. Electricity demand from AI data centers has a second-order effect on substrate design: operators' focus on energy per computation favors packages with shorter interconnects and more efficient power delivery, which pushes substrate makers toward embedded capacitors, integrated voltage regulation and thicker copper for power planes.
Legal
Legal exposure for substrate makers centers on contracts, intellectual property and compliance. Long-term supply agreements, prepayments and co-investment arrangements carry take-or-pay, allocation and exclusivity terms that define each party's risk if demand changes, and these terms are increasingly negotiated by legal teams rather than set by purchasing departments. Process know-how in SAP and fine-line patterning is a valuable trade secret, and staff movement between Japanese, Taiwanese, Korean and Chinese firms raises the risk of disputes over misappropriation. Export compliance obligations extend to substrate makers through customer screening and end-use certifications, particularly for products destined for advanced accelerators. In automotive supply, liability exposure and traceability requirements make documentation of materials, lots and process changes a contractual obligation. Automotive customers also expect suppliers to support recalls and field-failure investigations for many years after production, which extends legal exposure well beyond the commercial life of a substrate design.
Competition law adds a further consideration. Long-term exclusive arrangements and dedicated-line agreements between dominant buyers and a limited number of suppliers can draw scrutiny where they restrict rivals' access to scarce capacity, and supply concentration in build-up film means allocation practices may also attract attention from competition authorities. Intellectual property in emerging areas such as glass cores, embedded components and fine-pitch build-up materials is being patented actively, which raises the likelihood of licensing negotiations as these technologies enter production. Shortage conditions have also tested allocation and force majeure clauses, and both suppliers and buyers are revising contract language on priority, penalties for shortfall and the treatment of prepayments if a program is cancelled or delayed.
Profiles of 34 companies operating in the ABF Packaging Substrates Market market, including revenue, employee count, and market positioning where available.
Showing 34 of 34 companies
FY2022/23–FY2024/25 year-end headcounts were not captured in the releases reviewed. The 31 Dec 2024 figure was 13,204. The interim decline to 13,051 at 30 Sep 2025 reflects the deconsolidation of Ansan, Korea (sold January 2025) and the cost programme. AT&S is Europe's largest, and the Western world's only scaled, manufacturer of high-end IC substrates. It is also a top-tier producer of advanced printed circuit boards (HDI, mSAP/substrate-like PCBs, embedded-component boards). The company sits at the interface between semiconductor packaging and electronic system assembly. It supplies the ultra-fine-line interconnect platforms on which leading-edge processors, AI accelerators and server CPUs are mounted, and the dense boards inside smartphones, wearables, vehicles, medical devices and industrial equipment. More than three-quarters of revenue comes from US-headquartered customers and most sales are denominated in US dollars, while the cost base is spread across Austria, China, Malaysia and India. After a punishing 2023–2025 down-cycle financed by a ~€3.5bn capacity build-out, AT&S has re-rated into an AI-infrastructure play. Long-term, customer-financed capacity agreements with AMD and Marvell now underpin a €1.5–2.0bn Kulim expansion and guidance for 45–55% currency-adjusted revenue growth in FY2026/27. --- **What the company does.** AT&S designs and manufactures two families of interconnect products: 1. **IC substrates.** These are multilayer, ultra-high-density carriers that sit between a semiconductor die (or a set of chiplets) and the system PCB. They fan out thousands of micro-bumps at the die side to a coarser pitch the motherboard can accept. AT&S focuses on ABF-based flip-chip ball-grid-array (FC-BGA) substrates for high-performance computing (CPUs, GPUs, AI accelerators, networking ASICs). This requires large body sizes, high layer counts, fine line/space, and increasingly advanced cores and embedded structures. 2. **Advanced printed circuit boards.** These include high-density interconnect (HDI) and any-layer boards, modified semi-additive process (mSAP) "substrate-like" PCBs for smartphones and wearables, and boards for automotive (ADAS, radar, power electronics, e-mobility), industrial, medical and aerospace. The PCB range also covers embedded-component packaging (ECP) and module integration. **Company's own description (FY2025/26 boilerplate in results releases).** AT&S describes itself as a leading global manufacturer of high-end IC substrates and printed circuit boards. It cites production sites in Austria (Leoben, Fehring), China (Shanghai, Chongqing), Malaysia (Kulim) and India (Nanjangud), plus a European competence centre for R&D and IC-substrate production in Leoben. It serves mobile devices, automotive, industrial, medical and high-performance computing for AI. (Source: AT&S EQS releases, 30 Sep 2025 and 13 Jun 2026.) **Business model.** AT&S is a build-to-print / co-development manufacturer. It does not sell catalogue products. Each board or substrate is engineered to a customer's design, qualified over 6–24 months, and then produced in volume under multi-year programmes. Revenue is almost entirely product revenue (manufactured units). There is no material subscription, licensing or service revenue, although engineering co-development and module assembly are bundled into pricing. A distinctive feature of the model since FY2021/22 is customer-financed capacity. Under bilateral agreements, customers pre-pay or co-fund dedicated production lines. AT&S received €446M of such payments in FY2021/22 (FY2021/22 results release). The 2026 Kulim and Chongqing expansions are described as "fully supported and financed by long-term customer commitments" (ad-hoc, 13 Jun 2026; Q1 2026/27 release). **Value-chain position.** **Customer types.** Global semiconductor companies (substrates). Smartphone and consumer-device OEMs, tier-1 automotive suppliers, industrial and medical OEMs, and, since FY2025/26, defence and security customers (PCBs). According to APA/Vienna Stock Exchange reporting (Feb 2026), more than three-quarters of revenue is with US companies and the majority is generated in US dollars. Named customers in primary releases: AMD (13 Jun 2026) and Marvell Technology (22 Sep 2026). Other major customers (e.g., Apple, Intel) are widely reported in the press but not confirmed in AT&S releases reviewed. Reuters (15 Jun 2026) cited industry sources naming Intel as the unnamed second Kulim customer; AT&S later identified that customer as Marvell (22 Sep 2026), so the Reuters attribution appears to have been incorrect. **End-markets.** Data centre/server/AI accelerators (described as the growth driver in the H1 2025/26 release), mobile devices and wearables, PCs/notebooks, automotive, industrial, medical and healthcare, aerospace (Leoben holds Nadcap accreditation per aggregator data), and defence/security (entered Sept 2025). **Independent characterisation.** AT&S is now best understood as a two-speed company. The first is a mature, cash-generative but price-pressured PCB franchise (Electronics Solutions). The second is a capital-hungry, operationally geared IC-substrate business (Microelectronics) whose fortunes are tied to AI/HPC package complexity. In FY2025/26 Microelectronics revenue grew 53% (investor presentation summary, Quartr, May 2026). The FY2026/27 guidance step-up is driven almost entirely by substrates. The economics resemble a semiconductor-equipment-intensive foundry more than a classic PCB shop. Utilisation drives margins (start-up costs depressed EBITDA by several points in FY2021/22–FY2024/25), and FX (USD revenue against EUR/MYR/CNY costs) is a first-order earnings variable.
RTX occupies a structurally advantaged position that no other prime replicates: roughly half its revenue is commercial aerospace and half defence, giving it a natural hedge across two cycles that rarely peak together — and which, unusually, are peaking together in 2026. Collins Aerospace and Pratt & Whitney are entrenched on the installed base of the global narrowbody and widebody fleet, generating decades-long, high-margin aftermarket annuities. The Raytheon segment is the Western world's dominant supplier of ground-based air and missile defence effectors — Patriot, GEM-T, AMRAAM, Standard Missile, ESSM — precisely the munitions category that European rearmament and Middle East conflict have made scarce. A record $289 billion backlog at 30 June 2026, equal to roughly three years of sales, converts that positional advantage into unusual revenue visibility. The offsetting reality is that RTX carries $37 billion of debt, an $85 billion goodwill-and-intangible balance from the merger, and the unresolved cost tail of the GTF powder-metal remediation. RTX Corporation is the world's largest aerospace and defence company by revenue, and the only prime contractor that simultaneously holds franchise positions in commercial aircraft engines, commercial aerospace systems, and ground- and sea-based integrated air and missile defence. It was created in April 2020 by the merger of Raytheon Company with the aerospace businesses of United Technologies Corporation, and it renamed itself from Raytheon Technologies to RTX in July 2023 alongside a consolidation from four operating segments to three. --- ### What the company does RTX designs, manufactures, and services aerospace and defence systems for commercial airlines, aircraft OEMs, business aviation operators, the U.S. Government (principally the Department of Defense, latterly styled the Department of War in contract announcements), and allied governments worldwide. Its FY2025 Form 10-K describes the three segments as follows: Collins Aerospace provides advanced aerospace and defence products; Pratt & Whitney supplies aircraft engines; and Raytheon delivers defensive and offensive threat detection and mitigation capabilities. The company's independent characterisation is better expressed as three distinct economic engines bolted onto one balance sheet: 1. **An installed-base annuity business (Pratt & Whitney and, to a lesser degree, Collins).** Engines and nacelles are sold at or near cost — sometimes at a loss — to win position on an airframe, after which spare parts, overhauls, and long-term service agreements generate profit for twenty to thirty years. This is why Pratt & Whitney's reported segment margin (8.3% in FY2025) looks weak against Collins (16.2%) despite comparable revenue: Pratt is still absorbing original-equipment loss content on the GTF ramp while the aftermarket annuity has yet to reach maturity. 2. **A cost-plus and fixed-price government contracting business (Raytheon, plus Collins' defence lines).** Revenue is recognised over time on the percentage-of-completion basis, which makes reported margins highly sensitive to estimate-at-completion revisions. The FY2024 $575 million charge on a terminated foreign fixed-price development contract is the canonical illustration. 3. **A component and systems supply business (Collins).** Avionics, interiors, power management, and aerostructures sold to Airbus, Boeing, Embraer, Bombardier, and defence primes, with a large parts-and-repair aftermarket layered on top. ### Revenue model and mix | Metric | FY2025 | |---|---| | Commercial share of sales | 48% | | Defence share of sales | 52% | | Products share of sales | ~74% | | Services share of sales | ~26% | | Sales to U.S. Government (excl. FMS) | $33,279m (38% of net sales) | | Total international sales | $41,312m (47% of net sales) | | Total backlog | $268bn ($161bn commercial / $107bn defence) | | Backlog expected to convert within 12 months | ~25% | Sources: FY2025 Form 10-K Item 1 (U.S. government and international sales tables, backlog); RTX 2025 Annual Report sales-mix infographic; Q3 2025 disclosure for the product/service split. Note the structural shift: U.S. Government sales fell from 46% of revenue in FY2023 to 38% in FY2025 — not because U.S. volume declined (it rose from $31.6bn to $33.3bn) but because international and commercial revenue grew far faster. This is the single most important mix fact in the company today, because international direct commercial sales carry materially better margins than U.S. cost-type work, and because European air-defence procurement is the fastest-growing pool RTX addresses. ### Value chain position and customers RTX sits at the prime and Tier-1 layers simultaneously. On F-35 it is a major subsystem supplier (F135 propulsion via Pratt; sensors and avionics via Collins) to prime contractor Lockheed Martin — a direct competitor at the enterprise level. On Patriot and SPY-6 it is the prime. On A320neo it is a propulsion and nacelle supplier to Airbus, which in March 2026 was reported to be formally seeking damages from Pratt & Whitney over GTF disruption. This simultaneous supplier/competitor/counterparty posture across the same customer set is a defining feature of RTX's commercial relationships and a recurring source of litigation and negotiation risk. **End-markets served:** commercial air transport (OE and aftermarket); regional and business aviation; rotorcraft; military fixed-wing and rotary propulsion; integrated air and missile defence; naval combat systems; precision-guided munitions; space sensing and communications; airport and airline IT infrastructure; and government training and mission services.
### Identity and listing | Item | Detail | |---|---| | Entity profiled | Illinois Tool Works Inc. (exact legal-name match; active; publicly listed). The input classification "Public company" is confirmed | | Former names | None of significance disclosed. The company has operated as Illinois Tool Works since founding. Commonly abbreviated "ITW" | | Founded | 1912, Chicago, Illinois. Incorporated 1915 (Form 10-K FY2025) | | Jurisdiction of incorporation | Delaware, USA (Form 10-K FY2025) | | IRS Employer ID | 36-1258310 | | Headquarters | 155 Harlem Avenue, Glenview, Illinois 60025, USA. Tel. (847) 724-7500 | | Exchange / ticker | New York Stock Exchange: ITW (common stock) | | Other listed securities (NYSE) | Euro notes: 0.625% due 2027 (ITW27); 3.250% due 2028 (ITW28); 2.125% due 2030 (ITW30); 1.00% due 2031 (ITW31); 3.375% due 2032 (ITW32); 3.00% due 2034 (ITW34) | | ISIN / CUSIP | US4523081093 / 452308109 | | Fiscal year end | 31 December | | Index membership | S&P 500 constituent. Fortune 300 company (company description, 2026) | ### Scale and organisation | Item | Detail | |---|---| | Employees (latest) | About 43,000 at 31 Dec 2025; about 16,000 in the U.S. (Form 10-K FY2025) | | Employee trend | About 46,000 (FY2022 release); about 45,000 (FY2023); about 44,000 (FY2024 release); about 43,000 (FY2025). This is a steady decline driven by 80/20 simplification and productivity, not by revenue contraction | | Organisation | 88 divisions in 49 countries; about 410 plants and office facilities (Form 10-K FY2025) | | Auditor | Deloitte & Touche LLP. Ratification proposed for FY2026 (2026 Proxy) | | Holders of record | About 3,957 at 31 Jan 2026 | | Website | www.itw.com / investor.itw.com | ### Market data | Item | Detail | |---|---| | Shares outstanding | 288.2 million at 31 Jan 2026 (Form 10-K). About 284 million estimated at 30 Jun 2026, after 4.3 million shares were repurchased in H1 2026 (10-Q Q2 FY2026; derived) | | Market capitalisation (current) | About $82 billion. Basis: share price of roughly $288–$295 (5 Aug 2026 close $295.06; early-September 2026 dividend yield of 2.39% implies about $288) × about 284 million shares | | Market cap at 31 Dec 2025 | About $71 billion (2026 Proxy) | | Market cap discrepancies | Third-party aggregators show $71bn–$85bn depending on date. Live verification is recommended | | 52-week range | $238.82 – $303.16 (as of Aug 2026, aggregator data) | Illinois Tool Works is a 114-year-old, Glenview-based multi-industrial manufacturer with $16.0 billion of FY2025 revenue across seven segments: - Automotive OEM - Food Equipment - Test & Measurement and Electronics - Welding - Polymers & Fluids - Construction Products - Specialty Products ITW does not compete on scale or vertical integration. Its edge is a proprietary operating system, the "ITW Business Model," built on three elements: - **80/20 Front-to-Back management**, which concentrates resources on the largest, most profitable customers and products. - **Customer-Back Innovation (CBI)**, which develops products from customer pain points rather than from a central R&D lab. **A decentralised, entrepreneurial culture:** of 88 scaled-up divisions. Since launching its Enterprise Strategy in late 2012, ITW has lifted operating margin from 15.9% to 26.3% and after-tax ROIC from 14.5% to 29.3%. It has done this while shrinking revenue through divestiture of commoditised businesses (2026 Proxy). The "Next Phase" (2024–2030) pivots the agenda from margin expansion to sustained 4%+ organic growth, powered by a 3%+ CBI revenue yield. ITW is a Dividend King, with 63 consecutive annual dividend increases. --- ### Company's own description (Form 10-K FY2025, paraphrased) ITW describes itself as a global manufacturer of a diversified range of industrial products and equipment, organised into 88 divisions operating in 49 countries. Its seven reportable segments are grouped by similar product offerings and end markets. Products are distributed mainly direct to industrial manufacturers and through independent distributors. Backlog is not considered significant because delivery periods are short and inventory turns quickly. The company names its core competitive advantage as the ITW Business Model: - 80/20 Front-to-Back process - Customer-Back Innovation - Decentralised entrepreneurial culture Primary raw materials are steel, resins and chemicals, sourced from numerous commercial suppliers. ### Business model | Revenue type | Characterisation | Evidence | |---|---|---| | Product sales: consumables | Majority of revenue. Welding filler metals; Polymers & Fluids chemicals; fasteners; Hi-Cone carriers; marking inks; test consumables; contamination-control wipes | Segment product lists (10-K FY2025) | | Product sales: capital equipment | Welding power sources; food equipment; test systems (Instron, MTS); electronic assembly equipment; line automation | Segment product lists (10-K FY2025) | | Services | Food Equipment service, maintenance and repair (service organic growth +2.8% FY2025, +4.8% FY2024); aftermarket service in Test & Measurement | 10-K FY2025 Food Equipment discussion | | Software / subscription | Test & measurement software is embedded with equipment. Not reported separately | Not publicly disclosed | | Licensing | Not material / not disclosed | Not publicly disclosed | ITW's model rests on niche leadership in fragmented, technically demanding markets. Its businesses typically hold strong positions in specialised applications where: - the product is a small share of the customer's total cost but critical to performance (e.g., an automotive fastener, a weld wire, a test frame); and - differentiation comes from engineering, application know-how, brand and service. The 80/20 discipline continually prunes low-value SKUs and customers through Product Line Simplification (PLS). PLS deliberately reduced organic revenue by about 60 basis points in FY2024, about 60 bps in FY2025, and about 60 bps in H1 FY2026, in exchange for structurally higher margins (10-K FY2025; 10-Q Q2 FY2026). **Revenue model mix.** ITW does not report a formal product/service/subscription split. The analyst characterisation is: ### Value-chain position ITW sits as a Tier-1/Tier-2 component supplier (Automotive OEM, Specialty appliance components) and as an OEM of branded equipment and consumables (Welding, Food Equipment, Test & Measurement, Construction Products, Polymers & Fluids). It typically manufactures "in the market, for the market." This localisation was cited in FY2025 as the reason ITW could largely offset U.S. tariff costs through pricing and supply-chain actions (FY2025 release; 10-K FY2025). ### Customer types and end markets | Segment | Primary end markets (10-K FY2025) | Customer type | |---|---|---| | Automotive OEM | Automotive OEMs and tiers | Global and Chinese OEMs; Tier-1 suppliers | | Food Equipment | Food service, food retail, food institutional/restaurant | Restaurant chains, independents, institutions (healthcare, education), supermarkets | | Test & Measurement and Electronics | Electronics/semiconductor, general industrial, auto OEM/tiers, energy, industrial capital goods, consumer durables | R&D labs, quality labs, semiconductor fabs, electronics assemblers | | Welding | General industrial (fabrication, shipbuilding), construction, energy, MRO, capital goods, auto | Fabricators, contractors, OEMs; heavily via distributors | | Polymers & Fluids | Automotive aftermarket, general industrial, MRO | Retail auto-care, body shops, industrial maintenance | | Construction Products | Residential construction, renovation/remodel, commercial construction | Contractors, truss fabricators, big-box retail | | Specialty Products | Food and beverage, consumer durables, airlines, general industrial, capital goods, printing/publishing | Beverage packers, appliance OEMs, airports/airlines, packaging converters | ### Independent characterisation ITW is best understood as a portfolio of about 88 mid-sized, high-return niche franchises bound together by a common management system. Corporate allocates capital. Divisions run the business. Strengths of this structure: - A low-capital-intensity, cash-generative model. Capex was 2.6% of revenue in FY2025 ($419M on $16,044M), and after-tax ROIC is about 29–31%. - Demand is diversified across consumer, industrial and capex cycles. Weaknesses of this structure: - Organic growth has historically been modest (FY2023–FY2025 averaged roughly 0–2%). - PLS creates a built-in headwind to reported growth. - The company has unusually high exposure to Detroit-3 and European auto content, short-cycle construction, and the semiconductor capex cycle. The FY2026 data, with Q2 organic growth of +4.5% and double-digit growth in Welding and Test & Measurement, is the first meaningful evidence that the CBI-driven growth pivot may be gaining traction.
Dell Technologies is the world's largest branded server vendor by revenue and the third-largest personal computer vendor, and it is now the principal listed proxy for the migration of artificial-intelligence infrastructure from hyperscale cloud into enterprise, sovereign and neocloud data centres. Two reporting segments — Infrastructure Solutions Group and Client Solutions Group — generated $113.5bn of revenue in FY2026, and the business is running at an annualised revenue rate above $190bn in FY2027 on the strength of AI-optimised server demand. Dell's structural advantages are a direct-plus-channel go-to-market reaching customers in more than 170 countries, a supply chain that can integrate, liquid-cool and deploy rack-scale GPU systems at volume, an installed base served by a global support organisation, and a captive financing arm. Its structural constraints are thin hardware gross margins, a negative book equity position, high customer concentration in AI, and dependence on component suppliers whose pricing power currently exceeds its own. --- ### The company's own description In its FY2026 Form 10-K the Company describes itself as "a leader in the global technology industry focused on providing broad and innovative technology solutions for the data and artificial intelligence ('AI') era," with solutions that "range from client devices and peripherals to infrastructure solutions across servers, networking, and storage." It states that it designs, deploys and supports "secure, integrated solutions that extend from the edge to the core to the cloud," delivering "AI-optimized, software-defined, and cloud native infrastructure solutions across a broad partner ecosystem." The stated vision is "to become the most essential technology partner," executed by "leveraging our strengths to extend our leadership positions and capture new growth," anchored in a corporate purpose "to create technologies that drive human progress." ### Independent characterisation Dell is, at its economic core, a high-velocity systems integrator and distributor of other companies' silicon. It does not manufacture processors, GPUs, memory or flash; it buys them, engineers systems and racks around them, and monetises the assembly, integration, deployment, financing and multi-year support that surrounds them. This is a low-gross-margin, high-asset-turnover, negative-working-capital business model. In FY2026 consolidated gross margin was 20.0% and operating margin 7.2%, while asset turnover was approximately 1.25x and the current ratio 0.91 — Dell is funded in substantial part by its suppliers through $33.6bn of accounts payable at year end, rising to $49.7bn by 31 July 2026. Three characteristics distinguish the current business from the Dell of five years ago: **First, mix has inverted.** ISG overtook CSG as the larger segment in FY2026 ($60.8bn versus $51.0bn) and by Q2 FY2027 was more than twice CSG's size ($31.8bn versus $15.0bn). Within ISG, AI-optimised servers — a product category that did not exist as a separate disclosure line until Q4 FY2026 — generated $24.7bn in FY2026 and $32.5bn in the first half of FY2027 alone. **Second, the revenue model has bifurcated.** Product revenue grew 27% in FY2026 to $90.4bn while services revenue declined 4% to $23.1bn. The services decline is a reporting artefact of the wind-down of VMware resale and the disposal of Secureworks rather than a deterioration in attach rates; ISG and CSG services both grew. Nevertheless, the services line — historically the margin ballast of the business — is now only 20.4% of revenue, down from 25.3% in FY2025, and 12.5% of revenue in Q2 FY2027. Mix is moving away from Dell's most profitable revenue. **Third, consumption models have become material.** The Dell Payment Solutions portfolio offers utility, subscription, as-a-Service, lease, loan and immediate-pay structures. Dell Financial Services funded $11.9bn of originations in FY2026 and carried a $14.3bn global financing-receivables portfolio at year end. Financing receivables grew by $6.4bn in the first half of FY2027 alone, a direct consequence of large AI transactions carrying longer payment terms — this is why adjusted free cash flow ($11.3bn in H1 FY2027) diverges so sharply from unadjusted free cash flow ($4.1bn). ### Value chain position, customers and end markets Dell occupies the systems-integration and channel layer between component suppliers (NVIDIA, AMD, Intel, Broadcom, Micron, Samsung, SK Hynix, Western Digital, Seagate) and end customers. Manufacturing is a hybrid: Dell owns plants in the United States, Malaysia, China, Brazil, India, Poland and Ireland, and also uses contract manufacturers, principally in Asia, purchasing components and on-selling them to those manufacturers — an arrangement that generates large non-trade receivables and is disclosed as a credit-concentration risk. Customer segments are large global and national enterprises, government agencies and public institutions, educational institutions, healthcare organisations, small and medium businesses, and consumers. In FY2026 approximately 40% of net revenue was generated through channels other than the direct sales force — value-added resellers, systems integrators, distributors and retailers. Two customer cohorts now drive the growth narrative and both concentrate risk. The 10-K states plainly that AI solutions "have been purchased primarily by a small number of larger customers and cloud service providers," that large orders "may occur in some periods and not others," and that such transactions "may also involve larger amounts of credit or longer payment terms than have been typical for our business." Management has separately characterised the AI pipeline as a mix of "neocloud, sovereign and enterprise customers."
Company Headquarters: United States Founded: 1921 Workforce: ~7,500 Company Working: Master Lock Company LLC. is a global leader in the development and manufacturing of security products, including padlocks, combination locks, and other security solutions. Master Lock's product line includes a wide range of padlocks, safety lockout devices, digital locks, and other security solutions for residential, commercial, and industrial use. The company has a strong reputation for quality and durability, and its products are widely used in schools, hospitals, airports, and other high-security environments. In addition to its core product offerings, Master Lock provides services, including key cutting, lock repair, and customized security solutions for specific customer needs. The company is committed to innovation and strongly focuses on research and development to stay ahead of evolving security threats. Master Lock is owned by Fortune Brands innovations, a leading home and security products company that also owns other well-known brands such as Moen, Therma-Tru Doors, and Fiberon Decking.
84 interactive charts drawn from the ABF Packaging Substrates Market dataset — market size, each segment breakdown, and every region and country by segment. Open one to read its full data table and download it.
Global ABF Packaging Substrates Market By Region
Global ABF Packaging Substrates Market By Layer Count
Global ABF Packaging Substrates Market By Package Architecture
Global ABF Packaging Substrates Market By Application
Global ABF Packaging Substrates Market — North America by Country
Global ABF Packaging Substrates Market — North America by Application
Global ABF Packaging Substrates Market — North America by Layer Count
Global ABF Packaging Substrates Market — North America by Package Architecture
Global ABF Packaging Substrates Market — U.S. by Application
Global ABF Packaging Substrates Market — U.S. by Layer Count
Global ABF Packaging Substrates Market — U.S. by Package Architecture
Global ABF Packaging Substrates Market — Canada by Application
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